DE2150511A1 - PROCESS TO REDUCE THE SYSTEM-RELATED PHASE FLUCTUATION (JITTER) DURING RECEIVING RECOVERY OF THE PLESIOCHRONOUS PRIMARY CYCLE OF SEVERAL SENDING SIDE AT A MUCH HIGHER PRIMARY ORDER COMPOSED - Google Patents

Description

Procedure for reducing the system-related phase fluctuation (jitter) in the recovery of the plesiochronous primary clocks at the receiving end of several at the transmitting end primary time division multiple systems combined to form a higher order time multiple (Addition to patent application P 20 23 656.0) The main patent has a method for Reception-side recovery of the plesiochronous primary clocks of several transmission-side primary time division multiple systems combined to form a higher order time multiple to the subject. The recovery takes place according to the main patent by fading in or fading out individual clock pulses to or from a middle, locally generated Clock frequency based on the correction signals contained in the received multiplex bit stream in two identically structured, at n times the clock frequency of the one to be won Correction stages working in the primary clocks. The 1st level of correction is for all primary systems assigned centrally and gets its setting commands from a comparison of the received Multiplex-bitf1 @ stream f2 with a needle pulse train, which by subdividing m des in the 1st correction stage already roughly corrected primary f1 clock (n # f1 #) with the divisor numbers n and m and anm closing differentiation is obtained, with m <n and a correction of + 1 bit takes place at a distance of m. Each of the second correction levels is individually assigned to a primary system and gets its setting commands from a comparison stream of those contained in the multiplex bit Correction signals for the respective primary cycle with from the cycle sequence f1; m pulse sequence obtained centrally by inversion and division. ble present The additional invention poses the task, which by fading in and out (positive-negative-pot technique) to reduce the phase fluctuation (jitter) caused by this method.

According to the additional invention, this is done in that for each irimary system depending on the time interval between two successive correction commands the pulse repetition frequency closest to the required correction frequency Pulse sequences generated centrally by 1 from the pulse sequence ~~ by simple frequency division is selected.

The basic idea of this additional invention is, as in the previous one Additional patent application P 21 36 930.2, the correction frequency for each of the primary systems individually assigned second correction level to choose each so small that they is just sufficient to correct the measured clock deviation.

In contrast to the patent application P 21 36 930.2 is not after 32 correction pulses interrupt the correction until the next command "e" or "a", instead, the clock is corrected further with the next lower correction frequency. @ during aiso in the process according to the mentioned additional patent application always more or less short pauses after a correction are learned from the new one constantly corrected. Only change at this very low correction frequency Procedure correction and pause.

In this method, an approximation to that for a clock deviation of (. Additional patent application 1 21 36 930.2 and NTZ 6/1971, '.

318) necessary mean correction frequency is reached.

A circuit arrangement for carrying out the procedure is provided for Primary system two sliding registers functioning as adding units on either side of one central storage cells each required via a gate circuit Mark the stage of a frequency divider that generates the correction frequency and one for each Counter for on and off

Fade out to count the number of times required for a correction of the clock obtained 32 correction commands required by one clock pulse.

To further reduce the system-related phase fluctuation (jitter) a special design of the frequency divider circuit is advantageously provided. This consists of a ge-I, linseed divider stage with a divider ratio of 5: 1 and two downstream parallel divider branches with divider ratios of 2: 1 and 3: 1, each of which is followed by further divider stages with a divider ratio of 2: 1.

The essence of the invention is described below with reference to four figures shown: Figure 1 shows the block diagram, Figure 2 shows in a diagram the reduction in the jitter amplitude that can be achieved with the method in the exemplary embodiment of Figure 1, Figure 3 shows the function of the circuit using a timing diagram and FIG. 4 shows a frequency divider for further reducing the T-phase fluctuation.

In Figure 1, the frequency divider is below the interrupted Line assigned centrally to all primary systems.

The one shown here for obtaining the 1 different correction frequencies Divider corresponds to the frequency divider level in the main patent. The in the main patent A differentiating stage connected downstream of the frequency divider is here for each correction frequency generated necessary.

The one in Figure 1 of the main patent below the second, each Logic circuit I1 shown specifically for the correction stage associated with the primary system is replaced by the one above in the case of the Sdhaltungsanordnung according to the additional patent the arrangement shown in broken line.

The commands generated by a detection circuit in the demultiplexer "e" and "a" are each stored in a flip-flop (FF1, i'F2) and with the above a delay line VZ corresponding to delayed clock f2, = 3.2 kHz as Command for setting the cut registers SR I and R II requested. Since in the both shift registers only a single stage an "L", all other stages one "O" will be one of the AND gates connected to each memory cell T1 switched through if one of the levels + 1 to + 4 was marked with "Lu.

Via the second input of the relevant AND gate T1, the selected correction frequency as a sequence of differentiated in pulse shaper stages J Pulses via the associated OR gate T2 to output A + or A. Be at the same time the pulses are counted with the respective counter Z1 or Z2. This counter gives way 32 counted pulses each via a further pulse shaper stage J and an OR gate T3 a shift clock pulse to the shift register so that the written "L" is shifted in the register to the next level in the direction of level 0. By a monitoring circuit, not shown, ensures that in the shift register only one "L" is included. To move this marking "L" in the one or the other direction are the lines LS (left slide) or RS (right slide) intended.

The effect of the above-described method according to the invention is illustrated in FIG. 2. FIG. 2 shows the dependency of the jitter amplitude (Jmax) from the difference # f between the primary and converted secondary pulse train according to the relationship given above, or depending on the number of 1 tl of Takeovers between two incoming or outgoing

Skip commands, where # results from the relationship 3200Hz # # @@ The systematic jitter J5 \ resulting from the Clock recovery results from the method according to the main patent and the one after of the present additional patent application reduced jitter | Jr | for 4 correction frequencies.

FIG. 3 shows the timing of a setting of the shift register shown. From this it can be seen that the divider T is synchronized so that a command "e" or "a" not with a shift pulse from one of the counters Z1 or Z2 of FIG. 1 coincides, since otherwise the one in one of the flip-flops FF1 or FF2 would be closed Saving command "e" or "a" cannot be accepted.

The timing diagram is based on the assumption that the fourth stage of the shift register SR II that contains (see Fig. 1).

The top line of the timing diagram shows the synchronization pulse, the is derived from the upper frame (marker). For the following lines of the timing diagram it is further assumed that in the information originating from the primary system 3 a Pulse (+ S information) would have to be displayed.

This pulse sets the flip-flop FF2 in the third row.

The fourth line shows that from the pulse train f2 'through a delay element V2 obtained pulse sequence f2, (see Fig. 1). This pulse sequence f2 'becomes a left shift clock LS for the shift register 3R I or SR II derived and at the same time the flip-flop FF2 (third line) reset. From the last and penultimate lines of the timing diagram it can be seen that a reverse shift clock is generated after 32 correction pulses.

Line further reduction can be achieved using a frequency divider according to Figure 4. Here, the divider T must be designed so that the necessary Total divider ratio is 1 1 or. The number of stages of the shift register -10 15 ters increases by two levels for each new frequency divider level. This makes it possible to further reduce the jitter shown in FIG. since the maximum values in this representation are reduced to around 3% and accordingly all values are below the curve shown in FIG.

Claims (3)

patent claims experienced to reduce the system-related phase fluctuation (jitter) in the recovery of the plesiochronous primary clocks at the receiving end of several at the transmitting end Primary time division multiple systems combined to form a higher order time division by fading in or out individual clock pulses to or from a central one locally generated clock frequency due to contained in the received multiplex bit stream Correction signals in two identically structured signals at n times the clock frequency of the primary measures to be obtained, of which the 1st correction stage is assigned centrally to all irimärsystemen and their control commands from a comparison of the received multiplex bit stream f2 with a needle pulse sequence ~~ that by retarding the primary measure, which was already roughly f1 corrected in the 1st correction stage (n # i1 #) with the partial terms n and m and then @@ differentiation gained where m <n and a correction of +1 with m at a distance of, and of which the 2. f1 correction level is individually assigned to a primary system and their setting commands from a comparison of those contained in the multiplex-to-stream Correction signals for the respective primary cycle with one of the cycle sequence f1: m refers to the pulse sequence generated centrally by inverting and @@ ilung, according to patent application P 20 23 656.0, d a d u r c c g e k e n n n z e i c h n e t that for each primary system depending on the time interval two consecutive Correction commands the pulse repetition frequency that comes closest to the required correction frequency of 1 pulse sequences generated centrally from the clock sequence f m by simple frequency division is selected. 2. circuit arrangement for performing the method according to claim 1, characterized in that two functioning as an adder per primary system Shift register (SR I, SR II) on both sides of a central memory cell (O), each of the required correction frequency (f1 ..... f4) mark the generating stage of a frequency divider (T) and one counter for each (z1, Z2) for counting the number of clock pulses required to correct the clock pulse obtained 32 necessary correction commands are provided (Figure 1). 3. Circuit arrangement according to claim 2, characterized in that the frequency divider (T) from a common divider stage with the divider ratio 5: 1 and two downstream parallel divider branches with the divider ratios 2: 1 and 3: 1, each of which has further divider levels with the @ eiler ratio 2: 1 follow (Figure 4). L e r s e i t e