DE2115248A1 - Semiconductor component and method for its manufacture - Google Patents

Description

Dipl.-Ing. H. Sauerland ■ Dr.-Ing. R. King

Dipl.-Ing, K. Bergen

Patent Attorneys 4doo Düsseldorf Cecilienallee 7S Telephone 43 27 3a

Our file: 26 571 March 29, 1971

RCA Corporation, 30 Rockefeller Plaza, New York , NY 10020 (V.St.A.)

"Semiconductor component and process for its production"

The invention relates to junction transistors and integrated ones Circuits, in particular, the invention shows a junction transistor, which is an emitter circuit high short-circuit current gain (beta) can develop, as well as a method of making such transistors and integrated circuits equipped with these transistors.

It is well known that common emitter short circuit current gain (commonly called beta gain) of a junction transistor is inversely proportional to the base thickness of the transistor. So far, diffusion transistors, which are characterized by high beta reinforcement, due to the formation of thin base layers under more precisely Control of the base and emitter diffusion processes established. Integrated circuits with transistors that have different beta values, were previously produced by first putting all the base layers up to the same Diffused in depth, then the emitters of the transistors with higher beta values partially diffused in and Finally, these diffusion processes with simultaneous diffusion of the emitters of the transistors are less Beta values have ended. In other words, the tranai-

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disturbances with a higher beta value were produced by that their emitters were diffused deeper than those of the transistors with lower beta values3. It has previously been difficult to produce high beta transistors individually or in integrated circuits with sufficient Quality and good yield. This is to be achieved with the present invention.

Be it as a transistor or an integrated circuit The component according to the invention is one of two in mutually spaced pn junctions in a body of semiconductor material through a near one in the body formed groove defined area arranged. The depth of the groove i3t easy to adjust, and the effective The basic thickness of the component depends on the depth of the groove and not on the time, temperature or any other parameter determined by a diffusion process. In an inventive Integrated circuit can transistors with different beta values in a single diffusion process be made by changing their emitter areas diffused through the surfaces of grooves of different depths.

A controlled formation of the grooves can be achieved by a anisotropic etching process can be achieved »If the semiconductor material is silicon, the grooves can be made by anisotropic Etch a (100) face to be formed, becoming V-shaped Grooves result which are limited by (111) surfaces.

1 shows a partial cross section through an integrated circuit with a conventional and an inventive transistor;

Z and 5 represent the method step a of the method according to the invention for producing the transistor transistor or

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an integrated circuit; and

4 shows a partial cross section of a second embodiment of the transistor structure according to the invention.

The integrated circuit 10 shown in FIG. 1 comprises a conventional transistor 12 and a transistor 14 according to the invention. The circuit 10 has a substrate 16, in this case of the p-conductivity type, on its surface 18 in a conventional manner an epitaxial n-layer 20 is applied. The epitaxial layer 20 has a surface 22 which is used in the case of silicon as the semiconductor material preferably approximately parallel, i.e. within 0.5 ° i, of the crystallographic planes (100) in the silicon runs.

The transistor 12 has an embedded collector connection area 24, which is made in a conventional manner, i.e. by diffusing an n + type region into the p-type substrate 16 is made prior to the formation of the epitaxial layer 20. During the build-up of the epitaxial layer 20, foreign atoms diffuse from the substrate into the layer 20 and build up the region 24 in the area shown in the drawing Training on. A connection between the surface 22 is established via a diffused n + type region 26 and the embedded collector terminal area 24 is made. The transistor 12 has a base region 28 of the p-conductivity type, which together with the material of the epitaxial layer 20 has a collector pn junction 30 forms »Within the base area 28 there is a Emitter region 32 of the n + conductivity type, which together forms an emitter-pn junction 34 with the base region 28. The base thickness of the transistor 12 is ala the distance between the bitter pn junction 34 and the collector pn; The transition 30 is defined and determined according to the diffusion depths of the regions 28 and 32.

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The transistor 14 according to the invention can be produced at the same time as the transistor 12 and have a beta gain value which differs from that of the transistor 12. In accordance with the transistor 12, the transistor 14 also has an embedded n + collector connection area 36 and a diffused n + type zone 38, which establishes the connection to the area 36. The collector material of transistor 14 is the original n-type material of the epitaxial layer 20. In addition, 14 is similar to the transistor to the transistor 12 in that it has a base region 40, which can with the base ψ region 28 of the transistor are diffused 12 simultaneously , and accordingly forms a collector pn junction 42 which, with respect to the surface 22, is at the same depth as the collector pn junction 30 of the transistor 12.

The emitter of transistor 14 is different from that of the Built transistor 12, and it is precisely this different training that causes the difference in the beta value. With the transistor 14, a groove 44 is formed in the epitaxial layer 20 near the surface 22. The groove 44 is through defines the angled surfaces 46 and 48 which are inclined to the surface 22 at the same angle. If the semiconductor material is silicon and the surface 22 is oriented parallel to the crystal planes (100), so the surfaces 46 and 48 to the crystal planes (111) or (TT1) run parallel in the silicon. The surfaces 46 and 48 meet in a cutting line 50 which has a predetermined distance from the surface 22.

An emitter region 52 of the transistor 14 can be formed simultaneously with the emitter region of the transistor 12. In transistor 14, however, emitter region 52 is formed by diffusion of conductivity modifiers through the surfaces 46 and 48 of the groove 44 are formed. This creates between

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see the emitter region 52 and the base region 40 pn junction 54, the boundaries of which are spaced apart and essentially parallel to the surfaces 46 and 48 of the groove 44 are «These boundaries converge at a point 56, the one from the collector-pn junction 42 through the The depth of the groove 44 has a certain distance.

The effective base thickness of the transistor 14 is smaller because of the diffusion of the emitter region 52 through the groove 44 than that of transistor 12. Accordingly, transistor 14 has a higher beta than transistor 12, Die The size of the difference can be adjusted by changing the depth of the groove 44 accordingly.

A controlled production of grooves similar to groove 44 and thus of the emitter regions diffused through the groove can be achieved by an anisotropic etching process shown in FIGS. The production of a transistor _{according to the invention, for example I4 f,} begins in the same way as for the conventional transistor and also corresponds to conventional processes with regard to the subsequent Basls diffusion step. The subsequent procedure is new.

As shown in Fig. 2, the first step is the new stage in the process of producing an emitter mask coating 60 on the surface 22 of the epitaxial layer 20, at the one provided for the emitter region 52 There is an opening 62 in the coating 60. The opening 62 can be similar in plan to that in conventional Be formed emitters. The opening 62 is preferably an elongated slot, the flanks of which the Cut surface 22 of the epitaxial layer along and parallel to the (11) planes of silicon. The (111) and (TT1) planes are indicated by dashed lines in Fig. 2; she loved

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each at an angle oC to the normal of the surface the epitaxial layer.

The next step in the new method is that the uncovered areas of the surface 22 are brought into contact with an anisotropic etchant. A preferred etchant is a mixture of water, an etchant such as sodium hydroxide solution and an alcohol such as n-propanol. In particular, the etchant can be a mixture of about 61 mol percent water, about 35 mol percent sodium hydroxide solution and about 4 mol percent N -Be propanol. This substance etches silicon regardless of the resistance of silicon in the (300) direction at a speed of about 60 micrometers per hour at a temperature of 85 ^° C. Under the same conditions, the substance etches silicon in the (111) direction only about 3, 6 microns per hour. The directions which have similar properties to the (111) direction, namely, those defined by the Miller indices (1T1), (TTi), (TU), etc., are similarly affected. The etchant attacks silicon dioxide only insignificantly.

The surface treatment with the "anisotropic etchant" results in the removal of the material in the form of a symmetrical wedge, the (111) and (TT1) surfaces of the silicon being exposed in the present case, The The etch process is self-limiting and effectively stops when the apex 50 is between these surfaces is reached.

The distance between the apex 50 and the surface 22 depends on the width of the opening 62 in the mask cover 60, Accordingly, other transistors similar to transistor 14 can be formed on the same device 10, wherein the groove depths of the transistors simply by choosing the

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suitable opening width can be determined in the mask layer.

Upon completion of the etching step, donors are deposited on surfaces 46 and 48 of the resulting wedge-shaped or V-shaped groove 44, in the same Way as with the formation of the emitter of conventional 'npn transistors. The donors are then through the flank surfaces of the groove 44 diffuses into the silicon to the desired depth, and the in Fig. 3 training shown. The connection openings and the connection metallization are then made using conventional methods of the component created.

If further transistors with grooves of different depths are provided in the component 10, it is possible to use different base thicknesses and therefore different beta gain values in a single diffusion process of these transistors are created. Since only one etching and one diffusion process is required to form all of the transistors is, higher yields and better results can be expected.

Fig. 4 shows another embodiment of the invention Transistor, which is useful for higher emitter currents. The transistor 80 shown in Fig. 4 is similar to that 1 and differs from the latter in that it has a plurality of separate emitter regions owns. In particular, transistor 80 includes a substrate 82 and an epitaxial layer 84 with a top Area 86 on. The active regions of the transistor 80 comprise a buried collector region 88, a collector connection region 90 and a base region 92, all made by conventional methods. At this Embodiment is a relatively large base area

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92 used. Within the base area are nearby . A plurality of grooves 94 are formed on the surface 86 with the aid of the anisotropic etching process described above. Next to each of the grooves 94 has an emitter region 96. A metal layer 98 connects the emitter regions 96 so that im The result is multiple transistors connected in parallel.

The transistor and integrated circuit structures of the invention can also be realized with semiconductors other than P silicon, and the new process allows can also be carried out with anisotropic etchants other than the caustic etchants specified above. As an etchant For silicon there are also mixtures of water, an amine (e.g. hydrazine, ethylene diamine, etc.) and a complexing agent suitable as pyrocatechol. Gallium arsenide and germanium speak anisotropically to mixtures of hydrofluoric acid, Nitric acid and water.

The expression “(111) crystal planes ¹¹ , as used in the following claims, is intended to encompass all those planes which have identical digits in Miller’s notation, ie the (TT1), (1Ti), (IIT) W etc. planes .

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Claims (13)

RCA Corporation, 30 Rockefeller Plaza, New York . NY 10020 (V.St.A.) Claims; . jp "Semiconductor component with a body made of semiconductor material, which has a flat surface and a first region of a first conductivity type and a second region of the of the opposite conductivity type, between which a first pn junction ending at the flat surface is formed, characterized in that that in the body a from the surface (22) extending to a point remote from the surface (50) formed groove (44) and a third region (52) of the first conductivity type near the groove in the body is provided that forms a second pn junction (54) with the second region (40), the second pn junction ends at the surface (22) and is at a predetermined distance from the first pn junction (42). 2. Component according to claim 1, characterized in that that the groove (44) is formed by planes (46, 48) which are at an angle to one another and which are formed by extend from the surface (22) and meet at a point remote from the surface in a cutting line (50), both planes being at the same angle to the surface (22), and that portions of the second pn junction (54) run at a distance and essentially parallel to the groove planes (46, 48), 3. The component according to claim 2, characterized in that the semiconductor material is silicon is that the surface (22) is substantially parallel to 109843/1633 the (100) crystal planes of the body and that the at an angle to one another planes are arranged essentially parallel to the (111) crystal planes of the body are. 4 "Component according to claim 3, characterized in that that the first pn junction (42) has a substantially parallel to the surface (22) has flat section. 5. Component according to claim 1, characterized in that that the first area is a collector area, the second area is a base area and the third area an emitter area is " 6. The component according to claim 5, d a d u r c h characterized in that the base-emitter ^ "; ^ transition in the runs essentially parallel to the surface of the groove (44) * 7 «component according to A ^rr! 'r ^ 5, marked _£ . that the groove (44) is V-shaped. "8, component according to claim 7, characterized in that the V-shaped groove (44) is symmetrical. 9. Component according to claim 1, with at least two semiconductor components, at least one of which has a first region of a first conductivity type and a second region of the of opposite conductivity type, between which a first pn-overp, ending at the flat surface gang is formed, characterized that the body has at least one groove (94) formed by planes at an angle to one another. 109843/1633 with the planes forming the groove extending from the surface (86) and up to one remote from the surface Line of intersection and that a third area (96) of the first conductivity type near the groove in the body is provided which forms a second pn junction with the second region (92), portions of the second pn-junction run at a distance and essentially parallel to the groove planes and at one around a predetermined one Measure from the first pn junction distant point collide. 10. The method for producing a semiconductor component according to one of claims 1 to 9, characterized in that that a semiconductor body is produced with a first pn junction, a part of which with Spaced and substantially parallel to a surface of the body that an etch-resistant mask coating is applied to the surface, a portion of which the surface remains uncoated that an anisotropic etchant remains on the uncoated part of the surface is operated to expose planes at an angle to the surface and that conductivity modifier diffused into the body through the exposed surfaces, with a second pn junction is formed in such a way that sections of this second pn junction are spaced apart and essentially parallel to the exposed levels and at a predetermined distance from the first pn junction. 11. The method according to claim 10, characterized in that the semiconductor material is silicon is that the surface is oriented substantially parallel to the (100) crystal planes of the body, and that the masking coating is formed with at least one straight edge which is essentially parallel to the (111) 109843/1633 Crystal planes of the body is oriented " 12. A method for producing an integrated circuit with at least two transistors with different values the short-circuit current gain in emitter circuit, characterized in that a body made of monocrystalline silicon with a substantially parallel to the (100) crystal planes of the body Main surface is produced, the body having at least two mutually spaced areas of a conductivity type near the main surface, each of which forms a pn junction with the body, that an etch resistant mask coating is applied to the major surface in which near each area of the a conductivity type two openings are left free, each of the openings with spaced apart, parallel edges is formed which are oriented essentially parallel to the (111) crystal planes of the body and the distance between the edges of one opening differs from the distance between the edges of the other opening, that on the parts of the surface exposed through the openings a substance is applied which silicon atoms removed in the (100) planes to thereby create V-shaped grooves in the body and that conductivity modifier of the conductivity type opposite to the two mutually spaced regions through the groove surfaces are diffused into the body to areas of the opposite conductivity type in the body and pn junctions with the two mutually spaced regions of the first conductivity type form. 13. The method according to claim 12, characterized in that the substance is a mixture of water, a caustic and an alcohol. 1098A3M633 Blank page