DE2036680B2 - CIRCUIT ARRANGEMENT FOR DECODING A CODE FORMED FROM BIPOLAR CHARACTERS - Google Patents

Description

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The present invention relates to a circuit, from the German Offenlegungsschrift for decoding information which has become known 1462 869, the status bits as in a suitable for transmission, from bipülä- start-stop characters a counter in the receiver for ren characters generated code and to supply the locally generated clock pulses in a. If this counter has a form corresponding to a binary code, then this counter is processed during part of the reception by gradually counting more or less of the incoming number of clock pulses than a given shift register in a first bit Via a logic code converter switching either one pulse is suppressed or one converted and given to a second shift register pull clock pulse. This ensures that results are obtained from which the decoded information for io in each case the last Bii of the received word is also processed synchronously, also taken step by step,
will. For systems without these status bits, as is the case today

In transmission systems for telecommunications in PCM systems, on the other hand, in addition to instantaneous values of signal waves, a word synchronization group of pulses must be represented in a code. The simplest form of a code is a binary code, the position can be recognized and corrected.
which can be represented by the series α2 ⁰ + b2 ¹ + c2 ² + d2 ^s + ... While on the transmit side the clock of the occurring can be represented, in which the coefficients a, b, c, d, ... code words are still clearly recognizable, lose either 1 or 0 and, in technical terms, all the corresponding information when reversing the value 1 with a pulse and the value 0-20 conversion, so that an uncertainty with a pulse gap is displayed during decoding. On the sea side, the synchronization arises. The task on which the invention is based is based on the instantaneous value of the signal, and accordingly the selection of a code word and, on the receiving side, to ensure perfect synchronization at the receiving ovt.
voltage or current value. According to the invention, this is achieved in that

After the transmission, it is generally necessary- a test circuit to monitor the first Hch, the code, d. H. the pulses that represent the code in the shift register stored bit sequence is present, ask to regenerate before decoding; avoid the one for entering the At least this must be in one or more intermediate information generated by the code converter in the Stations also happen. A regeneration 30 assigns required clock pulses to second shift registers a reinforcement as an introductory process. or switch off.

Then follows a limitation between two. The invention makes use of the fact that in the

Levels, whereby from each incoming pulse mentioned binary encrypted ternary code

a narrow band, roughly halfway through the pulse ampli- the combinations LLOO, LLLL, 0000 and 00LL

tude, is cut out. For the gain 35 for reasons of ambiguity not be used

Both direct current and alternating currents are available. The test circuit therefore only has to check

current amplifier on. The former are in the case of whether in the first shift register one of these combination

necessary high frequencies of about 100 MHz to be able to recognize that the

not stable enough, and the second synchronization is not correct. Assume from the

If the zero level of the impulses is lost, the following bit sequence would be sent to the transmitting station:

can be restored with some effort. _n , _{n nmr rnnr} ηττηηηητ

. j. f ~. .. j. j, - ,. j. _yv . ll ^^ L UUUjL jLUUjL \ JLäL, \ J UUU / - *,

For these reasons, among other things, the request is made to the code provided for the transmission but in the receiving circuit the transfer would be that the zero level is automatically shifted by two bit positions so that the first remains constant. Code that meet this condition are 45 shift registers a bit sequence of the type
For example, all those in which each code character combination receives the same number of pulses - ^{Lim [) LLO {) LOL} · · ·
shows. In addition, binary-encrypted messages would also be passed to the code converter. The test circuit ternary code, in which the three values 0, 1, 2 or from the first group of four must recognize the wrong - 0, + -1 through 01, 00 alternating with 11 and 50 synchronization and the transfer rate around 10, this condition . While shifting a bit position, so that of the second only three bits of the second for the coding and decoding of moments group of four are written into the first shift register tanwert a binary code is most advantageous. After this first correction tet. If one of the two is specified for the transmission, the sequence Of) LL needed n code in the first shift register would be preferable. This requires the 55 stored on both sides, which causes a second correction and the transmission line, the installation of code converters, causes another shift, so that the third group of four learns correctly in this or from encoders and decoders for informational example, which are already in binary-encrypted form incurred is entered with LOOL,
and also reused at the receiving location. With reference to the drawing, the following is explained in more detail using an exemplary embodiment, for example in the case of data transmissions for finding. Computing systems. These bodies cause a doing shows

Conversion of a first specific number of F i g. 1 a circuit diagram of a decoder and

Code signal elements of a given temporal F i g. 2 is a timing diagram.

Duration in a second specific number of code A first shift register SCHI consists of four

Signal elements with the same duration. 65 bistable circuits Dl, Dl, D3 and DA, each

For the synchronization of the clock pulses it has the same structure and one piece of information for each code transmissions, in which so-called status bits are also present between the word input D and a clock input C with data bits. The two outputs Q and "Q are always in

I 4

antiphase switching position. The internal control is in the AND gate 1/6 the indirect output 2 «Jerbi-

in such a way that the respective information at the information stable circuit D 4 and the output of the uunw-

input with a clock pulse at clock input C Tores01, in AND gate Ul the direct outputs

is fed to the output, which is why this from the bistable circuit Dl and the output aes

output Q also as a direct output, on the other hand the output 5 OR gate 02 and in the AND gate the direct one

gang 2 is referred to as the inverted output. Output Q of the bistable circuit D 4 and the / vus-

The incoming line is connected together via the input E gang of the inverter II
connected to the information input D of the bistable switching device D1 in the two further AND gates U ν and u xu. The direct output Q of these are the outputs of the previously described bistable circuit Dl controls the information input io AND gates US ... U 8 connected in pairs of the bistable circuit D 2, whose direct tet by the outputs of the AND gates US \ Line -it / ο output Q the information input D of the bistable to the AND gate t / 9 and the outputs of the UINU-lore circuit D 3 and its direct output Q to the In- Ul and t / 8 to the AND gate t / 10 ..The formation input D of the bistable circuit D4. The output of the AND gate t / 9 is connected to the Mellein-So that the following bistable circuit 5 of the bistable circuit D1 takes over and the output device with a clock pulse at the clock input C is the one at the AND gate t / 10 with the control input , i of the bidirectional outputs of the preceding bistable stable circuit D 6 verbu-.uen. The control input J circuit standing logic value in the known of the bistable circuit D 5 confused ¹ over the UJNlJ-1 or way. Uli through the information from the two inverters

The second so / 1 and / 2 is also controlled in a corresponding manner.

Shift register SCH 2 with the three bistable switching The three AND gates U 9, t / 10 and Uli received

lines D 5, D 6 and D 7 built up. The bistable forwarding pulses each at a third input

In contrast, circuits themselves have an AND gate U 12.

The test circuit PS consists of a bistable value directly on the switching side, which is connected to the inverted circuit!) 8, an AND gate with inverücrtem output 2, is fed. The gang t / 13 and from an inverter / 3. In the AND-Ior information input D of the bistable circuit Dl UU the transfer clock from the AND-Ior is connected to a positive potential source, word / 12, the information from the two OR-loren through with each clock pulse at the clock input C of the Ol and O 2 in the code converter CW and the direct 'ogical value L is written. The direct output Q of the bistable circuit D 8 2 together output Q is connected to the information input D of the. The output of this AND gate L 13 is connected to the bistable circuit D 6 and its direct output from the information input D of the bistable circuit is connected to an information input D of the bistable D8. The clock input C receives the clock circuit D 5 connected. The direct output Q impulse from a clock pulse input TP via this last-mentioned bistable circuit D5 is to 35 inverters / 3.
an output A. The clock pulse sequence for storage in the

With this arrangement, the first shift register SCHI becomes from the pulses

inputs S with the logic values entered by the clock pulse input TP via a first divider

Clock pulse sequence at clock inputs C is generated step by step Tl with a division ratio of 3: 1,

inverts the output A, starting with the 40 and the clock pulse sequence for the Ausspeiclierung out

logical value at the output β of the bistable switch the second shift register SCH 1 is made from a

device D 5, supplied. Divider stage Tl, which consists of two dividers with a divider

The code converter CW consists of four AND gates with a ratio of 2: 1 each. The feed

Ul ... U 4, two OR gates with inverted output of the pulses from the clock pulse input TP to

gear oil, O2, two inverters / 1, II as well as from seven 45 second dividers Tl takes place via a gate circuit TS,

AND gates with inverted output t / 5 ... U 11. which are represented as AND gates with inverted output t / 14

In the AND gate U 1 are the direct output Q from which is set and from the direct output Q the bi-

bistable circuit D1 and dtr indirect output 2 labile circuit D 8 is controlled,

from the bistable circuit Dl merged, that the transmission pulses for storage

while in the AND gate t / 2 the direct output of the 50 generating into the two shift register SCHI

bistable circuit Dl and the indirect off AND gate t / 12 summarizes the output pulses from the

gang 2 of the bistable circuit Dl merged Teiiersuife Tl, from the divider stage Γ2 via a

are. Accordingly, the bistable circuits are inverters / 4, the pulses from the clock pulse input TP

D 3 and D4 are given to the AND gates t / 3 and t / 4. as well as a pulse sequence from the divider stage Tl after

The outputs of the AND gates Ul and Ul are related to the first divider TlA over 55. So that everyone will

the OR gate Ol fed to the inverter / 1 and the twelfth pulse at the clock pulse input TP to the

the outputs of the AND gates U ^ and t / 4 via the AND gates £ / 9, t / 10 and Uli in the code converter CW

OR gate O 2 to the inverter 11. The OR gates and the AND gate U 13 in the test circuit PS

Ol and 02 only then give a logical L, guided.

if both bistable switches combined with it are 60 For the explanation of the mode of operation,

linesDl, Dl or D 3, D4 the same logical values only only the implementation of the first shift register

contain. SCHI look at the second shift register SCH 2

Six AND gates with inverted output, which tet without going into synchronization. With

AND gates US .. .UW are used to control the pulses from the first divider T 1 is the

Control inputs 5 of the bistable circuits D 6, D 7 65 input E pending information in the first

in the second shift register SCH2. In this case, SCHI are written into the shift register. The AND gates

AND gate US the direct exits of the bistable t / l and Ul give the at their exit. logical

Circuit D1 and the output from the inverter / 1, Wen O, if the two bistable circuits D 1

and Di represent equal logical values. The same also applies to the AND gates U 3 and t / 4 for the logical values of the bistable circuits D 3 and D 4. If the logical values in the bistable circuits are not the same, the corresponding AND gate outputs the logical value L. By combining the AND gates Ul, Ul and t / 3 in pairs. 1/4 give the OR gates Oi. Ol only then starts from a logical value L when the same values are present in two of the bistable circuits D I. Dl or D3, D4. With unequal values in the bistable circuits D 1 and Dl , the AND gate U 5 receives the value from the direct output Q of the bistable circuit D1. so that with the combination OZ. at the output of which the value O appears and with the combination LO the value L: thus the inverted value of the output Q of the bistable circuit D1 appears at the output of the AND gate US. Through the AND gate V 6, the logic value of the bistable ao circuit D 4 is forwarded as a function of the value of the ODHR gate Oi , so that with the same values in the bistable circuits D 1 and D 2, the logic value from the bistable circuit D 4 is forwarded. In the event of unequal values in the bistable circuits D 1 and Dl , a logic 0 is obtained at the output of the AND gate 1/6, regardless of the value stored in the bistable circuit D 4. The subsequent AND gate 1/9 outputs the control input S of the bistable circuit Dl if the logic values in the bistable circuits Dl and Dl are not the same, the logic value from the bistable circuit D 2 for the same values in the bistable circuits DI and D2, the inverted value the bistable circuit D4. By inverting the control input S of the bistable circuit D 7, either the value from the bistable circuit D 2 or the inverted value from the bistable circuit D4 appears at the direct output Q.

The same procedure is used with the storage in the bistable circuits D3 and D4, so that if the values are unequal, the value from the bistable circuit D 4 comes to the direct output Q of the bistable circuit D 6. If the values in the bistable circuits D 3 and D 4 are the same, the logical value is taken from the bistable circuit D 2.

The AND gate UU connects the outputs from the two inverters / 1 and II , which both always have an L in the case of unequal values in the bistable circuits D 1. Dl or D3, DA , so that at the control input S and thus at the output Q of the bistable circuit D 5 always a 0 appears, on the other hand, given the same logic values in one of the two pairs of bistable circuits Dl, D 2 or D3. D4 received an L at the output β. It should be noted here that the OR gates 0 1 and Ol never give the same logical Wertl with proper synchronization. A correction can therefore be made with this criterion.

The AND gate U 13 combines the outputs of the two OR gates 0 1 and O 2: as a result of the inversion, a 0 can only appear at its output if both OR gates give the logical value L. The mode of operation of the synchronization is illustrated with the aid of FIG. 2, in which the individual lines represent the output voltages at the circuit elements from FIG. 1 indicated on the left-hand edge, using the sequence mentioned at the beginning. The abscissa of this representation is the time axis.

At the time rl a clock pulse appears at the clock pulse input TP , at the same time the output of the first divider stage Tl shows the value L, the output TlA of the second divider stage Tl the value O and the output 7 "2S the value L. This leads the AND-Toi t / 12 on the one hand the clock pulse to the AND gates t / 5 ... VW and on the other hand to the AND gate f / 13. Since the bit sequence LL 00 is stored in the first shift register SCH i , the two OR gates Ol and Ol at the output the value Λ so that with the end edge of the clock pulse the bistable circuit D 8 receives the value Γ at output Q and thereby blocks the AND gate f / 14. F <is thus suppressed the following clock pulse with the next pulse off the bit sequence in the shift register SCH 1 is changed to LLLO in the divider 71, whereby the OR gate 01 changes to the value Γ, so that the output of the AND gate U 13 assumes the value L. The end edge of the next clock pulse represents the output Q the bistable circuit DS to L. and the AND-T or 14 unlock! The output pulses at the outputs TlA and TlB of the divider stage Tl have been shifted by one clock pulse width. With the write clock from the dividing stage Ti , the bit sequence in the shift register changes back to an illegal combination via OLLL to 00ZX. The OR gates 0 1 and 01 both give the value L, and there is a further shift of the output clocks from the divider stages TIA and TlB, because at this time (/ 2) the AND gate Ui2 conducts a clock pulse. In the further course result! Another shortening of the output pulse pause from the AND gate t / 12 by a write-in pulse cycle from the dividing stage Ti.

Up to time / 3, the bit sequences 000 L, LOOC and LLOO were entered into the shift register SCH 1. The test circuit PS responds to the last-mentioned bit sequence by shortening the clock pulse pause for the clock pulses from the AND gate U 12, the clock pulse earlier is delivered. According to the pulse sequence specified at the beginning, the proper synchronization is achieved. The other bit sequences in the shift register SCHI are OLLO. 00 LL and LOOL. Although the two OR gates Ol and Ol simultaneously output the value L for the second bit sequence 00 LL mentioned, the test circuit will not respond because at this time / 4 no clock pulse is passed through the AND gate U 12.

At time ί 5. when the next clock pulse is then passed, the shift register SCH 1 has the synchronous bit sequence LOOL, and the code converter works from now on synchronously with the transmitted bit sequence. In the event of a fault, the unused bit sequences LL 00, 00 LL appear again. LLLL or 0000 at the time of the clock pulses from the AND gate Uli, and by shifting these clock pulses again, the correct synchronized position is achieved again.

Claims (7)

Patent claims: 1. Circuitry for decoding information in a for transmission suitable code formed from bipolar characters occur unci in a binary code corresponding form can be further processed in that bits of the incoming information entered step by step into a first shift register are converted via a logic code converter and fed to a second shift register, from which the decoded information for processing is also taken step by step, characterized in that «ine test circuit {PS) to monitor the bit sequence stored in the first shift register {SCH 1), which switches the clock pulses required for entering the information generated by the code converter into the second shift register {SCH 2) via a gate circuit {TS) . 2. Schahungsanordnung according to claim 1, characterized in that a bistable switching stage (D 8) is present in the test circuit (PS) through which the switching off of the clock pulses is effected for a time corresponding to a clock for storing in the first shift register { SCH 1). 3. Circuit arrangement according to claim 2, characterized in that the bistable switch stage (D 8) of the test circuit (PS) is controlled by clock pulses for input into the second shift register {SCHI). 4. Circuit arrangement according to claim 1, characterized in that the clock pulses for input into the first shift register {SCH 1) and the clock pulses for saving from the second shift register {SCHI) are in a pulse ratio of 4: 3 to each other, 5. Circuit arrangement according to claim 4, characterized in that the clock pulses for input into the first shift register {SCH 1) via a first divider stage (Tl) with a division ratio of 3: 1 and the clock pulses for Ausspeichem from the second shift register (5CH 2 ) are taken from a common pulse generator {TP ) via a second divider {T1) with a divider ratio of 4: 1. 6. Circuit arrangement according to claim 5, characterized in that the clock pulses for entering the information from the code converter {CW) in the second shift register {SCHI) originate from a gate circuit, which by the pulses from the first divider (Tl) and from the second divider (T 2) controlled wini and thus emits every twelfth pulse from the pulse generator {TP). 7. Circuit arrangement according to claim iS, characterized in that the gate circuit {TS) is connected in the feed line of the clock pulses from the pulse generator {TP) to the second Teilet (T 2) and that the bistable circuit (D 8) the gate circuit (TS) blocks for the duration of a pulse from the pulse generator {TP). 1 sheet of drawings 109548/481