DE2012368A1 - Device for checking a group of characters with attached test characters and for determining a test character for a group of characters - Google Patents

Description

Device for checking a group of characters with an attached test character and for determining a test character for a character group. The invention relates refers to a device for checking a group of characters with an appended check character and for determining a check character for a character group, the characters including of the test character include a number of 4m + 2 characters and m at least the value 2 and that each character is assigned a fixed value from 1 to 4m + 2 inclusive is, the end position of the device after the introduction of the group of characters Correctness of this group or the determined test mark is determined by known ones Check digit procedure, individual errors are detected, but this procedure fail more or less with various other types of errors. So far is only a decimal system for checking is known, the single errors, interchanges (from # ba) and detects phonetic errors (13 # 30; ln # n0) to looX. However, this method has the disadvantage that jump interchanges (abc A cba), which, however, only rarely occur and only make up about l / lo of the error formed by neighboring interchangeable tones, only about 67% can be determined.

Double faults (aa # bb), which have roughly the same low frequency as the above-mentioned jump swaps occur, namely to about 55%.

The invention is based on the task of detecting jump errors and to improve double faults and thereby the 100% detection of single faults, Maintain interchangeability and phonetic errors.

With the facility for checking a group of characters with an attached Test mark and to determine a test mark for a group of characters according to the present In the invention, the above-mentioned improvements can be achieved through the distribution of the values attached to the characters into a lower class and an equal class high class, of which the low class has the values 1 up to and including 2m + 1 attached characters and the high class from the values 2m + 2 up to and including 4m + 2 attached characters is formed, and by the .od 2-counting the high characters of the group of characters, and by adding the mod 2m + 1 of the character appended to the entering character Value after this value is multiplied by a certain factor, where this factor for the lower sign is x to a power that of the number corresponds to the preceding low sign, and this factor for the high Character is equal to x to a power of the number of preceding high characters corresponds to, where x is a number between 1 and 2m with the property that you Square mod 2m + 1 is not equal to 1, and that a number is then added, which is a function of the bit configuration of high or low characters which does not change the result of the mod 2m + 1 addition or changes it if it is mixed up of two consecutive characters from the same or different class, where the character group is only correct if the mod 2 count and the mod 2m + 1 addition a predetermined result is achieved and that also for the Determination of the test character for the character group of this character from the result sheet the above counting and addition is evident.

In particular, is the embodiment of the device according to the invention so taken that the function of the bit configuration of the high. or being low the sign consists of a sum mod 2m + T of the power of x, with as an exponent the number of high signs that precede each of the high signs minus one Sunde mod 2m + 1 Of powers of x with as an exponent the number of low characters that Precedes each of the high signs.

According to a first embodiment, the characters are used as pulse trains entered, the number of pulses in the pulse train being the same as the number attached to the characters Value and setting up a mod 2 counter that counts on every emerging high Character advances one step, a first mod B counter that enters each time low character advances one unit, a second mod S counter that for each high character that occurs, a unit advances, a switch, which switches after a possible (2m + 2) impulse and is reset after each character as well as a mod 2m + 1 adder, which with each pulse of the pulse series adds the value offered by a gate circuit, the gate circuit in such a way the switch controls that the offered value during the first 2m + 2 Pulses is equal to x to a power that corresponds to the position of the first mod s counter and after the (2m + 2) pulse it is equal to x to a power equal to Is the position of the second mod 2 counter, where s is equal to the period of x mod 2m is.

Expediently, 2 is selected for the device x, the values of s being determined as a function of m in accordance with the table below. m # 2 3 4 5 6 7 8 9 lo 11 12 13 14 15 16 s # 4 3 6 lo 12 8 8 18 6 11 20 18 28 5 lo In one embodiment of the invention, the characters and the check character are input in parallel in the form of a pulse on a conductor separate for each character, these pulses, if the characters are low, via an OR circuit to a first mod s counter or via another OR circuit to a second mod s counter, if the characters are high, are passed and that each conductor embodying a certain character as well as the outputs of the first and second mod s counter with the inputs of a code converter, whose 2m outputs at inputs of a mod 2m + 1 adder, the mod 2m + 1 adder adds the value offered by the code converter for each character depending on a pulse mod 2m + 1 delivered by a gate circuit via a conductor common to all characters.

According to a further feature are those fed to the adder.

and from the respective counter readings of the first and second counter as well as from the character to be checked of the character group to be entered via an input device according to the following table: C 0 1 2 3 D 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 1 1 1 1 1 2 2 2 2 * 4 4 4 3 3 3 3 2: 2 2 2 2 4 4 4 4 3 3 3 3 1 1 1 1 3 3 3 3 3 1 1 1 1 2 2 2 2 X 4 4 4 4 4 4 4 4 4 3 3 3 3 1 1 1 1 1 2 2 2 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 1 1 1 1 2 2 2 2 4 4 4 4 3 3 3 3 7 2 3 0 4 3 4 1 0 0 1 3 2 4 0 2 1 8 3 0 4 2 4 1 0 3 1 3 2 0 0 2 1 4 9 4 2 3 0 0 3 4 1 2 0 1 3 1 4 0 2 0 0 4 2 3 1 0 3 4 3 2 0 1 2 1 4 0 An advantageous embodiment is achieved by using a code converter which determines the check character from the readings of the first mod s counter, the second mod s counter or the mod 2m + 1 adder.

To determine the test character for a given group of characters, each character being assigned a specific fixed numerical value, or to determine whether the test character assigned to the group of characters is correct, the digits are represented in a known manner, as shown below, and the control is based on performed two equations, as illustrated by examples. In these examples, m = 2 is set (checking of decimal numbers): 1 i 1 2 3 4 O E 1 - 1 1 2 3 4 5 1 6 7 - 8 9 o a) Calculation of the check number: 1 0 1 2 3 4 5 6 ai 4 7 2 5 8 a5 = 4 #i 0 1 0 0 1 # 5 = 0 αi 4 4 2 2 0 3 α5 = 4 ji 0 0 1 1 1 j5 = 2 j6 = 2 ki O 1 1 2 3 k5 = 3 k6 = 4 i the consecutive numbering of the sequence of digits ai the sequence of digits with check digits (a5) #i the binary component of ai #i the quinary component of ai ji the number of preceding digits ai # 5 (high digits) ki the number of preceding digits ai (6 (low digits), the relationships also apply The check number is calculated from the following two check equations: (mod 2) or S6 = constant (mod 2) The constant 0 or 1 can be set for equation (1), ie the value 0 or 1 must be selected and fixed for practical implementation. One of the values 0, 1, 2, 3 or 4 can be selected as a constant for equation (2).

In the numerical examples below, for both equations the value O (zero) is chosen.

1) 0 + 1 + 0 + 0 + 1 + E5 = 0 (mod 2) 2 + # 5 I O (mod 2) # 5 = 0 (mod 2) For a5, # 5 = 0; So a5 is a digit <6 (lower digit) and thus k6 = 4 and j6 = 2.

2. (20 # 2 + 21 # 3) + (20 # 4 + 21 # 2 + 22 # 0 + 23 # α5) = 20-2 21 + 22 -2 23 (mod 5) 2 + 6 + 4 + 4 + 0 + 8 α5 = 1 - 2 + 2 - 8 (mod 5) 16 + 8α5 = -7 3α5 = = - 16 - 7 = - 23 5 5 5 - 23 - 2 (mod 5) 3α5 = 6 # α5 = α5 = 2 # 2 = 4 (mod 5) α5 = 4 With α5 = 4 and # 5 = 0 we get a5 = 4.

b) Checking a multi-digit number with the help of check digits. 1 0 1 2 3 4 5 ai 6 1 0 7 3 0 #i 1 0 1 1 0 1 α1 1 1 0 2 3 0 ji 0 1 1 2 3 3 4 ki 0 0 1 1 1 2 2 1 + 1 + 1 + 1 = 0 (mod 2) (20 # 1 + 21 # 0 + 22 # 2 + 23 # 0) + (20 # 1 + 21 + 3) = 20-20 + 21 -2 21 + 22 -2 21 + 23 -2 22 1 + 0 + 8 + 0 + 1 + 6 = 1-1 + 2-2 + 4-2 + 8-4 (mod 5) 16 = 6 (mod 5) The invention is explained below with reference to the drawings, in which various embodiments of the test device according to the invention are shown, explained in more detail.

Show it: Fig. 1 is a block diagram of a device to check a group of characters with an appended check digit for the case m * 2 (decimal numbers), Fig. 2 is a block diagram of a checking device in general for character groups with 4m + 2 characters, where m is greater than 1 and FIG. 3 is a block diagram of a other execution of the facility.

In the circuit shown in Fig. 1, which according to the mentioned Test equations works, one has assumed that the individual Digits of a given multi-digit number as pulse trains from an input device (e.g. a voter disc) K can be fed to the device.

These pulse series are simultaneously via a line 1 one mod 5 adder A and, via a line 2, a pulse detector 0 and a switch B supplied. The pulse detector G is switched on at the beginning of each series of pulses and switched off at the end of the pulse series. So it delivers a series of impulses during each a continuous pulse. The switch B speaks with the occurrence of pulse trains with six or more pulses, controlled by the trailing edge of the 6th pulse, on and becomes at the end of such a series of pulses by the trailing edge of the pulse detector 0 delivered pulse via the line R is reset to its original state. Of the Switch B determines the digits in the series of digits whose component is Ei e 1.

The output of the pulse detector a is connected to the input of a switch E connected, which is controlled by the output of the switch B. When occurring of pulse series with less than six pulses, the switch 13 delivers via the Line 3, an output signal "O", in which the pulse detector a from the switch E is connected via line 4 to a first cyclic mod 4 counter C, which In each case, it advances through the trailing edge of a pulse supplied by the pulse detector G. The counter C counts the received ones.

Digits ai with pulse trains less than six pulses. Of the Meter reading of the counter C corresponds to the value kl (low digits) in the case of series of pulses with six or more pulses, the switch B delivers an output signal via the line 3 "1" to the changeover switch E, which accordingly controls the pulse detector 0 via a line 5 connects to a second cyclic mod 4 counter D. The counter D becomes the same In each case switched on by the trailing edge of a pulse supplied by the pulse detector G.

In this way, the counter D counts the entered digits a1 Pulse trains of six or more pulses. The count of the counter D corresponds the value ji (high numbers).

The two mod 4 counters C and D each have the possible for each Counter reads a certain output with the value 0, 1, 2 or 3, whichever with a gate circuit F, which is controlled via a line 6 from switch B, connected is. The gate circuit F is on the output side with the mod 5 adder.

Werk A in connection.

If a series of pulses with fewer than six pulses occurs (B. If an output signal "O" is supplied, switch B controls the gate circuit via line 6 F such that the outputs of the counter C are connected to the adder A, while with pulse trains of six or more pulses (B lierert an output signal "1") the outputs of the counter D are connected to the adder A through the gate circuit F will.

The values given by the gate circuit F to the adder A result from the values given by counters C and D according to the formula: F = XC # (1-B) + XD # B (mod 5) For B = 0, the output value of gate circuit F is determined by the count of counter C and for B, 1 after that of counter D.

In the exemplary embodiment of FIG. 1, x - 2 is set. The circuit but can also be carried out for any other value of x.

For the outputs of counters C and D, the following values result for the outputs of F for mw 2 (mod 4 counters): C, D 0 1 2 3 F @ 1 2 4 3.

The mod 5 adder A adds the for each pulse of the pulse series value offered by F. For example, if a digit "4" is introduced, and the counter C has a count "1", the gate circuit F supplies the adder A the Value "2" so that the adder A advances by 4 x 2 = 3 (mod 5).

The mod 5 adder A is via an output line 7 and the mod 4-counter D connected via an output line 8 to an AND circuit 9, the with certain previously defined final states, e.g. A = 0 and D = 0 0 or 2, by means of a signal at the output 10 of the AND circuit 9 the correctness of the offered Number with a check digit or an error. The AND circuit 9 thus checks whether the conditions of the two test equations are met.

In the event that the facility is also used to determine and display the check digit belonging to a group of digits is to be used by a code converter P provided, which is via a line 11 with the counter C, via line 7 with the Adder A and via line 8 is connected to the counter.D, and which after predefined conditions, e.g. A = 0, C = 0 and D = 0, from the counter readings of the Counters C and D and the status of the adder A determine the check number (e.g. P = 5) and displays.

The following table shows the values of the check digits that the Code converter P from the given counter readings of the counters C, D and the adder A determined.

Table for the P values 0 1 2 3 4 CD 5 4 3 2 10 0 5 2 4 1 3 1 0 5 1 a 3 4 2 0 5 3 1 4 2 @ 3 0 8 0 7 9 6 0 1 0 7 9 6 8 1 1 9 6 8 0 7 2 1 P 7 9 6 8 0 3 1 .5 4 3 2. 1 0 2 5 2 4 1 3 1 2 5 1 2 3. 4 2 2 5 3 1 4 2 3 2 9 7 0 8 6 0 3 7 0 8 6 9 i1 3 8 6 9 7 0 2 3 o 0 8 6 9 7 3 In the case of the test device shown in Fig. 2 for groups of characters with 4m + 2 characters, where m> 1, the following table can be put together: m @ 2 3 4 5 6 7 8 9 lo 11 12 13 14 15 16 Sign- number - 14 18 22 26 - 34 38 - 54 58 6264 5 4 3 6 lo 12 8 8 18 6 11 20 18 28 5 lo In this device, the already mentioned counters, here designated C1 and D1, count with mod s for the high and low characters (see table above), while the adder, here designated Al, counts with mod 2m + 1 and one attached counter H1 is counted with mod 2. In this case, the mod 2 counter H1 fulfills the conditions for the first test equation. The mod 2 counter H1 receives input pulses from the switch B1 via a line 12 and is connected on the output side via a line 13 to the AND circuit 9 and via a line 14 to the code converter P1.

In the embodiment shown in Fig. 3, the digits and the check digit, if any, in parallel in the form of a pulse on one for each digit separate head introduced.

The lower digits are ORed into a mod s counter C2 fed, while the high digits U via another OR circuit to a mod s-Count.r D2 and, if necessary, a mod 2-CounterI are fed. If s even is one can do without the latter mod 2 counter I, since the number mod 2 of the high digits in that case can be determined from the status of D2. The ones corresponding to the digits Just like the 6 outputs of the two counters C2 and D2, conductors become one Code converter H2 supplied, whose outputs a mod 2m + l adder A2 a variable Offer value.

The table below specifies which value is fed to the adder A2 in each case as a function of the counter readings of the counters C2, D2 and the digit offered by the input device K2. C2 0 1 @ 2 3 D2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 1 1 1 1 1 2 2 2 2 4. 4 4 4 3 3 3 3 2 2 2 2 2 4 4 4 4 3 3 3 3 3 1 1 1 1 3 3 3 3 3 1 1 1 1 2 2 2 2 2 4 4 4 4 4 4 4 4 41 3 3 3 3 1 1 1 2 2 2 2 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K2 6 1 1 1 1 2 2 2 2 2 4 4 4 3 33 3 3 7 2 3 0 4 3 4 1 0 0 1 3 2 4 0 2 1 8 3 0 4 2 4 1 0 3 1 3 2 0 0 2 1 4 9 4 2 3 0 0 3 4 1 '2 0 1 3 1 4 o 2 0 0 4 2 3. 1 0 3 4 3 2 0 1 2 1 4 0 Whenever a digit is offered, a pulse is determined by a gate circuit F2, which is fed to the adder A2 and which causes the value mod 2m + 1 offered by H2 to be added in A2. The end position of the adder A2 and the two-divider I control a detection circuit L2, which determines whether the number entered is correct. If the device is used to determine the check digit, the check digit can be specified in the same way as in the first embodiments via a code converter P2.

Claims

Claims (8)

P a t e n t a n s p r ü c h e 1. Device for checking a group of characters with attached test character and to determine a test character for a group of characters, where the characters including the test character have a number of 4m + 2 characters and m has at least the value 2 and that each character has a fixed value from 1 to including 4m + 2 is assigned, the end position of the device after introduction the group of characters the correctness of this group or the determined test character determines the distribution of the characters attached to the characters Values in a low class and an equally large high class, of which the low Class of characters appended to the values 1 up to and including 2m + l and the high class of characters appended to the values 2m + 2 up to and including 4m + 2 is formed, and by mod 2 counting the high characters of the character group and by mod 2m + l adding the value appended to the entering character after this value is multiplied by a certain factor, this factor being for the lower sign is equal to x to a power that of the number of the preceding one equals low characters, and this factor equals x for the high characters is a power equal to the number of preceding high characters, where x is a number between 1 and 2 m with the property that its square is mod 2m + 1 is not equal to 1, and that a number is then added, which is a function the bit configuration of being high or low is the result the mod 2m + l addition does not resp. probably changed if two consecutive characters were mixed up from the same or different class, whereby the group of characters is only correct is if predetermined by the mod 2 count and the mod 2m + 1 addition Result is achieved and that for the determination of the test character for the character group this sign is evident from the result of the above counting and addition. 2. Device according to claim 1, d a 4 u r c h g k e n n -z e i c h n e t that the function of the bit contour of the high or low character consists of a sum mod 2m + 1 of the power of x, with the number of as the exponent high sign that precedes each of the high signs minus a sum mod 2m + 1 of powers of x with as an exponent the number of low signs that each precedes the high signs. 3. Device according to claim 1 or 2, d a d u r C h g e -k e n n shows that the characters are entered as a series of pulses, with the number the pulses of the pulse train is equal to the value attached to the symbol, and that the establishment of a mod 2 counter (H1) that counts for each high character that occurs advances a step, a first mod s counter (C1), the each occurring low character advances one unit, a second mod s counter (D1), which advances one unit with each high character that occurs, a switch (B1), which after a. any (2m + 2) impulse toggles and reset after each character as well as a mod 2m + 1 adder (A1), which at each. Impulse of the impulse series the value offered by a gate circuit (F1) is added, the gate circuit (F1) is controlled by the switch (B1) in such a way that I the offered value during of the first 2m + 2 pulses is equal to x to the power of the position of the mod s counter (cl) and after the (2m + 2) pulse is equal to x tu to a power that is equal to the position of the mod s counter (D1), where 5 is equal to the period of x mod 2m + 1 is. 4. Device according to one of the preceding claims, since -dur ohgeknown 5 i O hnet, since x is selected to be 2, the values of 1 being determined as a function of 1 according to the table below: m 2 3 4 5 6 7 8 9 lo 11 12 13 14 15 16 5 4 3 6 lo 12 8 8 18 6 11 20 18 28 5 lo 5. Device according to claim 1, 2 or 4, wherein the characters occur as pulse trains, of which the number of pulses is equal to the value attached to the character, d a it is clear that m = 2 and the group of characters is a decimal number and characters 1 to 9 are the related digit value and characters 0 are the value lo is assigned, and that the device has a first mod 4 counter (C), which at Advances one unit for each character with a numerical value <6, a second mod 4 counter (D) with a numerical value for each character that occurs # 6 advances one unit, a switch (B) that, after a possible 6th pulse switched and reset after each character as well as a mod 5-addlerwerk (A) has, that for each pulse of the pulse series, which the entered numerical value represents, adding the value offered by a gate circuit (F), the gate circuit (F) is controlled by the switch (B) in such a way that the offered value during of the first 6 pulses is equal to 2 to a power equal to the position of the mod 4 numerator (C) and after the 6th pulse is equal to 2 to a power that is equal to the position of the mod 4 counter (D) is, and that the mod 4 counter (D) consists of two series-connected Two-parters, with the i being the high characters of the first of the two two-parters mod 2 is counted. 6. Device according to claim 1, 2 or 4, d a d u r c h g e -n n z e i c h n e t that the characters and the test character are parallel in the form of a pulse can be entered on a separate parent for each character, whereby these pulses, if the characters are low, via an OR circuit to a first mod s counter (C2) or a second Sod s counter (D2) via another OR circuit, if so di. Signs are high, to be directed, and that each have a certain sign embodied Avoid the conductors and the outputs of the first and second mod s counters (C2, D2) Inputs of a code converter (H2), its 2m outputs to inputs of a mod 2m + 1 adder (A2) are connected, with the 2m + l adder (A2) for each character the value offered by (H2) depending on one of a gate circuit (F2) added mod 2m + 1 via a pulse supplied for all characters. 7. Device according to claims 1, 2, 4 and 6, dzdurchg okzeichen; that the values fed to the adder (A2) and dependent on the respective counter readings of the first and second counters (C2, D2) as well as on the characters to be checked of the character group to be entered via an input device (K2) are determined according to the following table: C2 0 1 2 3 D2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 1 1 1 1 1 2 2 2 2 4 4 X 4 3 3 3 3 2 2 2 2 2 4 4 4 4 1 3 3 3 3 3 1 1 1 1 3 3 3 3 -3 1 1 1 1 @ 2 2 2- 2 4 4 4 4 K2 4 4 4 4 4 3 3 3 3 1 1 1 1 2 2 2 2 5 0 0 0 0 0 0 O 0 0 0 0 0 0 0 0 0 6 1 1 1 1 2 2 2 2 4 4 4 4 3 3 3 3 7 2 3 0 4 3 4 1 0 0 1 3 2 4 0 2 1 8 3 0 4 2 4 1 0 3 1 3 2 0 0 2 1 4 9 4 2 3 0 0 3 4 1 2 0 1 3 1 4 0 2 0 0 4 2 3 1 0 3 4 3 2 0 1 2 1 4 0 8. Set up after a. of claims 1 to 7, d a d u r c h g o k e n n n e i c h n e t that a code converter (P, P1, P2) is provided which from the counting positions of the mod s counter (C, D; C1, D1; H1; C2, D2) and the mod 2m + 1 adder (A, Al, A2) determines the test character and that one at the output of the mod 2m + 1 adder (A, Al, A2) and the mod s counter (D, H1, D2) connected Detection circuit (9, L2) indicates the test result.