DE2006504C3 - Method for inserting an equidistant sequence of binary signals into the pulse frame of a transmission link - Google Patents

Description

- bars of f _{o are} inserted in each case.

2. The method according to claim 1, characterized in that with a pulse frame of 256 bits, two shift registers (Sp 1 and 5p 2) with a pulse frame of 256 bits divided into two information blocks of 120 bits each by a synchronizing and a Kennzeichenk ^ nal each of 8 bits each 120 memory locations are used, are read alternately with the low clock frequency door each 120 bits into and read out with the higher Taktfrequeiz / _o ^ dc transmission link.

3. The method according to claim Γ, characterized in that that from the cycle of the transmission line

4 = 256 x 8 kHz = 2.048 MHz
one by the factor

256-2-8
256

lower clock f " of 1.92MHz is derived almost phase-locked.

4. The method according to claim 3, characterized in that the pulse frame clock (1) is fed once directly and once inverted each to a start-stop generator oscillating with the clock frequency of 1.92 MHz, which is lower by I ^, in such a way that the two start - Replace stop generators in their active time in a ratio of 1: 1 and that the alternating output signals (3, 4) are combined via a gate circuit O \ to a continuous cycle of 1.92MHz (5) (Fig. 2).

According to the preamble of claim 1, the invention relates to a method for inserting Equidistant binary signals in the pub frame of a PCM system, but with certain places synchronization signals within the frame because of the necessary transmission of other information, switching indicators) may not be occupied.

There are methods known that the transmission of asynchronous data signals via synchronous systems - ζ. Β. Lines with integrated regenerative amplifier - allow. First and foremost is The sampling process should be mentioned here, in which the data signal to be transmitted is synchronized with the synchronous Transmission path is scanned. In this procedure, the characteristic distortion is

Here t is the period of the interrogation act.

ίο (We 11 hau sen, H. W .; H essen müller, H .: Basic parameters of a PCM mass transit system. The telecommunications engineer, 23 [1969], 4.)

Another method in which the distortion is considerably smaller than in the sampling method is that

π Possibility of coding the polarity reversal of the Data signal through 3 or more bits of the synchronous transmission link. (Travis, LF .; Yeager, R. E: Wideband data on Tl carrier. Bell S.T.J. 44 [1965], 8, Pp. 1567-1604.)

In addition to asynchronous data transmission, synchronous data transmission is conceivable in which the output and Input at the data terminal is controlled by the clock of the transmission link. All described Processes have the disadvantage that the synchronous ones ultimately to be transmitted over the line Signals form an equidistant sequence, in the course of which no signals are used for other purposes can be transferred.

This is also not possible with buffers that

jo with a low clock frequency and a higher one Clock frequency can be read out (Bell S.T.J. 1969, p. 615).

The invention is based on the object of converting an equidistant sequence of binary signals into a binary

J5 to insert current higher speed, whereby the transmission of these signals is periodically interrupted by the fading in of signals serving other purposes (synchronization signals, switching characteristics). The PCM 30/32 pulse code modulation system widely used in Eviiopa is an example of such a need. In this system, a pulse frame of 256 bits with a bit rate of 2.048 Mbits / s has been defined. The first 8 bits of each frame are used to transmit the frame synchronization identifier, followed by 120 bits to transmit the actual information. Bits 129 to 136 are reserved for identification transmission, while the remaining 120 bits are used for message transmission. Accordingly, generally k (16) of bits arranged in ρ (2) groups totaling η (256) bits must be inserted.

The object is achieved according to the invention in that from the clock frequency f "of the transmission path a clock frequency /" η which is ^{lower by a factor of 1} ^

is derived and the binary signals in cyclical order

during each - clocks of this lower clock frequency

P.
quenz f _u first in one of ρ buffers with

—Memory locations are read in and then read out again with the higher clock frequency f „ , the ρ groups of each —bit in the rest

P.

Time of the pulse frame during - ^ - clocks of f "

P.
inserted.

With a puk frame of 256 bits divided into two information blocks of 120 bits each by one synchronization and one identification channel of 8 bits each, two shift registers with 120 storage locations each are used, into which 120 bits are read alternately at the low clock frequency / "" can be read out with the higher clock frequency f _{tl of the transmission link.}

The clock frequency of such a system is derived from the clock of the transmission path ι ο

/ _O = 256 x 8 kHz = 2.048 MHz

the pulse frame clock 8 kHz and from this one by the factor

256-2 8 _ 15

256 ~ 16

lower clock rate f "derived from 1.92MHz almost phase-locked.

For this purpose, the pulse frame clock is advantageously fed once directly and once inverted to a start-stop generator oscillating at the H lower clock frequency of 1.92 MHz in such a way that the two start-stop generators are active in a ratio of 1: 1 and that the alternating output signals are combined via a gate circuit O \ to a continuous cycle of 1.92MHz (5).

F i g. 1 shows the details of an exemplary embodiment for the pulse frame of the PCM 30/32 system. the end F i g. 2 shows the associated pulse diagram. The gate connections are for positive potential (logical ■ "1") AND, for negative potential (logical "0") OR circuits.

In the clock center TZ of Fig. 1, the clock of the transmission link of 2.048 MHz is generated by a frequency-stable generator. It is available at point 7. The pulse frame clock (2.048: 256 = 8 kHz, line 1 in FIG. 2) and the clock for fading in the synchronizing signals (line 6 in FIG. 2) are generated from this clock through frequency division and logic operations. Both clocks are available at outputs 1 and 6 of TZ . The frame cycle 1 starts the start-stop generator Gl with its positive edge, while the negative edge stops it again. The inverter / 1 inverts the pulse frame clock. The resulting complement of the frame cycle at 2 starts and stops a second start-stop generator G 2. Eq and G 2 alternate with their active time in a ratio of 1: 1. Both vibrate with the frequency

2.048 H = 1.92 MHz.
Io

The output signals of both generators (lines 3 and 4 in FIG. 2) are linked via the gate circuit O 1 - 1, so that a continuous clock of 1.92 MHz is available at 5. If the frequency stability of the generators Gl and G 2 reaches the real value of 10- ^J , the phase jitter of the 1.92 MHz clock is no greater than approx. 10%, which is irrelevant for the proper functioning of the circuit. In the encoder C , the data present at 10 are processed according to the scanning, coding or other method, so that an equidistant sequence of binary characters containing the data information is available at 11, which via the gates U 1 and UI alternately in the rhythm of the pulse frame rate (Control by 1 or 2) to the ranks of the two i2ö-bit shift registers SpX and SpI gr'aiigi. At the same time, the clocks for the shift registers are alternately switched between 2.048 and 1.92 MHz. If z. B. U 1 is opened by the potential at 1. the signal from 3 for reading in the information from 11 is available at the clock input of Sp 1 and O2. During this time, U2 is blocked by the negative potential at 2, so that no information can be read into Sp2. After '.20 bits have entered 5p 1, U \ is blocked by the negative potential at 1 and L / 3 is opened by the positive potential at 2. The 1.92 M Hz cycle at 3 has thus been switched off. For this, the 2.048 MHz clock rate of 7 is available via U3. After 120 periods of this cycle, the information from 5p 1 is stored and is passed on to the transmission link at point 8 via O4. During the following 8 clock periods, synchronization or switching technology signals can be switched to the route via the gate i / 5. Then U 1 opens again, i / 3 blocks, G 1 begins to oscillate, etc.

D-.r circuit part in the lower part of FIG. 1 with the elements Sp2, 112, i / 4, G2 and O3 works in the same way as described above by 180 ° - based on the pulse frame clock - phase-shifted.

The inverters / 2 and / 3 ensure the functionality of the (OR) link OA.

The method according to the invention enables fully asynchronous operation. The distortion of the system is determined only by the type and construction of the encoder.

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. A method for inserting an equidistant sequence of binary signals into the pulse frame of a transmission link with η bits, of which k bits arranged in ρ groups that are equidistant to one another are not available for the binary signal transmission, characterized in that the clock frequency f _{o of} the transmission - stretch one by the factor -— - lower Clock frequency f _{u is} derived and the binary signals are read in cyclic sequence during each - clocking of this lower clock frequency f _u in one of ρ buffer memories with - storage locations and then read out again at the higher clock frequency f _a , the ρ groups of t each
- Bit in the remaining time of the pulse frame during