DE2001427C3 - Circuit arrangement for controlling devices (dialing pulse generators) for generating dialing pulse sequences that are dependent on dialing information of a different type - Google Patents

Description

The invention relates to a circuit arrangement for controlling devices (dial pulse generator) for spontaneous generation of dialing pulse trains, whose pulse lengths are dependent on dialing information of a different type and their pulse pause lengths multiples of the period of one and the same, of a common one Clock pulse generator generated periodic pulse train clock pulse train), by means of buffer devices for intermediate storage dialing information of a different kind. for computer-controlled telecommunication switching systems.

When making telephone connections, the facilities with which the connections can be produced by a combination of several Controlled digits that are dialed by the calling party.

Most telephone systems have a number of pulses of a certain length for each digit sent out, whereby this number corresponds to the value of the digit and the pulses are determined by pulse pauses Length are separated from each other. The pulses are generated by a changeover relay. this has the disadvantage that the digit information is sent at a low speed. Therefore became this procedure, especially when transferring information abandoned between two telephone exchanges, but also a modern one Computer-controlled television switching system must be equipped with facilities for the transmission of digit pulses, as they are usually with switching systems older design must work together.

Below are two suitable and, for example, using the DT-AS 12 74 66 «

derived circuit arrangements described.

In the first circuit arrangement, a digit dialed by a subscriber and in a the participant's associated memory word is a number stored, which is equal to the sum of the number of impulses lind the impuispauscii isi. those from the associated dial pulse generator or pulse transmitter relays must be generated. There is also a clock word for each pulse transmitter relay assigned, the content of which is compared with the content of a clock register that is used for all pulse transmission relays is common. If the clock word and clock register match, the corresponding one switches Pulse transmitter relay to, d. H. a pulse or a pulse pause is initiated. A control arrangement, which is also common, firstly sets the clock word in such a way that that after entering a memory word at nachjten Step of the clock register match occurs that the following matches are correct Pulse lengths or pause lengths and that no match is possible. if the content of the memory word is zero. Second, the common control arrangement lowers the content of the memory word with each match / between clock and clock register by one unit.

In the second circuit arrangement, each one is used to fingerling the memory expenditure Participants associated memory word-clock word units the first-mentioned circuit arrangement by a number of common for all participants Replaces buffer facilities or registers, in welehe random orders are written in such a way that certain pulse transmission relays contain certain digits Send in the form of pulses of the appropriate number. A job consists of a memory word-address combination, where the address defines the particular pulse transmission relay. At a certain step A common clock register is used to write all the pulse transmission relays and their addresses in the buffer registers are switched from this clock register. As in the case of the former, the memory word contains Circuit arrangement initially the sum of the pulses and pulse pauses required for the digit to be sent, which sum is changed each time by a control arrangement common to all buffer registers a unit is reduced when the clock register the Pulse transmission relay switches. If the memory word of a pulse register is counted down to zero. will the associated address is also deleted and the corresponding pulse transmission relay is disconnected from the clock register, after which a new job can be written to the relevant buffer register.

While in the first case a very high memory requirement is required. In the second case, there is the fact that the devices for generating the dialing pulses are logs controlled in unison, in particular activated. be, the possibility that the power source for the Dialing pulses (clockwise) is overloaded.

The invention is based on the problem of this possibility of overloading the power source for the To prevent election impulses.

A circuit arrangement is in the sense of solving this problem of the type set out in the introduction characterized according to the invention

through a register (address register) for storing the addresses of the dial pulse generators. ^(l 5 through a register (dialing information register) for storing dialing information of a different kind. which express the sum increased by one from the number of pulses and the number of pulse pauses of the dialing pulse sequence to be generated in each case.; e,

through with the election pulse generators, with the clock, with the address and with the election information register connected buffer devices with memory cells for the addresses of the dial pulse generators, with an interval corresponding in the pulse lengths and in the pulse pause lengths downward counting pulse counter, with a transfer of a stored in the address register Address in one of the memory cells controlling counter (memory line counter) and with a decoder (address decoder) connected to the memory cells, through which in cooperation with the pulse counter, the outputs connected to the dial pulse generators the buffer device can be activated by a shift register with the buffer devices individually assigned cells for searching the one containing a free memory cell (Available) buffer devices in a (first) search run as well as through one with the dialing information register and comparison means connected to the buffer means by which the content of the Wahlinformalionsregisiers during the (first) search run of the shift register with the reading of the pulse counter of the respective available buffer facility \ and at Correspondence the transfer of the contents of the address register into a free memory / part of this Buffer device is initiated. In the circuit arrangement according to the invention are the times of activation de: devices for generating the dialing pulse sequences so scattered that at least not all devices that are currently being controlled are activated at the same time. Kin is an advantage. that the number of buffer facilities required can be reduced in comparison with the above-mentioned known circuit arrangements can, since the buffer devices in the circuit arrangement nych of the invention several at the same time Wahiiiii | jülsgeber control.

In a further development of the circuit arrangement according to the invention, the buffer devices are further cells of the shift register individually assigned via which, if the first search does not match the contents of the election information register and the status of the pulse counters of the available buffer facilities. in a subsequent further search of the shift register an available buffer device is selected, its pulse counter is at zero, and the transfer of the contents of the dialing information register in the pulse counter as well the contents of the address register is caused to be in a free memory cell of this buffer device.

The invention is explained in more detail below with reference to an example of an aluminum guide shown in the drawing described.

The circuit arrangement is fed with computer speed, the two registers RfXi R and RIzG S are provided for this purpose. If a digit is to be generated by a dialing pulse generator, the address of the same is fed in the address register REG R and the information about the number of pulses and pulse pauses corresponding to the digit in the dialing information register REG S. After a comparison device d or an AND gate circuit OZ \ die

20 Oi 427

Has released the transfer of the address, a new digit-address combination can be entered in the circuit arrangement. Towards shift register SH. which also mil Rcchnergcschwindigkeit arbeilet is provided with activatable successively outputs which are connected to a number of Puifereinrichtungen B \ to lim, of which the Hinfachheit sake only the Pufl'ereinrichtung Bq is shown in the drawing.

The buffer device Sq consists of a number of memory cells 61 to 615 in which the address information for the dial pulse generators R \ to Rn can be registered via AND gate switching OWi to OIV15, with stored address information relating to a specific one of the outputs 1 to η of an address decoder A VK R activated.

The registration of address information in the various memory cells is controlled by a memory cell counter CC which is connected to the gate circuits OWi to OWi5 via a further address decoder AVKb , so that the memory cell counter CC is switched on . that the gate circuits OW15 to OIV15 are opened one after the other.

The buffer devices also contain devices for pulse and pause generation, which work much slower compared to those previously mentioned and are controlled by a common clock generator C /. being controlled. In the buffer device Bq , a pulse counter PC displays every instant. how many more pulses and pulse pauses are to be generated by the dial pulse generators R \ to Rn , the addresses of which are stored in the memory cells oil to 615. The pulse counter PC receives countdown pulses from a further comparison device C2, the first input of which is connected to the clock CL via an AND gate circuit OCvcrbundcn and the second input of which is connected to a timer Tin, the function of which is described in detail below. When the input signals of the further Verglcichscinrichtungen Cl are equal, an output signal is generated. The output of the further comparison device Cl is also connected to two AND gate circuits OP1 and OP1. which are also connected with their second inputs to the last digit position of the pulse counter PC , the second input of OP1 being inverting. With each downward counting pulse, either the output of the gate circuit OPl or the output of the gate circuit OPl is activated depending on whether the sum of the remaining pulses and pulse pauses is odd or even, ie whether an In.puls or a pulse pause is to be initiated. The outputs of these gate circuits are connected to AND gate circuits OXa to Ona or OI6 to Onb, the second input of the gate circuits being connected to the correspondingly numbered output of the address decoder A VK R. The outputs of the gate circuits OXa to Ona are connected to the "!" - set inputs of bistable multivibrator circuits VX to Vn , the outputs of which are activated when "!" Is set and are connected to the corresponding dial pulse generators RX to Rn . The outputs of the gate circuits OXb to Onb are connected to the "O" set inputs of the bistable multivibrator circuit Vl to Vn . Furthermore, the output of the AND gate circuit OP1 is connected to a first clock circuit input of the time counter T and the output of the door circuit OP1 is connected to a second clock sound input of this line counter. Pulses at these inputs switch the time counter 7 by the number of clock pulses of the clock generator C / corresponding to a pulse or a pulse pause. further, ie if the switching period of the clock generator ■ / .. B. 20 ms, the pulse length bO ins and the pulse pause is 40 ms and the line counter is switched by three steps from the first reverb entry and by two steps from the second switch input. As a result, the pulse counter PC counts down at intervals of alternating 60 ms and 40 ms. The outputs of the pulse counter PC are connected to the inputs of an OR gate circuit EZ , which has an inverting output which is connected to an inverting input of the AND gate circuit OC . When the pulse counter PC has counted to zero. the output of the OR gate circuit EZ is activated, the AND gate circuit OC is blocked and the downward counting of the pulse counter PC is stopped.

The mode of operation of the circuit arrangement described above will now be explained using an example. It is assumed that the digit information 5 is to be sent from the address register Reg R. The sum of the pulses and the pulse pauses increased by 1 in this number, i.e. 10, is then stored in the dial information register REG S and the address of Rp is stored in the address register REG R. The value in the register REG S is applied to one input of the comparison device C1. Further switching of the shift register SH. starting with cell £ "1, an output of cell E1 being connected to a buffer device oil (not shown in the drawing), i.e. the buffer devices BX to Bm are scanned in sequence. The effect of this scanning process is shown in clearly follows from the explanation of the scanning operation of the buffer device Bq.

If the memory cell counter CC does not indicate that all memory cells bX to 615 are occupied, the result is that the inverting input of an AND gate circuit OEI is not activated.

When activating the output of the cell Eq win

then the value stored in the pulse counter PC is passed to the AND gate circuit OE1 to the second input of the comparison device CI. If at the scm point in time the value in the pulse counter PC with the

If the election information register REG S agrees, which can be the case if the pulse counter counts down from a sum greater than 10, an output signal from the comparison device Cl is used

hold, which opens an AND gate circuit ΟΏ , where the content in the address register REG R via this AND gate circuit and the AND gate circuit OEl opened by the Schicbcrcgistc SH to the one input of the AND gate circuit O »VI to O» VI5 gc will give. Which of these AND gate switching crises is opened and in which memory cell bX to 615 de

The value of Rp stored depends on the value of ir

Memory counter CC from. So that the next storage takes place in the following memory cell, we

the memory cell counter CC thereby refines its switching input from the output of the AND

Torschaltkrcises OEl is activated. In this way

<«; the sending of the digit 5 is initiated by the Adrcsscnrcgisic REGR. The l.cscn of the address register REG R also means that the shift register .S '/

is reset to zero (in the drawing nid '

shown).

If no correspondence is found in the comparison device CI between the contents of the pulse counter PC and the election information register REG S , the shift register SW is switched on, and if, after all buffer devices have been scanned, no agreement is found (i.e. not even in the stage Em) , the switching of the shift register SH is continued. The cells Z1 to Zm are then activated, which are connected to a buffer device with a corresponding index in a manner as shown for the cell Zq connected to the buffer device Bq . The drawing shows that this stage is connected to one input of an AND gate circuit OZl, the second input of which is connected to the output of the OR gate circuit EZ . This output is activated when the pulse counter PC is set to zero, ie when the buffer device Bq is free. If this is the case. the AND gate circuit OZl is opened and the content of the election information register REG S is passed through the UN D gate circuit OZ2 to the pulse counter PC and the content of the address register REG R is stored in the memory cell b \ via the AND gate circuits OZ3 and OWl, because the memory cell counter CC was set to zero by the output of the OR gate circuit EZ. A signal is received from the output of the gate circuit OZ2 which opens the AND gate circuit 05, whereby the value of the clock CL is stored in the time counter T. As a result, the transmission of the dialing or digit pulses from the address register REG R is initiated and the shift register SH is set to zero (not shown in the drawing).

If, however, the pulse counter PC is not set to zero, the shift register SH is switched on until a pulse counter set to zero is found. If this is not the case, then wire a new switching process of the shift register started after 20 ms, after which either a pulse counter may have received a value that corresponds to that of the choice information register REG S , or a pulse counter may have been set to zero .

1 sheet of drawings

Claims (3)

Patent claims: 1. Circuit arrangement for controlling bin- ^ directions (election impulses) for voting instructions Another type of dependent generation of dialing pulse trains, their pulse lengths and their Pulse pause lengths Multiples of the period of one and the same, from a common clock generated periodic pulse train (clock pulse train) are, by means of Bufferereinrichuinget. to the Intermediate storage of dialing information of a different type, for computer-controlled telecommunications systems, marked by a register (address register. REG R) for storing the addresses of the dialing pulse generators (Rl to Rn), by a register (election information register. RECS) for storing the election information of a different type. Which express the sum increased by one from the number of pulses and the number of pulse pauses of the respective dial pulse sequence to be generated. through with the dial pulse generators. with the clock (Cl.), with the address and dialing information register connected buffer devices (e.g. Rq) with memory cells (bi to 615) for the addresses of the dialing pulse, with a pulse counter that counts down in the pulse lengths and> n intervals corresponding to the pulse pause lengths ^{(PO. With a counter (memory cell counter, CO and} with a decoding device (address decoder, A VK R) connected to the memory cells) that controls the transmission of an address stored in the address register to one of the memory cells the selection pulse generators (Ri to Rn) vcrbun which outputs of the buffer device can be activated, through a shift register (SH) with the buffer devices individually assigned cells (Ei to Em) for searching the (available) buffer devices containing a free memory cell in a (first) search run as well by one with the election information register and with the Comparison device (Ci) connected to buffer devices. by which during the (first) synchronization of the shift register the content of the selection information register is compared with the status of the pulse counter of the respective available buffer device and, if they match, the transmission of the content of the address register into a free memory cell of this buffer device is initiated 2. Circuit arrangement according to claim 1, characterized in that the buffer devices (z. B. Bq) further cells (Zi to Zm) of the shift register (SIf) are individually assigned via which, if the first search run, there is no match between the content of the election information register (REG S) and the status of the pulse counter (PO of the available buffer devices. In a subsequent further search run of the shift register, an available buffer device is selected whose pulse counter is zero, and the transfer of the content of the Walilinformalionsregister in the pulse counter and the Contents of the address register (RlXi R) in a free memory cell (bi to oil5) of this remote device. 3. Circuit arrangement according to claim 1 or 2, characterized through a. .1 the pulse counter (PO assigned time counter (T) for counting the pulse lengths and the pulse interval corresponding periods of the clock pulse train,
by a further comparison device ((2). One input with the clock generator (CL), the other input with the output of the line counter and the output, which is activated when the signals at its two inputs match, with the reset input of the pulse counter and with each one input of two gate circuits (OPl. OPl) is connected, which alternately open when counting down / counting the pulse counter and whose outputs are each connected to a further switching input of the time counter to increase the time counter by the pulse length or the pulse pause length corresponding number of periods of the Takiimpuk sequence wciter to switch, as well as by further gate circuits (OI.7 bi ^ On.iO] '' Ks ünb), their inputs with the outputs iks address decoder (AVKR) and or with the A '-' eiiiigi- ^'11 <- ^ier two gate ^' circles (O / l. Oll) and the outputs of which are connected to bistable multivibrator circuits ( Vi to Vn) , the outputs of which are connected to the dial pulse generators (R \ to Rn) .