DE19936676B4 - Interpolating memory circuit arrangement - Google Patents

Abstract

A memory circuit arrangement for a fast access to interpolated data comprises an address input (1) and a data output (2), a memory circuit (3) with a plurality of addressable memory cells, an interpolation circuit (4) with at least one data input (5, 6) for interpolating data, a coefficient input (7) for inputting weighting coefficients of the interpolation and a result output. Address bits of low value of the address input (1) are connected to the coefficient input (7), the higher-order bits are used to address memory cells of the memory circuit (3).

Description

The The present invention relates to a memory circuit arrangement with an address input and a data output and a memory circuit, the plurality of addressable memory cells.

In various technical application areas will have faster access on interpolated values of stored data needed so For example, in computer graphics or in digital mobile communications. Especially in digital mobile this problem occurs when, for the evaluation of a received signal, only a limited Number of samples of the received signal can be obtained each corresponding to certain sampling times, in the later processing but values needed which correspond to times between sampling times.

A Possibility, such intermediate values for providing them with fast access is through interpolation to calculate and samples and interpolated values of their temporal Order filed according to order in a memory circuit. Access to a stored value is done by addressing a memory cell corresponding to the respective time.

It is obvious that the Memory requirement in such a solution proportional to the fineness the needed Interpolation increases. Furthermore is obtaining the interpolation values with a considerable Computing costs associated with this, which is in vain in many applications, because only a small percentage of the calculated interpolation values indeed reading is accessed.

From the US 5,083,208 a memory circuit arrangement with an address input and a memory circuit with a plurality of addressable memory cells and an interpolation circuit with at least one data input for data to be interpolated and a result output is known. The address input comprises lines which serve to address the memory cells. The result output of the interpolation circuit is also connected to the data output of the memory circuitry.

From the DE 195 25 531 A1 For example, an interpolation circuit is known which has a coefficient input for inputting weighting coefficients of the interpolation.

task The present invention is a memory circuit arrangement specify the type defined above, the fast access on interpolated data allowed, while a small amount of memory has and the computational effort for keeps the interpolation low.

The Task is solved by that the memory circuit arrangement is equipped with an interpolation circuit that at least a data input for data to be interpolated, a coefficient input for inputting weighting coefficients of interpolation and a result output having the address input the memory circuit arrangement, lines for addressing the Memory cells serve, as well as lines connected to the coefficient input and the result output of the interpolation circuit connected to the data output of the memory circuitry. The lines connected to the coefficient input correspond address bits low priority. In this way it is possible, though for example, two lines connected to the coefficient input are present by entering addresses 0, 4, 8 (located in do not distinguish their two lowest bits) at the address input the memory circuit arrangement each aufeinanderfol lowing addresses the memory circuit to address, and by entering addresses 1, 5, 9, ...; 2, 6, 10 or 3, 7, 11 ... to address the same memory cells and at the same time weighting factors ¼, ½, ¾, for the interpolation circuit on the two low-order lines.

There for one Interpolation at least two output values are needed and these as fast as possible, should preferably be available simultaneously, is preferably as a storage element uses a dual-port RAM, which is the simultaneous query of two memory locations allowed.

The needed Address of the second memory is expediently by an incrementing generated to address those of the memory cells Lines connected to one transmitted on the lines address value to increment. This incremented address value will be used for addressing of the second address entry of the dual-port RAM used.

Further Features and advantages of the invention will become apparent from the following Description of exemplary embodiments with reference to the figures.

It demonstrate:

1 a block diagram of a memory circuit arrangement according to the invention; and

2 the result obtained in reading data from the memory circuitry in relation to a received signal by the sampling of which the data stored in the memory circuitry has been obtained.

In the 1 a memory circuit shown as a block diagram has an address input 1 with a width of n bits. Two coefficient lines 9 are to the least significant bits of the address input 1 connected, the higher order bits are over address lines 8th to a first address entrance 11 a dual port RAM 3 connected. A second address entrance 12 of the dual-port RAM 3 is with the address lines 8th connected via an incrementing circuit, over which it always receives an address value which is greater by 1 than that at the same time at the first address input 11 attached value.

Two data outputs of the dual-port RAM 3 are at data inputs 5 . 6 an interpolation circuit 4 connected and deliver to these at the same time in each case the values in the over the address inputs 11 . 12 addressed memory cells are stored.

The interpolation circuit performs a linear interpolation on the data inputs 5 . 6 values for the weighting of the values at their coefficient input 7 over the coefficient line 9 adjacent two least significant bits of the input to the circuit arrangement address uses.

The result output of the interpolation circuit 4 simultaneously forms the data output 2 the circuit arrangement. For the application of the circuit arrangement, it is sufficient to enter the measured data to be interpolated in their time sequence in the dual-port RAM. The behavior of the circuit is then indistinguishable from that of a four times as large memory circuit in which the same measurement data are stored with intercalated, pre-calculated interpolation data.

2 shows as a solid curve 20 the course of a function or a measurement signal, by the sampling of which at two successive times x1 and x2 a pair of samples, represented by the arrows 21 . 22 that was obtained in the dual-port RAM 3 stored at consecutive addresses. By entering the address of the sample 21 on the n-2 more significant bits of the address input 1 Both samples are addressed and appear at the data inputs 5 . 6 the interpolation circuit. If the two least significant bits at the address input 0 are equal to the exact addressing of the sample 21 , The interpolation circuit 4 therefore evaluates the sample 22 with the value coded on the coefficient line 0 and the value 21 with its complement 1 so that the value 21 as output at the data output 2 appears. If the value on the coefficient line is a value m other than Q, the value is weighted 22 with m / 4 and that of value 21 with the complement, and a correctly interpolated intermediate value, corresponding to one of the dashed arrows 23 , is at the data exit 2 receive.

Depending on the required resolution or interpolation, the circuit arrangement according to the invention can also be only a single coefficient line 9 or more than two.

Of course, the invention is not limited to linear interpolation. In order to carry out a higher-order interpolation with more than two output values, it is sufficient to have the number of incrementing circuits and the inputs and outputs of the memory 3 to multiply and use a corresponding interpolation circuit. It is also conceivable, for example, for an interpolation fit four output values, the same dual-port RAM as in the circuit arrangement of 1 and to read out the required output values for the interpolation in two consecutive accesses and to buffer them if necessary.

Claims (3)

Memory circuit arrangement with an address input ( 1 ) and a data output ( 2 ) and a memory circuit ( 3 ) having a plurality of addressable memory cells and an interpolation circuit ( 4 ) with at least one data input ( 5 . 6 ) for data to be interpolated, characterized in that the interpolation circuit ( 4 ) a coefficient input ( 7 ) for inputting weighting coefficients of the interpolation and a result output, the address input ( 1 ) Cables ( 8th ), which are used to address the memory cells, and lines ( 9 ) associated with the coefficient input ( 7 ) and the result output of the interpolation circuit with the data output ( 2 ), with the coefficients input ( 7 ) connected lines ( 9 ) Are address bits of low significance and an incrementer circuit ( 10 ) provided to address the memory cells ( 8th ) is connected to one on the lines ( 8th ) to increment the transmitted address value. Memory circuit arrangement according to Claim 1, characterized in that the memory circuit ( 3 ) is a dual port RAM. Memory circuit arrangement according to Claim 2, characterized in that the dual-port RAM ( 3 ) a first address input ( 11 ) connected to the lines ( 8th ) is connected directly, and one with the incrementing circuit ( 10 ) second address input ( 12 ) having.