DE19932944B4 - Circuit arrangement for driving a load - Google Patents
Circuit arrangement for driving a load Download PDFInfo
- Publication number
- DE19932944B4 DE19932944B4 DE1999132944 DE19932944A DE19932944B4 DE 19932944 B4 DE19932944 B4 DE 19932944B4 DE 1999132944 DE1999132944 DE 1999132944 DE 19932944 A DE19932944 A DE 19932944A DE 19932944 B4 DE19932944 B4 DE 19932944B4
- Authority
- DE
- Germany
- Prior art keywords
- load
- driving
- switching device
- circuit arrangement
- semiconductor switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
- H03K17/164—Soft switching using parallel switching arrangements
Landscapes
- Electronic Switches (AREA)
- Dc-Dc Converters (AREA)
Abstract
Es wird eine Schaltungsanordnung zur Ansteuerung einer Last vorgeschlagen, die eine Schaltvorrichtung aufweist, die seriell mit der Last zwischen einem ersten und einem zweiten Versorgungspotentialanschluß verschalten ist. Eine Steuervorrichtung steuert die Schaltvorrichtung leitend oder sperrend. Die Schaltvorrichtung weist dabei einen ersten und zumindest einen zweiten Halbleiterschalter auf, die mit ihrer Laststrecke parallel verschalten sind und deren Steueranschlüsse miteinander gekoppelt sind. Durch ein verzögertes Schalten des ersten und des zweiten Halbleiterschalters findet eine Flankenverrundung im Stromverlauf statt, so daß die elektromagnetische Abstrahlung verringert ist.It is proposed a circuit for driving a load having a switching device, which is connected in series with the load between a first and a second supply potential terminal. A control device controls the switching device conducting or blocking. The switching device has a first and at least one second semiconductor switch, which are connected in parallel with their load path and whose control terminals are coupled together. By a delayed switching of the first and the second semiconductor switch edge rounding takes place in the current waveform, so that the electromagnetic radiation is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1999132944 DE19932944B4 (en) | 1999-07-14 | 1999-07-14 | Circuit arrangement for driving a load |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1999132944 DE19932944B4 (en) | 1999-07-14 | 1999-07-14 | Circuit arrangement for driving a load |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19932944A1 DE19932944A1 (en) | 2001-02-08 |
DE19932944B4 true DE19932944B4 (en) | 2005-10-20 |
Family
ID=7914758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1999132944 Expired - Fee Related DE19932944B4 (en) | 1999-07-14 | 1999-07-14 | Circuit arrangement for driving a load |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE19932944B4 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10301693B4 (en) | 2003-01-17 | 2006-08-24 | Infineon Technologies Ag | MOSFET circuit with reduced output voltage oscillations at a shutdown |
US20140103897A1 (en) * | 2012-10-17 | 2014-04-17 | Qualcomm Incorporated | Glitch suppression in dc-to-dc power conversion |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393337A (en) * | 1978-03-25 | 1983-07-12 | Sony Corporation | Switching circuit |
GB2184622A (en) * | 1985-12-23 | 1987-06-24 | Philips Nv | Output buffer having limited rate-of-change of output current |
EP0332301A2 (en) * | 1988-03-10 | 1989-09-13 | Advanced Micro Devices, Inc. | Time variant drive for use in integrated circuits |
EP0572706A1 (en) * | 1992-06-05 | 1993-12-08 | Siemens Aktiengesellschaft | Control circuit for a power-FET with a load connected to its source |
US5834860A (en) * | 1992-11-25 | 1998-11-10 | Sgs-Thomson Microelectronics Ltd. | Controlled impedance transistor switch circuit |
-
1999
- 1999-07-14 DE DE1999132944 patent/DE19932944B4/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393337A (en) * | 1978-03-25 | 1983-07-12 | Sony Corporation | Switching circuit |
GB2184622A (en) * | 1985-12-23 | 1987-06-24 | Philips Nv | Output buffer having limited rate-of-change of output current |
EP0332301A2 (en) * | 1988-03-10 | 1989-09-13 | Advanced Micro Devices, Inc. | Time variant drive for use in integrated circuits |
EP0572706A1 (en) * | 1992-06-05 | 1993-12-08 | Siemens Aktiengesellschaft | Control circuit for a power-FET with a load connected to its source |
US5834860A (en) * | 1992-11-25 | 1998-11-10 | Sgs-Thomson Microelectronics Ltd. | Controlled impedance transistor switch circuit |
Also Published As
Publication number | Publication date |
---|---|
DE19932944A1 (en) | 2001-02-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |