DE19918049C2 - Non-volatile ferroelectric memory without cell plate lines and method of operating the same - Google Patents

Description

The invention relates to a semiconductor memory, more particularly a non-volatile ferroelectric memory SWL (split Word Line = subdivided word line) structure.

Ferroelectric memory, i. H. ferroelectric direct to handle memory (FRAM) with a data speed that corresponds to that of DRAMs, as they are generally half conductor memory can be used to pull the memory attention of the next generation, since they are the ge keep stored data even when none There is tension on them.

FRAMs are memory devices with almost the same structure as that of DRAMs, however, as mentioned, their data are not erased even when no electric field is present, since a ferroelectric material with high residual polarization is used. In other words, as illustrated by the hysteresis loop of FIG. 1, polarization caused by an electric field does not disappear due to the presence of spontaneous polarization even when an electric field is removed, but it remains a constant state (states d and a) maintained. This component is used as a memory in that the states d and a correspond to the logical states 1 and 0, respectively.

Referring to the figures, a conventional fer Roelectric memory explained as follows.

Fig. 2 is a cell array structure of a conventional ferroelectric memory. The unit cell structure of this conventional FRAM consists of a transistor and a capacitor (1T / 1C), which is similar to existing DRAMs. That is, a plurality of word lines separated by equal spaces are formed in one direction. A plurality of plate lines are formed between the word lines in parallel therewith. A plurality of equally spaced bit lines (B_n, B_n + 1, B_n + 2,...) Is formed perpendicular to the word and plate lines. The gate electrodes of a transistor forming a unit memory cell is connected to the word line W / L, and the source electrode of this transistor is connected to the bit line B / L adjacent to it. The drain electrode of the transistor is connected to a first electrode of a capacitor, and the second electrode of the capacitor is connected to the plate line P / L adjacent to it.

The drive circuit and the way it uses a ferroelectric  Memory with the conventional 1T / 1C- Structure operates are explained as follows.

FIGS. 3A and 3B show a diagram of the driving circuit of a conventional ferroelectric memory. Since the drive circuit of a ferroelectric SpeI Chers with conventional 1T / 1C structure a a reference voltage generating reference voltage generator 1, a plurality of transistors Q1-Q4 and a capacitor C1 provides the output tension generated by the reference voltage generator 1 may voltage signal not be placed directly at the sense amplifier. Therefore, the drive circuit is constructed to have a reference voltage stabilizing circuit 2 for stabilizing the reference voltage on two adjacent bit lines, a first reference voltage storage circuit 3 composed of a plurality of transistors Q6-Q7 and capacitors C2 and C3, and reference voltages of logic value 1 and stores the logical value 0 on their respective adjacent bit lines, a first equalization circuit 4 , which consists of a transistor Q5 and balances the two adjacent bit lines, a first main cell array 5 , which is connected to the various word lines and plate lines and stores data , a first sense amplifier 6 , which consists of a plurality of transistors Q10-Q14 and p-sense amplifiers (PSA) and detects the data value of a cell selected in the first main cell array 5 by the word line, a second main cell array 7 , which uses different word and plate lines connected i st and stores data, a second reference voltage storage circuit 8 , which consists of a plurality of transistors Q27 and Q28 and capacitors C9 and C10 and stores reference voltages of logic value 1 and logic value 0 on their adjacent bit lines, and a second sense amplifier 9 includes that of a plurality of transistors Q15-Q24 and an n-sense amplifier (NSA) and detects the data value of the cell selected by the word line in the second main cell array 7 .

The input and output operations of a ferroelectric memory cell with the conventional 1T / 1C structure are the following.

Fig. 4 is a timing chart showing the operation in the write mode of the conventional ferroelectric memory, and Fig. 5 is a timing chart showing the operation in the reading mode thereof.

The write mode starts when a chip select signal CSBpad through a transition from a high to a low Zu stand is activated and at the same time an enable signal WEBpad changes from high to low.

When an address decoding operation begins in write mode, changes to the corresponding word line W / L Impulse from high to low state and it becomes a Cell selected. So in the interval in which the word line assumes the high state, a high signal with fixed interval and a low signal with a fixed inter vall in turn to the corresponding plate line P / L applied, and a synchroni with the write enable signal Fixed high or low signal will correspond to the de bit line applied to a high or low logi write the value into the selected cell.

In other words, the interval in which a high signal comes on there is a bit line and a high pulse to a word line is created, the logical value 1 in the corre sponding ferroelectric capacitor inscribed if a low pulse is applied to the plate line.  

When a low pulse is applied to a bit line and a high pulse is applied to a word line the logical value 0 in the corresponding ferroelectric Capacitor registered.

Operation when reading one into a cell in write mode The data value written is as follows.

If the chip selection signal CSBpad is activated by changing from high to low state, all bit lines are set to the same potential by a compensation signal before the corresponding word line is selected. If e.g. For example, if a high pulse is applied to the equalization circuit 4 shown in FIG. 3A and a high signal is applied to transistors Q18 and Q19, the bit lines for these transistors are grounded and brought to the same potential.

After each bit line by turning off the transistors Q5, Q18 and Q19 was made inactive and the address deco the signal of the corresponding word line changes by means of the decoded address from the low to the high state so that the corresponding cell is selected becomes.

By applying a high signal to the plate line of the selected cell will correspond to the logical value 1 Corresponding data value in the ferroelectric memory destroyed. However, if the data value corresponding to logical value 0 stored in the cell, it is not destroyed.

So there are different output signals than one another destroyed data value and an undestroyed data value correspond according to the hysteresis curve described above, and they are assigned a logical value of 1 or 0 by the sense amplifier  detected.

The case in which the data value is destroyed corresponds to the transition from point d to point f on the hysteresis loop of FIG. 1, and the case in which the data value is undamaged corresponds to the transition from point a to point f. Therefore, the output signal of the sense amplifier has the logic value 1 if it is activated by an enable pulse and the data value is destroyed. In contrast, the output signal of the sense amplifier has the logic value 0 when it is activated by an enable pulse, but the data value is not destroyed.

To restore the original state in the memory len after the sense amplifier has acquired the data value has amplified the detected signal and an output signal has created, the plate line is inac under the condition tiv made that a high impulse to the corresponding Word line is created.

With conventional ferroelectric memory with 1T / 1C Structure tends to function as the reference cell is affected quickly since it has a lot more data input and output operations as a main memory cell executes.

With conventional ferroelectric memories and their type Control circuits have the following problems.

A first problem is that a conventional one FRAM a complicated because of the divided plate lines t layout, but the advantage is that maintain the data even when the power is off stay.  

A second problem is that of speed of a conventional FRAM is reduced because the data is aisle and exit operations through separate record line are done and for the data reading and writing opera a control signal is applied to the plate lines becomes.

A third problem is that the reference voltage is not stable since a reference cell is all read operations a few hundred main memory cells processed, why with regard to the reference voltage, a quick impairment supply occurs.

A fourth problem is that the process for Generate the reference voltage through a voltage setting circuit is not stable because of the reference voltage Fluctuations in the external supply voltage influenced becomes a characteristic change due to external interference signals memory.

A fifth problem is that there is no high speed access is achieved because the ferro electrical memory only the chip selection signal CSBpad ver is applied.  

DE 693 13 785 T2 describes a non-volatile ferroelectric memory known with a variety of unit cells, each from a memory cell with a transistor and ferroelectric capacitor and a Be pull cell exist, which also have a transistor and a ferroelectric Has capacitor. To control the unit cells are divided Word lines are provided so that the reference cell and the memory cell un can be controlled depending on each other. The capacitors are in usually connected on the one hand with plate lines while their on whose electrodes via the transistors with a bit line or a Be train bit line are connected.

EP 0 671 745 A2 describes a semiconductor memory device with a Memory cell array that can be controlled via X and Y decoders. The single ones Cells of the memory cell array are usually over word and bit lines lines controllable, the ferroelectric capacitors in known Are connected with an electrode to a plate line.

The invention has for its object a non-volatile ferroelectric to create memory with divided word lines, which the Usen of separate cell plate cables is unnecessary. Furthermore, a procedure is ren to operate such a memory are provided.

This object is achieved by the subject matter of the independent claims solves. Advantageous further developments and refinements are in the respective Subclaims described.

The accompanying drawings illustrate embodiments play the invention and serve together with the description Exercise to explain the principles of the invention.

Fig. 1 is a characteristic curve showing a hysteresis loop of a conventional ferroelectric substance;

Fig. 2 shows a conventional cell array structure of a ferroelectric memory;

Figs. 3A and 3B are block diagrams of a drive TIC for the conventional ferroelectric memory;

Fig. 4 is a timing chart illustrating the operation of the conventional ferroelectric memory in the write mode;

Fig. 5 is a timing chart illustrating the operation of the conventional ferroelectric memory in the read mode;

Fig. 6 is a block diagram of a Treibersteuerungs- and data input / output circuit of a fer roelektrischen invention SWL memory;

Fig. 7 is a block diagram of a cell array of a memory according to the invention;

Fig. 8 is a detailed block diagram of the cell array in the memory of the present invention;

Fig. 9 shows the structure of a basic memory cell of a memory according to the invention;

Fig. 10 is a block diagram of a unit driver control and data input / output circuit in the memory according to the invention;

Fig. 11 is an operational flowchart for explaining the relationship between a bit line level and a reference level;

Fig. 12, the memory cell array structure shows an OF INVENTION to the invention the memory;

Fig. 13, reference cell array structure shows an OF INVENTION to the invention the memory;

Fig. 14 shows a block diagram of the bit line control circuit of a memory according to the invention;

Figure 15 shows capacitive components of each node in the circuit of Figure 14;

Fig. 16 is a timing chart for the operation of the inventive memory;

Fig. 17 shows the variation of the bit line potential and the potential at the input and output nodes when a sense amplifier is in operation;

Fig. 18 shows a block diagram of a global control pulse generator in the invention;

FIG. 19A shows timing pulse generator, an operation diagram for the Global when the Y-address is reciprocally connected and forth;

Fig. 19B shows an operational flowchart for the global control pulse generator when addresses X, Z are switched;

Fig. 20 shows a block diagram of a local control pulse generator in the invention;

Fig. 21 shows a circuit of the sense amplifier and its input and output control in the first embodiment of the invention;

Fig. 22 shows a circuit of the sense amplifier and its input and output control in the second embodiment of the invention;

Fig. 23 shows the structure of a column control circuit in the invention;

Fig. 24 shows the structure of a reference bit line level control circuit in the first embodiment of the invention;

Fig. 25 shows the structure of a reference bit line level control circuit in the second embodiment of the invention;

Fig. 26 shows a circuit of the sense amplifier and its input and output control in the third embodiment of the invention;

Fig. 27 shows a circuit of the sense amplifier and its input and output control in the fourth embodiment of the invention;

Fig. 28 shows waveforms for the operation of the local control pulse generator in the write mode when the address Y changes;

Fig. 29 shows waveforms for the operation of the pulse generator Lokalsteue approximately in the read mode, when Y address is changed;

Fig. 30 shows waveforms for the operation of approximately Lokalsteue pulse generator in the write mode, when addresses X, change Y; and

Fig. 31 shows waveforms for the operation of the local control pulse generator in the read mode when addresses X, Y change.

Now the cell array structure, the driver control scarf device and a method for operating an inventive non-volatile ferroelectric memory with reference explained in detail on the accompanying figures.

Fig. 6 is a block diagram of the Treibersteuerungs- and data input / output circuits showing an embodiment of a ferroelectric memory according to the invention SWL. This circuit includes an X address buffer 11 for buffering addresses X under externally supplied addresses X, Y and Z; an X predecoder 12 for predecoding the output signal of the X address buffer 11 ; a Z address buffer 13 for buffering addresses Z at said addresses X, Y and Z; a Z predecoder 14 for predecoding the output of the Z address buffer 13 ; an (X, Z-ATD) generator 15 for detecting address transition points of the signals for the addresses X and Z as received by the X address buffer 11 and the Z address buffer 13 , respectively; a global control pulse generator 16 for receiving the output signal of the (X, Z-ATD) generator 15 and an externally supplied signal CSBpad in order to generate a voltage switch-on detection signal itself and then a basic pulse relating to the memory control depending on the (X, Z-ATD ) Signal, from the CSBpad signal and from the power-on detection signal; a Y address buffer 17 for buffering addresses Y at said addresses X, Y and Z, a Y predecoder 18 for predecoding the output signal of the Y address buffer 17 ; a Y-ATD generator 19 for detecting an address transition point of the signal for the Y address as obtained from the Y address buffer 17 and for generating a Y-ATD signal; a local control pulse generator 20 for generating a pulse as required for each memory block by combining the output signal from the global control pulse generator 16 , the Z predecode signal from the Z predecoder 14 and the output signal from the Y-ATD generator 19 ; an X post decoder 21 for combining the X predecoder signal and the Z predecoder signal as obtained from the X predecoder 12 and the Z predecoder 14 , respectively, and to select the corresponding memory cell block; a SWL driver 22 for combining the Ausgangssi obtained from the X-Nachdecodierer 21 and the local control pulse generator 20 gnale and for driving each divided word line SWL each cell block 23; a column controller 24 for combining the output signals obtained from the Y predecoder 18 and the local control pulse generator 20 and for selecting the corresponding bit line; a sense amplifier input / output controller 25 which combines the output signals from the local control pulse generator 20 and column controller 24 and controls the operation and input / output of the sense amplifier; and an input / output bus controller 26 that interfaces between an external data bus and the sense amplifier input / output controller 25 .

This structure of the cell array in the SpeI according to the invention cher is explained as follows.  

Fig. 7 shows a block diagram of the cell array of a memory according to the invention, and Fig. 8 shows a detailed block diagram of this cell array. Fig. 9 shows the structure of a memory cell of the memory according to the invention.

In Fig. 7, the basic structure of the array is shown cherblöcken of Einheitsspei, wherein the circuit arrangement is divided into three blocks.

There are a SWL driver block 70 corresponding to each unit memory block and a cell array block 71 containing a main memory cell array block and a reference cell array block corresponding to each unit memory block. A core block 72 , which contains both a column control circuit block and a sense amplifier array block, is divided into two parts per unit memory block, which are common to two adjacent unit memory blocks.

The detailed structure of the memory array will now be explained with reference to FIG. 8.

First, the SWL driver block 70 is repeatedly constructed so that it contains a first and a second divided word lines SWL1 and SWL2 as the basic pair. In other words, each pair consists of lines SWL1_n and SWL2_n, SWL1_n + 1 and SWL2_n + 1, SWL1_n + 2 and SWL2_n + 2, SWL1_n + 3 and SWL2_n + 3,. , ,

The cell array block 71 is a group having a main memory cell array block 73 and a reference cell array block 74 . There are four memory cell arrays B_n, B_n + 1, B_n + 2 and B_n + 3 in the main memory cell array block 73 , and in the reference cell array block 74 there are two reference cell arrays RB_n, and RB_n + 1.

Another cell array block is in the same way with four other memory cell arrays B_n + 4, B_n + 5, B_n + 6 and B_n + 7 and two other reference cell arrays RB_n and RB_n + 1 in one Group trained.

Here, the main memory cell array block 73 consists of four columns of memory cell arrays, but it can be made up of any even number of columns, such as 6, 8, 10, etc. A core block 72 with both a bit line control circuit block 75 and a reference bit line control circuit block 76 is pro Unit block of memory divided into two parts. Each of the two parts is common to two adjacent unit memory blocks, and they lie symmetrically at the two ends of a cell array block 71 . Bit line control circuit block 75 includes a sense amplifier block for performing data read and write operations for a memory cell, and a write control circuit.

In the cell array block 71 , two divided word lines are arranged in a pair, such as (SWL1_n and SWL2_n), (SWL1_n + 1 and SWL2_n + 1),. , ., wherein a plurality of the pairs are arranged in one direction in the cell array block 71 , and a plurality of bit lines B_n, B_n + 1, B_n + 2,. , , is arranged at right angles to the divided word lines.

The bit line control circuit block 75 in each of the main cell array groups and the reference cell array groups consists of one of the main cell columns and a reference cell column.

There are two bit line control circuit blocks 75 at the bottom left. Each of the blocks consists of a pair of a main cell column B_n and a common reference cell column RB_n and a pair of a main cell column B n + 2 and a common reference cell column RB_n.

At the bottom right, at the penultimate position from the right, there are also two bit line control circuit blocks 75 . Each of the blocks consists of a pair of a main cell column B_n + 4 and a common reference cell column RB_n + 2 and a pair of a main cell column B_n + 6 and a common reference cell column RB_n + 2.

There are two bit line control circuit blocks 75 in the upper left. Each of the blocks consists of a pair of a main cell column B_n + 1 and a common reference cell column RB_n + 1 and a pair of a main cell column B_n + 3 and a common reference cell column RB_n + 1.

There are also two bit line control circuit blocks 75 in the top right at the penultimate position from the right. Each of the blocks consists of a pair of a main cell column B_n + 5 and a common reference cell column RB_n + 3 as well as a pair of a main cell column B_n + 7 and a common reference cell column RB_n + 3.

At the intersections between each divided word line and each bit line, unit cells exist, the structure of which is shown in more detail in FIG. 9.

Fig. 9 shows the structure of a basic memory cell. This cell contains a first NMOS transistor T1 92, the gate of which is connected to a first divided word line SWL1 90; a second NMOS transistor T2 93 whose gate is connected to a second divided word line SWL2 91; a first ferroelectric capacitor C1 94, one electrode of which is connected to the source of the first transistor 92 and the other electrode of which is connected to the second divided word line 91 ; and a second ferroelectric capacitor C2 95, one electrode of which is connected to the first divided word line 90 and the other electrode of which is connected to the source of the second transistor 93 .

Here, the drain of the first transistor 92 is connected to the bit line Bit_n, and the drain of the second transistor 93 is connected to the bit line Bit_n + 1.

Two data values can be stored in this unit memory cell get saved. A pair of a first and one second divided word lines SWL1 and SWL2 form one Row address, and a pair of bit lines Bit_n and Bit_n + 1 form two columns.

A detailed explanation is now given for each block of memory with this array structure.

First, the unit driver control and data on Gabe / output circuit in the invention as follows builds to problems like impairing a dummy cell (dummy cell) and instability of the reference voltage during generation to overcome the reference level.

Fig. 10 shows a block diagram for the unit driver control and data input / output circuit in the memory of the present invention, and Fig. 11 illustrates an operation flowchart for explaining the relationship between a bit line level and a reference level.

Fig. 10 shows a structure of two ferroelectric SWL memory cells and shows the unit driver control and data input / output circuit. This driver control and data input / output circuit consists of a unit cell with a first transistor T1, one electrode of which is connected to the Nth bit line BIT_N; a second transistor T2, one electrode of which is connected to the (N + 1) -th bit line BIT_N + 1; a pair of word lines, namely first and second divided word lines SWL1 and SWL2, each connected to the gates of the two transistors T1 and T2; a SWL driver 100 connected to the first and second divided word lines SWL1 and SWL2 and applying SWL drive signals to the word lines; a reference level generator 101 for generating a reference level to be used in sense amplifiers 102 a and 102 b, which are connected to the bit lines BIT_N and BIT_N + 1; and column decoders 103 a and 103 b, which transmit the output data from the sense amplifiers 102 a and 102 b to data bus lines by means of address signals Y_N and Y_N + 1.

Here, the cells N and N + 1, which work for a pair of word lines with the same row address but have different operating pulses from one another, are distinguished by the column address signals Y_N and Y_n + 1, as are applied to the column decoders 103 a and 103 b ,

The reference level generator 101 generates a reference level, as required for the acquisition of data, and it applies the reference level signal via a reference line REF to the sense amplifiers 102 a and 102 b.

In Fig. 11, the relationship between the bit line level signal and the reference level signal at a main cell in the reading mode in the memory of the present invention with the above-described driver control and data input / output circuit for the time before and after the selection of a cell is Darge ,

Referring to FIG. 11, the time is divided into three intervals, namely a pre-charge interval, a cell data transmission interval and a sense amplifier interval. The first precharge interval is used to preload the bit line level and the reference level to the low level before the word line is activated.

The second cell data transfer interval is used to transport the main memory cell data value to the bit line and the output data value from the reference level generator 101 to the reference line.

The third sense amplifier interval is used so that the sense amplifier 102 a and 102 b operated by the column decoders 103 a and 103 b amplify the difference between the data level on the bit line and the data level on the reference line REF and then the amplified signal to the Return bit line.

The structure of the main memory cell array block 73 of the unit memory block of the memory according to the present invention is shown in detail in FIG. 12, and the reference cell array block 74 is shown in FIG. 13.

Referring to FIG. 12 does not exist Zvi rule at all intersections divided word lines (SWL1_n and SWL2_n), (SWL1_n + 1 and SWL2_n + 1). , , and bit lines B_n, B_n + 1, B_n + 2,. , , a memory cell. In view of a special subdivided word line, it looks as if a memory cell is arranged on every next but one bit line, which is why a folded bit line is formed.

Therefore, it looks like the SWL cells are in view to the SWL array of the unit memory block on rectangular Arranged way. So a memory cell of an even number  or an odd-numbered bit line of the divided Word lines are assigned. This means that in the SWL Cell array equal to a pair of SWL word lines SWL1 and SWL2 must be activated in good time.

In the same way, two bit lines form a folded one Bit line structure if the SWL memory cell in a Column is arranged and the lines SWL1 and SWL2 of the Main cell arrays with the lines SWL1 and SWL2 of the SWL Reference cell are connected.

The structures of the bit line control circuit and the read amplifier with this memory cell array as well as the reference Cell array structures in the invention will now be as follows explained.

FIG. 14 shows a block diagram of the bit line control circuit of a memory according to the invention, and FIG. 15 shows the capacitive components of each node in the circuit of FIG. 14.

Fig. 14 shows the basic structure of the Bitleitungssteuerschal processing of the memory according to the invention. This control circuit includes a plurality of transistors T21, T22, T23 and T24 which are switched on by the activated first control signal C1 and a plurality of bit lines B_n, B_n + 1, B_n + 2, B_n + 3,. , , with input and output nodes B1, B2, B3, B4,. , , connect; a plurality of transistors T25 to T28, which are switched on by the activated second control signal C2 and a reference bit line RB0 with the input and output nodes R1, R2, R3, R4,. , , links; a bit line level controller 140 for controlling the level by the third control signal C3; and a pull-up transistor PU0 which applies a pull-up voltage VCC to a reference bit line RB10 in accordance with a fourth control signal C4.

The explanation of the capacity at each node is in the bit line control circuit of this basic structure the following.

First, the capacitive component of each bit line is the Main memory cell area with Cb_n, Cb_n + 1, Cb_n + 2,. , , and the capacitive component of the reference bit direction of the reference cell area is designated Crb0. The capacitive components for other areas are through Cr1, Cr2, Cr3,. , , and Cb1, Cb2, Cb3,. , , designated. Then the circuit is designed as follows.

The number of memory cells that the main memory cells array and the reference cell array with the bit lines det corresponds to the number of reference cells, so that consequences The following applies: Cb_n = Crb0, Cb1 = Cr1, Cb2 = Cr2, Cb3 = Cr3 and Cb4 = Cr4. The number of bit lines in the main cell array is determined so that the condition Crb0 = n.Cr1 is fulfilled is. The bit therefore applies to the total capacity Cbit_total line in connection with the main memory cell the fol end: Cbit_total = Cb_n + Cb1. However, if Cb_n »Cb1 applies, applies Cbit_total = Cb_n. For the total capacity Crbit_total of the bit line in connection with the reference cell: Cbit_total = Crb_n + n.Cr1. The total capacity of the bitlei device in connection with the main memory cell is the dop the total capacity of the bit line in connection with the reference cell.

The data input / output circuit with this structure in the invention is explained as follows.

Fig. 16 shows a time-related diagram for the operation of the memory according to the invention, and Fig. 17 shows the variation of the bit line potential and the potential at the input and output node when the sense amplifier is in operation.

First switch when the first control signal C1 to the high state is activated, the NMOS transistors T21 to T24 on, and therefore bit lines B_n, B_n + 1, B_n + 2, B_n + 3,. , , of the main memory cell area electrically with the input nodes B1, B2, B3, B4,. , , connected. If the second control signal C2 is activated to the high state , the NMOS transistors T25 to T28 turn on towards the bit line RB0 of the reference memory cell area electrically with the input / output nodes R1, R2, R3, R4, , , , is connected.

Thus, when the third control signal C3 is activated under the condition that the first and second control signals C1 and C2 are in the high state, transistors T29 to T40 in the bit line level controller 140 are active, and then the bit line of the main memory cell and the bit line of the reference cell correspond to one another, at the same time being pulled down to the ground level.

By holding the first and second control signals in the ho hen state becomes the third control signal C3 at the time disabled to which the balancing and pulling down are reached.

The fact that two word lines SWL1 and SWL2 on the high State to be made active after the third tax sig nal has been deactivated, those in the main memory cells transfer stored data via B_n to B_n + 3 to B1 to B4 gene, and the data value stored in the reference cell becomes transmitted to R1 to R4 via RB0.  

When the data values stored in all cells are complete dig are transmitted to the main or reference bit lines, the transistors T21 to T28 are switched off, that the first and second control signals are low State can be deactivated.

Under these conditions, by setting a signal SAP low and a signal SAN high to make the sense amplifier (not shown in Figs. 14 and 15) active, respectively on R1 to R4 and B1 to B4 transmitted tiny voltage amplified.

When the amplification process is complete, the data amplified by the sense amplifier on B1 to B4 er thereby to the bit lines B_n to B_n + 3 of the main memory cell transmit that the first control signal the high state is activated.

Furthermore, the destroyed logical data value becomes 1 again in the reference memory cell, the reference bit device is set to the high level by the fourth Control signal is made active at the high level and the NMOS transistor PUO is turned on. Under this condition tion in the reference and main memory cells disrupted data restored by taking turns a low and a high voltage on the word lines SWL1 and SWL2 can be created. If the restore is completed, the sense amplifier is de activated that the word lines SWL1 and SWL2 and the ers te and fourth control signal brought to low voltage and the signal SAN to low voltage and the Sig nal SAP are brought to high tension.

The basic structure of the data input / output circuit at The invention is aimed at being for everyone  ferroelectric areas thereby the same property Changes shows that the number of main memory cells len, which is accessed 72686 00070 552 001000280000000200012000285917257500040 0002019918049 00004 72567n, the number of reference cells, accessed, made the same.

Therefore, the relationship between the bit line voltage for the reference cell and the bit line voltage for the main memory cell is kept constant which is why the operation of the sense amplifier stabilizes and the lifespan of the chip is extended.

According to Fig. 17, even if the capacity of the Be zugszelle equal to the capacity of the main memory cell and the logic value is chert vomit in the two cells 1, the change of the bit line voltage in the memory cell is greater than in the reference cell.

When logic 1 is stored in the reference cell and logic 0 is stored in the main memory cell, the change in bit line induction voltage in the reference cell is larger than that in the main memory cell. In other words, when the state for logic value 1 and logic value 0, as stored in the main memory cell, is approximately half of the bit line induction voltage, a bit line voltage of the reference cell is generated. Therefore, when a circuit is constructed according to the same condition as that of FIG. 15 and the logic value 1 is stored in the reference cell, it is determined exactly whether the data value stored in the main memory cell has the logic value 1 or the logic value 0.

The driver control circuit of a memory according to the invention with this basic structure of the input / output circuit is explained as follows.  

In the driver circuit of a memory according to the invention, the core block technology includes a local control pulse generator 20 , a Y address buffer 17 , a Y-ATD generator 19 , an X post-decoder 21 , a Y pre-decoder 18 , a column controller 24 and a sense amplifier input / output Controller 25 , which is constructed around a SWL cell array 23 as a center, and the SWL driver 22 of Fig. 6, which shows the overall structure of the driver control circuit.

In other words, in this embodiment of a memory according to the invention, blocks are used to control the data input / output operations around the local control pulse generator 20 .

First, the global control pulse generator that supplies the local control pulse generator 20 with various operating pulses will be briefly explained as follows to understand the flow of the various control signals in detail.

Fig. 18 shows a block diagram for the global control pulse generator in the invention, and Figs. 19A and 19B show an operational flowchart therefor.

The global control pulse generator 16 includes an input buffer 31 for receiving a CSBpad signal and one of X, Z-ATD signals from an (X, Z-ATD) generator and a power-on detection signal that includes CSBpad to provide first and second synchronizing signals produce; a low voltage operation and noise reduction circuit 32 for receiving a feedback signal and the first synchronizing signal of the input buffer 31 and generating a low voltage detection signal for stopping operation when the voltage is low to produce a trouble-free signal from which noise signals are deleted from the first synchronizing signal , and for generating a pre-activation pulse signal; a first controller 33 for generating a first control signal for controlling the start point for the sense amplifier activation time by receiving the trouble-free signal when a normal supply voltage is supplied from the low voltage operation and noise reduction circuit 32 , a second control signal for controlling the start points for the first control signal for the column selection time and for pulling up the bit line, and a third control signal for generating an input signal for the SWL driver as well as their control signals; a second controller 34 for receiving the third control signal of the first controller 33 for subsequently generating a pair of basic waveform generation signals S1 and S2 for the pair SWL1 and SWL2 of the SWL driver, and a fourth control signal which is a basic pulse signal for controlling the active interval the signals S1 and S2, as a feedback signal for the low voltage operation and noise reduction circuit 32 and for outputting a pulse signal P2 which is an improved fourth control signal to have higher driving powers; a third controller 35 for receiving the first and second synchronizing signals of the input buffer 31 and the fourth control signal of the second controller 34 for subsequently generating a fifth control signal for controlling them in such a manner that they are synchronized with the signal CSBpad, if all Signals with the exception of the signals S1 and S2 are deactivated, and a sixth control signal for outputting the activation state of the signals S1 and S2 upon completion of normal operation of the same when the signal CSBpad is deactivated under the condition that the signals S1 and S2 are active ; and a fourth controller 36 for receiving the fifth and sixth control signals from the third controller 35 , the first, second and third control signals from the first controller 33, and the pre-activation pulse signal from the low voltage operation and noise reduction circuit 32 to subsequently generate an activation signal SAN for the NMOS Element of the sense amplifier, an activation signal SAP for the PMOS of the sense amplifier, a control signal C1 for connection between the bit line of the main cell block and the first input / output node of the sense amplifier, a control signal C2 for connection between the bit line of the reference cell block and the second input / output node of the sense amplifier, a control signal C3 for controlling the low voltage precharge for the bit line of the main cell, the bit line of the reference cell and the sense amplifier node, a control signal C4 for controlling the starting point of the gap selection activation and pulling up the bit line of the reference cell.

Operation of the global control pulse generator for control pulse generation is explained as follows.

Fig. 19A is an operational flowchart for the global control pulse generator when the address Y is switched back and forth, and Fig. 19B is a corresponding diagram when the address X, Z is switched back and forth.

The chip enable signal CSBpad is from the outside via a Chip release pin is supplied, and it is replaced by an over activated from high to low state. It is an inactive interval on the high state is required to perform a new read or write.

In Fig. 19A, the entire period is divided into 15 intervals from t1 to t15.

The CSBpad signal is low from the interval t1 active until the end of interval t14, and it learns at Starting point of the interval t15 a transition to the high one  State whereupon it is inactive. While the signal CSBpad addresses X and Z do not change, but it does moves address Y to the start point of interval t7 and to Starting point of the interval t11 a transition. Y-ATD generated high in intervals t7 and t8 as well as t11 and t12 Impulse by detecting the change in address Y. The Signa le S1 and S2 are used for the basic waveforms to generate for the word lines SWL1 and SWL2 of the SWL cells gene.

First, the signal CSBpad is thereby in the interval t1 enabled it to go from high to low goes. The addresses X, Y and Z keep their states before the interval t1. After the address Y to the starting point of the interval t7 has undergone a transition, that keeps Signal Y-ATD at high intervals t7 and t8 was standing. After address Y to the start point of the interval t11 has undergone a transition, the signal Y-ATD keeps in the intervals t11 and t12 its high state.

When the interval t1 has passed and the interval t2 begins, the signals S1 and S2 go high about. The signal S1 holds the high and in the interval t3 Interval t4 the low state. The signal S2 stops the intervals t3 and t4 the high state.

The basic signal C1, which is used to control the signal flow between the main cell bit line and an input control of the sense amplifier is only in the Interval t3 on the low state. Hence the Sig Flow between the main cell bit line and one Input connection of the sense amplifier in the interval t3 below broken.

The basic signal C2, which is the signal flow between the reference cell bit line  and the other input port of the read amplifier controls, is in the intervals t3 to t14 in the low state. Therefore the signal flow is between the main cell bit line and the other input terminal of the sense amplifier in the intervals from t3 to t14 below broken.

The basic signal C3, which is the signal flow between the main cell bit line and the external data bus controls and au also controls the pulling up of the reference bit line a transition from low to the start of interval t4 towards the high state and it experiences at the starting point which the CSBpad signal is deactivated (end of the interval t4) another transition from high to low Zu was standing. Therefore, controlling the signal flow between the Main cell bit line and the external data bus and a Controlling the pull-up of the reference bit line only in the In intervals from t4 to t14 possible.

The signal P2, which serves to prevent the Signa le S1 and S2 in the interval in which these signals normal Im pulse, be disturbed, goes to the starting point of the Inter valls t2, to which the signals S1 and S2 are high State, go to the high state and it goes at the start point of the interval t6 to the low state about.

The signal C3, which is used to pre-charge the low voltage of the Bit lines of the main and reference cells serve before the Signals S1 and S2 become active, keeps its high state in Interval t1, it goes to the starting point of interval t2 over the low state, and it's going to, at the time which the signal CSBpad is deactivated, to the high close stood over.  

The signal SAN (a preparatory signal that is to be generated a signal SAN_C for controlling NMOS transistors for Operating the sense amplifier the sense amplifier input / Output control is used) keeps its previous low state at the end point of the interval t2 goes to the start point of the interval t3 to the high state and goes at the time when the CSBpad signal is deactivated, over to the low state.

The signal SAP (a preparation signal that is used to generate a signal SAP_C for controlling PMOS transistors for Operating the sense amplifier the sense amplifier input / Output control is used) changes with counter polarity to the SAN signal. That is, the signal SAP its previous high state at the end point of the interval t2 holds low at the starting point of interval t3 State goes and at the time the signal CSBpad is deactivated, goes to the high state.

The waveforms for the input / output operation of the global control pulse generator when the addresses X, Z change are very similar to the waveforms for the input / output operation when the address Y changes. The different part is that the X, Z-ATD signal is high when the X, Z addresses in FIG. 19B change while the Y-ATD signal is high, when the address Y changes in Fig. 19A. In the global control pulse generator, the (X, Z-ATD) signal and the CSBpad signal are combined when the addresses X, Z change. If intervals (t7 and t14) are high in the (X, Z-ATD) signal, the global control pulse generator determines that the CSBpad signal is high in that interval. Therefore, in the global control pulse generator, all output signals are generated again, and there is normal access to the corresponding addresses X, Z. The signal C1, which after a temporary transition to the low state, while both signals S1 and S2 are in an interval in are in their high state, returning to their previous state, go to the low state in the intervals t3, t10 and t17. The signal C2 changes from the high to the low state at the time when the signal C1 changes to the low state. The signal C4 goes low when the signal C2 goes high, and then goes high when signal C1 goes high. Signal P2 goes high when both signals S1 and S2 go high and when the second high state of signal S1 ends with the two high pulse intervals, goes low. The signal C3 goes to the low state at the time when the two signals S1 and S2 go high, and it goes high when the (X, Z-ATD) signal goes on passes the high state. The SAN and SAP signals each transition to their opposite states when the C2 signal changes. The local control pulse generator receives the pulse signal from the global control pulse generator and then controls the memory according to the invention.

Now the local control pulse generator at the Erfin explained in detail.

Figure 20 shows the block diagram of the local control pulse generator in the invention.

The signals S1, S2, P2, C1, C2, C3, C4, SAN and SAP, which are the input signals of the local control pulse generator, are the output signals of the global control pulse generator. The Y-ATD is an address transition detection signal generated at the time of address Y transition and forms a high pulse. The signal WEBpad is a write enable signal, and it shows the low state in its active state in the write mode. Z_Add1 to Z_Add4 are signals as generated by the Z address predecoder 14 . The local control pulse generator shown in FIG. 20 exemplifies the case where a signal for controlling the upper block in FIG. 8 is generated. The driver control pulse for the lower block is generated in the same way.

The local control pulse generator 20 includes a first control pulse generator 200 for generating an input signal of a sense amplifier input / output controller 25 , a second control pulse generator 201 for generating an input signal of the column controller 24 , and a third control pulse generator 202 for generating an input signal of the SWL driver 22 ,

The first control pulse generator 200 includes a first logic operation unit 203 which receives the signals SAP, SAN, Z_Add3, Z_Add4 and the third control signal C3 and generates control pulses SAP_C, SAN_C, C3N_C and C3P_C to control the upper and lower blocks, and a second Logic operation unit 204 , which receives the first and second control signals C1 and C2 and the signals Z_Add1 and Z_Add2 and generates control pulses C1P_T, C1N_T, C2P_T, C2N_T and C3N_T for controlling the upper block.

Now the structure of the local control pulse generator explained in more detail.

The first control pulse generator 200 includes a first NAND gate 203-1 for performing a logic operation on the Z_Add3 and Z_Add4 signals and for generating an output signal related to the generation of the control signal to be applied to the upper block; a second NAND gate 203-2 for performing a logic operation on the output of the first NAND gate 203-1 and on the output of the NAND operation for the signals Z_Add1 and Z_Add2; a third NAND gate 203-3 for performing an operation on the input signal SAP and on the output signal of the second NAND gate 203-2 ; a first inverter 203-4 for generating a signal SAP_C by inverting the output of the third NAND gate 203-3 ; a fourth NAND gate 203-5 for performing a logic operation on the input signal SAN and on the output signal of the second NAND gate 203-2 ; a second inverter 203-6 for generating a signal SAN_C by inverting the output signal of the fourth NAND gate 203-5 ; a fifth NAND gate 203-8 for performing a logic operation on a third control signal C3 inverted by a third inverter 203-7 and on the output of the second NAND gate 203-2 ; a fourth inverter 203-9 for generating a signal C3P_C by inverting the output signal of the fifth NAND gate 203-8 and a fifth inverter 203-10 for generating a signal C3N_C by inverting the output signal of the fourth inverter 203-9 .

The second logic operation unit 204 of the first control pulse generator 200 includes a first NAND gate 204-1 for performing a logic operation on the signals Z_Add1 and Z_Add2 and for generating an output signal relating to the generation of the control signal to be applied to the upper block; a first inverter 204-2 for inverting the output of the first NAND gate 204-1 ; a second NAND gate 204-3 for performing a NAND operation on the output of the first inverter 204-2 and the first control signal C1; second and third inverters 204-4 and 204-5 for amplifying the output signal of the second NAND gate 203-4 and for generating a signal C1P_T; a fourth inverter 204-6 for inverting the output of the second NAND gate 204-3 and generating a signal C1N_T; a third NAND gate 204-7 for performing a logic operation on the output signal of the first inverter 204-2 and on the second control signal C2, a fifth and a sixth inverter 204-8 and 204-9 for amplifying the output signal of the third NAND gate 204 -7 and for generating a signal C2P_T; a seventh inverter 204-70 for inverting the output signal of the third NAND gate 204-7 and for generating a signal C2N_T; a fourth NAND gate 204-11 for performing a logic operation on the output of the first inverter 204-2 and on the inverted output of the third control signal C3; and ninth and tenth inverters 204-12 and 204-13 for amplifying the output of the fourth NAND gate 204-11 and for generating a signal C3P_T.

The second control pulse generator 201 includes a first inverter 201-1 for inverting the signal WEBpad, a second inverter 201-2 for inverting the output signal of the first inverter 201-1 ; a third inverter 201-3 for inverting the fourth control signal C4; a NAND gate 201-4 for performing a logic operation on the outputs of the second and third inverters 201-2 and 201-3 ; a fourth inverter 201-5 for inverting the signal of the NAND gate 201-4 ; a NOR gate 201-6 for performing a logic operation on the third control signal C3, on the output of the fourth inverter 201-5 and on the output of the first NAND gate 204-1 of the second logic operation unit 204 in the first control pulse generator 200 ; a fifth inverter 201-7 for inverting the output of the NOR gate 201-6 and for generating a signal C4P_T; and a sixth inverter 201-8 for inverting the output signal of the fifth inverter 201-7 and for generating a signal C4N_T.

The third control pulse generator 202 includes a first inverter 202-1 for inverting the signal P2; a first NAND gate 202-2 for performing a logic operation on the signal Y-ATD, on the output signal of the first inverter 202-1 on the fourth control signal C4 and on the inverted signal of the signal WEBpad; a second inverter 202-3 for inverting the output of the first NAND gate 202-2 ; a delay unit composed of third to sixth inverters 202-4 to 202-7 for delaying the output of the second inverter 202-3 ; a first NOR gate 202-86 for performing a logic operation on the signal S1 and on the output signal of the second inverter 202-3 ; a second NOR gate 202-9 for performing a NOR operation on the output of the first NOR gate 202-8 and on the output of the first NAND gate 204-1 of the second logic operation unit 204 ; a seventh inverter 202-10 for inverting the output signal of the second NOR gate 202-9 and for generating a signal PS1_T; a third NOR gate 202-11 for performing a NOR operation on the second control signal S2 and on the output signal of the sixth inverter 202-7 ; a fourth NOR gate 202-12 for performing a NOR operation on the output of the third NOR gate 202-11 and on the output of the first NAND gate 204-1 of the second logic operation unit 204 ; and an eighth inverter 202-13 for inverting the output signal of the fourth NOR gate 202-12 and for generating a signal PS2_T.

The local control pulse generator in the invention is a control pulse generating block by which the first logic operation unit 209 of the first control pulse generator 200 can be shared for the upper and lower blocks, the second and third control pulse generators 201 and 202, and the second logic operation unit 204 of the first control pulse generator 200 which are blocks for generating the control pulse for the upper block.

The control pulse generation process by the local controller pulse generator in the invention is explained as follows.

First, the output signal of the second inverter 202-2 of the second control pulse generator 201 is in the low state, since the signal WEBpad is in the low state in the write mode. Therefore, the first NAND gate 201-4 becomes inactive, and the output signal of the gate is at the high state, so that the NOR operation unit 201-6 becomes active.

When the NOR gate 201-6 is active, the third control signal C3 passes through the fifth inverter 201-7 and becomes the signal C4P_T. This signal C4P_T passes through the sixth inverter 201-8 and becomes the signal C4N_T. The third control signal C3 deactivates all column selection signals in the state before the divided word lines SWL1 and SWl2 become active, that is to say in the precharge interval for the memory cells bit lines and the reference cell bit line. The signal flow between the data bus and the data line is interrupted by the deactivated column selection signal. Therefore, when the bit line is preloaded in write mode, a collision between a data value on the bit line and a data value on the input / output bus can be avoided.

Furthermore, the NAND gate 202-2 of the third control pulse generator 202 is active because the signal WEBpad is low and the output signal of the first inverter 201-1 of the second control pulse generator 201 is in the write mode in the high state. Thus, the NAND gate 202-2 of the third control pulse generator 202 is controlled by the signals Y-ATD, P2 and P4. In other words, when the signal P2 is high and the signals S1 and S2 are normally active, the NAND gate 202-2 of the third control pulse generator 202 becomes inactive, and the signals S1 and S2 are surely found in normal operation.

When the normal operation of the signals S1 and S2 is completed, the signal P2 changes to the low state and the output signal of the first inverter 202-1 of the third control pulse generator 202 is in the high state. As a result, the NAND gate 202-2 of the third control pulse generator 202 becomes active. In this state, the operation of the NAND gate 202-2 of the third control pulse generator 202 is determined in accordance with the condition of the Y-ATD signal or the C4 signal.

When the signal C4 goes high under the condition that the output signal of the first inverter 202-1 of the second control pulse generator 201 is high, the NAND gate 202-2 of the third control pulse generator 202 goes to the active state State over and the Y-ATD signal is transmitted to the SWL driver block 70 .

In other words, the signals S1 and S2 make the first and third NOR gates 202-8 and 202-11 of the third control pulse generator 202 active in the interval in which the address Y undergoes a transition. Then passes through the Y-ATD signal, the NAND gate 202-3 and the second inverter 202-3 of the third control pulse generator 202, and it is gen to the first NOR gate 202-8 of the first control pulse generator 202 übertra. At the same time delay to the third sixth inverter 202-4 to 202-7 the output signal of the second inverter 202-3 , and the delayed signal is given to the third NOR gate 202-11 .

The Y-ATD signal, which passes through the first and second NOR gates 202-8 and 202-9 and the seventh inverter 202-10 in turn , becomes the low signal PS1_T. The signal Y-ATD, which passes through the third and fourth NOR gates 202-11 and 202-12 and the eighth inverter 202-13 in turn , becomes the signal PS2_T at a low state. The signals PS1_T and PS2_T therefore have inverted polarity with respect to the signal Y-ATD. By setting the number of inverters used to delay the output of the second inverter 202-3 of the third control pulse generator 202 , using the four inverters 202-4 to 202-7 in this example, the overlap time becomes between the two signals PS1_T and PS2_T.

In the read mode, the NAND gate 201-4 of the second control pulse generator 201 becomes active. Then, the signal C4 passes through the third inverter 201-3 , the NAND gate 201-4 , the fourth inverter 201-5 , the NOR gate 201-6 and the fifth inverter 201-7 in turn , and it becomes the signal C4P_T. The sixth inverter 201-8 produced by inverting the output of the fifth inverter 201-7 a signal C4N_T. The signals C4N_T and C4P_T are used to transmit the signal amplified by the sense amplifier to a data bus.

In this read mode, the output signal of the first inverter 202-1 of the second control pulse generator 201 goes low and the NAND gate 202-2 of the third control pulse generator 202 becomes inactive. Then the transmission of the signals Y-ATD, P2 and C4 is prevented. When the output signal of the second inverter 202-3 of the third STEU erimpulsgenerators 202 goes to a low state, the first NOR gate 202-8 is the third Steuerimpulsge nerators 202 to Active. Have pulse generation in accordance with this operation, the Steuerim as input signals of the SWL driver block 70 to be used and signals PS1_T PS2_T reverse polarity with respect to the signals S1 and S2.

The explanation for the sense amplifier and its input / Output control circuit is as follows.

Fig. 21 shows a circuit for the sense amplifier and its ne input / output control according to the first embodiment of the invention, and Fig. 22 shows a corresponding circuit according to the second embodiment.

The structure of the circuit of the sense amplifier and its input / output control in Fig. 21 is as follows.

As shown in Fig. 7, since the core block 72 of the memory of the present invention is shared between the upper block 71 and the lower block 72 , the bit line BIT_T connected to the upper main memory cell, the bit line RBIT_T connected to the upper reference cell, are bit line BIT_B connected to the lower main memory cell and bit line RBIT_B connected to the lower reference cell connected around the sense amplifier block 210 .

The structure includes a sense amplifier 210 connected to the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B and which detects and amplifies the data from these lines in accordance with the sense amplifier activation signals SAP_C and SAN_C as generated by the local control pulse generator; an equalization circuit 211 for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with the equalization signals C3N_C and C3P_C; a first and a second transmission gate 212 and 213 for selectively connecting the input and output lines of the sense amplifier 210 to the bit lines BIT_T and RBIT_T, which correspond to the connection signals C1P_T, C1N_T, C2P_T and C2N_T for the upper cell array with the upper main memory and Reference cells are connected; third and fourth transmission gates 214 and 215 for selectively connecting the input and output lines of the sense amplifier 210 to the bit lines BIT_B and RBIT_B, which are connected to the lower main memory and reference cells according to the connection signals C1P_B, C1N_B, C2P_B and C2N_B become; a fifth transmission gate 216 , which is connected to the bit line BIT_T between the first transmission gate 212 and the upper memory cell and controls the connection to the data bus D_BUS in accordance with the column selection signals Y_n_T and YB_n_T; a sixth transfer port 217 connected to the bit line BIT_B between the third transfer port 214 and the lower memory cell and controlling the connection to the data bus D_BUS in accordance with the column select signals Y_n_B and YB_n_B; a first bit line level controller 218 , one electrode of which is connected to the bit line BIT_T between the first transmission port 212 and the fifth transmission port 216 , the other electrode of which is connected to the power supply terminal, and the gate of which is supplied with the pull-down control signal C3N_T by which Control the level of the bit line BIT_T; and a second bit line level controller 219 , one electrode of which is connected to the bit line BIT_T between the third transfer gate 214 and the lower memory cell array block, and the other electrode of which is connected to the power supply terminal and the gate of which is supplied with the pull-down control signal C3N_B by which To control the level of the bit line BIT_B.

The data bus D_BUS is common for the operations used in both read and write modes. Different said, the data bus D_BUS is in read mode as an output transmission line  of the sense amplifier used while he in write mode as a transmission line for the in one Memory cell data value to be used is used.

The following are the data input / output control circuit and the sense amplifier control signals and the associated block structures explained.

The signal SAN_C is applied to the gate of an NMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to the ground connection VSS. The high state of the SAN_C signal activates the sense amplifier 210 , while its low state makes the sense amplifier 210 inactive.

The signal SAP_C is applied to the gate of a PMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to the ground connection VCC. The low state of the SAP_C signal activates the sense amplifier 210 , while its high state makes it inactive. The equalization signals C3N_C and C3P_C applied to the equalization circuit 210 equalize the potentials of the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B of the main and reference cells and the potential of the sense amplifier 210 before the divided word lines SWL1 and SWL2 are active.

The pull-down control signal C3N_T performs the pull-down operation by turning on the first bit line level controller 218 when the upper main cell column and the reference cell column are selected, and it ensures low levels of the bit lines BIT_T and RBIT_T that are associated with the upper main memory and reference cells are connected.

The pulldown control signal C3N_B performs a pulldown operation by turning on the second bit line level controller 219 when the lower main cell column and the reference cell column are selected, and it displaces the bit lines BIT_B and RBIT_B connected to the lower main memory and reference cells are at the low level.

The circuit in Fig. 22 is an example of the sense amplifier and its input / output control according to the second embodiment of the invention, each NMOS transistor of the circuit block of this circuit being controlled by the associated control pulse.

The circuit according to the second embodiment of the invention includes a sense amplifier 220 which is connected to the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B and which detects and amplifies the data from the lines in accordance with the sense amplifier activation signals SAP_C and SAN_C generated by the local control pulse generator ; an equalization circuit 221 for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with the equalization signals C3N_C and C3P_C, a first and a second NMOS transistor 222 and 223 for selectively connecting the input and output lines of the sense amplifier 220 to the Bit lines BIT_T and RBIT_T, as connected to the upper main memory and reference cells, corresponding to the upper cell array connection signals C1N_T and C2N_T, which are generated by the local control pulse generator; third and fourth NMOS transistors 224 and 225 for selectively connecting the input and output lines of sense amplifier 220 to bit lines BIT_B and RBIT_B connected to lower main memory and reference cells in accordance with lower cell array connection signals C1N_B and C2N_B; a fifth NMOS transistor 226 , which is connected to the bit line BIT_T between the first NMOS transistor 222 and the upper memory cell and controls the connection to the data bus D_BUS in accordance with the column selection signal Y_n_T; a sixth NMOS transistor 227 connected to the bit line BIT_T between the third NMOS transistor 224 and the lower memory cell and controlling connection to the data bus D_BUS according to the column selection signals Y_n_B; a first bit line level controller 228 having one electrode connected to the bit line BIT_T between the first NMOS transistor 222 and the fifth NMOS transistor 226 and having its gate supplied with the pull-down control signal C3N_T to control the level of the bit line BIT_T; and a second bit line level controller 229 having an electrode connected to the bit line BIT_B between the third NMOS transistor 224 and the lower memory cell array block and having its gate supplied with the pull down control signal C3N_B to control the level of the bit line BIT_B ,

Now the structure of the column control of the fiction moderate memory explained.

Fig. 23 shows this structure.

Fig. 23 is an example of the control block of the upper memory cell array. This column control block receives the address signals from the Y predecoder and the control signals from the local control pulse generator, and generates the column select signal for selecting a cell when performing data input / output operations.

The column controller includes a plurality of NAND gates 230 to 233 for performing logic operations on the signal C4N_T from the local control pulse generator and each of the addresses Ypre_n, Ypre_n + 1, Ypre_n + 2, + 3 Ypre_n. , ., as predecoded by the Y predecoder 18 , and a plurality of inverters 234 to 237 , each of which is connected to the output terminals of these NAND gates.

The output signals of the NAND gates 230 to 233 which pass through the inverters 234 to 237 form the Y addresses Y_n_T, Y_n + 1_T, Y_n + 2_T, Y_n + 3_T,. , ,

The output signals of the NAND gates that are not the inverter pass through, the reference / Y addresses form YB_n_T, YB_n + 1_T, YB_n + 2_T, YB_n + 3_T,. , , If column control is active, is one of the Y addresses Y_n_T, Y_n + 1_T, Y_n + 2_T, Y_n + 3_T, , , , active in the high state, and one of the / Y addresses YB_n_T, YB_n + 1_T, YB_n + 2_T, YB_n + 3_T,. , , goes to the low Zu stood over. These active signals control activation or disabling the switch block that comes from transmission gates or transistors that are connected to the data bus in Le amplifier and its input / output circuit verbun they are.

The reference bit line level control circuit 76 in the present invention will now be explained.

Fig. 24 shows the structure of the reference bit line level control circuit according to the first embodiment of the invention, while Fig. 25 shows the corresponding second embodiment.

The reference bit line level control circuit 76 of FIG. 24 constitutes a circuit for performing pull-up of the reference cell column. The upper reference bit line level control circuit consists of a first PMOS transistor 240 whose sen gate is supplied with the reference bit line level control signal C4P_T from the local control pulse generator, the source electrode of which is connected to VCC and the drain electrode of which is connected to the reference line RBIT_T; and a first NMOS transistor 241 , whose drain electrode is connected to the reference bit line RBIT_T, whose source electrode is connected to VSS and whose gate is supplied with the reference bit line level control signal C3N_T, and it generates the pull-up or pull-down signal for controlling the level the reference bit line RBIT_T connected to the upper reference cell.

The lower reference bit line level control circuit consists of a second PMOS transistor 242 , the gate of which is supplied with the reference bit line level control signal C4P_B from the local control pulse generator, the source electrode of which is connected to VCC and the drain electrode of which is connected to the reference bit line RBIT_T, and a second NMOS Transistor 243 , whose drain electrode is connected to the reference bit line device RIBT_T, whose source electrode is connected to VSS and whose gate is supplied with the reference bit line level control signal C3N_B, and generates the pull-up or pull-down signal for controlling the level of the one connected to the lower reference cell Reference bit line RBIT_B.

In this reference bit line level control circuit, the pull-up operation according to which the reference bit line RBIT_T goes high is achieved when the signal C4P_P makes the first PMOS transistor 240 active. Thus, when the reference bit line is pulled up to a high voltage, a high state data is stored in the upper reference cell. When the second PMOS transistor 242 is activated by the signal C4P_T, the reference bit line RBIT_B is pulled up to a high voltage. Thus, when the reference bit line is pulled up to a high voltage, a high state data value is stored in the lower reference cell. When the first NMOS transistor 241 is activated by the C3N_T high state signal, the reference bit line RBIT_T is pulled down to low voltage. When the second NMOS transistor 243 is activated by signal C3N_B high, the reference bit line RBIT_T is pulled down to a low voltage.

Fig. 25 shows a second embodiment of the reference bit line level control circuit in the invention, which is constructed as follows.

The upper reference bit line level control circuit consists of a first NMOS transistor 270 , the gate of which is supplied with the reference bit line level control signal C4N_T from the local control pulse generator, the source electrode of which is connected to VCC and the drain electrode of which is connected to the reference bit line RBIT_B, and a second NMOS Transistor 271 , whose drain electrode is connected to the reference bit line RBIT_T, whose source electrode is connected to VSS and whose gate is supplied with the reference bit line level control signal C3N_T, and generates the pull-up or pull-down signal for controlling the level of the one with the upper reference cell connected reference bit line RBIT_B.

The lower reference bit line level control circuit consists of a third NMOS transistor 272 , the gate of which is supplied with the reference bit line level control signal C4N_B from the local control pulse generator, the source electrode of which is connected to VCC and the drain electrode of which is connected to the reference bit line RBIT_B, and a fourth NMOS transistor Transistor 273 , whose drain electrode is connected to the reference bit line RBIT_T, whose source electrode is connected to VSS, and whose gate is supplied with the reference bit line level control signal C3N_B, and generates the pull-up or pull-down signal for controlling the level of the connected to the other reference cell Reference bit line RBIT_B.

Fig. 26 shows the structure of the reference bit line level control circuit according to the third embodiment of the invention, and Fig. 27 shows the structure of the corresponding circuit according to the fourth embodiment.

First, the structure of the reference bit line level Control circuit according to the third embodiment as described below.

This structure includes a sense amplifier 260 connected to the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B, which detects and amplifies data from the bit lines in accordance with the sense amplifier activation signals SAP_C and SAN_C generated by the local control pulse generator; an equalization circuit 261 for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with the equalization signals C3N_C and C3P_C, a first and a second transmission gate 262 and 263 for selectively connecting the input and output lines of the sense amplifier 260 with the bit lines BIT_T and RBIT_T, which are connected to the upper main memory and reference cells, corresponding to the connection signals C1P_T, C1N_T, C2P_T and C2N_T for the upper cell array, a third and a fourth transmission gate 264 and 265 for selectively connecting the input and output lines of the sense amplifier 260 with the bit lines BIT_B and RBIT_B connected to the lower main memory and reference cells, corresponding to the connection signals C1P_B, C1N_B, C2P_B and C2N_B for the lower cell array; a fifth transmission port 266 connected to the input and output lines of sense amplifier 260 and controlling connection to data bus D in accordance with column select signals Y_n and YB_n; a sixth transmission port 276 connected to the input and output lines of sense amplifier 260 and controlling connection to the data bus DB in accordance with column select signals Y_n and YB_n; a first bit line level control circuit 268 connected between the first transfer gate 262 and the bit line BIT_T of the upper memory cell and controls the level of the bit line BIT_T in accordance with the pull up or pull down control signal C3N_T applied to its gate; and a second bit line level control circuit 269 whose one electrode is connected to the bit line BIT_B between the third transfer gate 264 and the lower memory cell array block and whose gate is supplied with the pull-down control signal C3N_B to control the level of the bit line BIT_B.

The signal SAN_C is applied to the gate of an NMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to the ground connection VSS. The high state of the SAN_C signal activates the sense amplifier 260 and its low state deactivates the sense amplifier 260 .

The signal SAP_C is applied to the gate of a PMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to the ground connection VCC. The low state of the signal SAP_C activates the sense amplifier 260 and its high state de activates the sense amplifier 260 .

The voltage applied to the equalization circuit 261 Ausgleichssig dimensional C3N_C and C3P_C same the potentials of Bitleitun gen BIT_T, RBIT_T, bit_B and RBIT_B the main and reference cells and the potential of the sense amplifier 260 from before the split wordlines SWL1 and SWL2 are active.

The pulldown control signal C3N_T performs the pulldown operation by turning on the first bit line level control circuit 268 when the upper main cell column and the reference cell column are selected, and sets the bit lines BIT_T and RBIT_T connected to the upper main memory and reference cells to the low level.

The pulldown control signal C3N_B performs the pulldown operation by turning on the second bit line level control circuit 269 when the lower main cell column and the reference cell column are selected, and sets the bit lines BIT_B and RBIT_B connected to the upper main memory and reference cells to the low level.

The structure of the reference bit line level control circuit according to the fourth embodiment of the invention the following.

This structure includes a sense amplifier 270 which is connected to the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B and which detects and amplifies the data from the lines in accordance with the sense amplifier activation signals SAP_C and SAN_C generated by the local control pulse generator; an equalization circuit 271 for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with the equalization signals C3N_C and C3P_C; first and second NMOS transistors 272 and 273 for selectively connecting the input and output lines of the sense amplifier 270 to the bit lines BIT_T and RBIT_T connected to the upper main memory and reference cells in accordance with the connection signals C1N_T generated by the global control pulse generator and C2N_T for the top cell array; third and fourth NMOS transistors 274 and 275 for selectively connecting the input and output lines of the sense amplifier 270 to the bit lines BIT_B and RBIT_B connected to the lower main memory and reference cells in accordance with the connection signals C1N_B and C2N_B for the lower cell lenarray; a fifth NMOS transistor 276 , which is connected to the input and output lines of the sense amplifier 270 and controls connection to the data bus D in accordance with the column selection signal Y_n; a sixth NMOS transistor 277 which is connected to the input and output lines of the sense amplifier 270 and controls the connection to the / data bus DB in accordance with the column selection signal Y_n; a first bit line level control circuit 278 having one electrode connected to the bit line BIT_T between the first NMOS transistor 272 and the memory cell block and having its gate supplied with the pull-down control signal C3N_T to control the level of the bit line BIT_T; and a second bit line level control circuit 279 whose one electrode is connected to the bit line BIT_B between the third NMOS transistor 274 and the lower memory cell array block and whose gate is supplied with the pull-down control signal C3N_B to control the level of the bit line BIT_B.

The data input / output operation of the invention Memory with the driver control circuit described above is explained as follows.

Fig. 28 shows the waveforms for operating the local control pulse generator in the write mode when the address Y changes.

For the present ferroelectric SWL memory, the Driver control of the upper memory cell block explained since the core block with the sense amplifier and its input /  Output control circuit from the adjacent above ren and lower memory cells is shared.

First, the period of the waveform in Fig. 28 is divided into 15 intervals from t1 to t15 from the time when the chip enable signal CSBpad is activated to its low state until the time when it is deactivated again to its high state ,

In the interval t1, the interval CSBpad is in its low activated state, and the signal WEBpad is in its low state activated. The addresses X, Y, Z their previous states, and the signals PS1_T, PS2_T, C1N_T, C2N_T, C4N_T, C3N_C, SAP_C and SAN_C from the Glo Ball control pulse generators also keep their states de from before the interval t1 at.

The signal PS1_T is then high in t1 State, in t2 and t3 on the low state, in t4 on the high state, in t5 on the low state, in t6 on the high state, in t7 and t8 on the low close stood high in t9 and t10, in t11 and t12 on the low state and after the starting point of t13 on the high condition.

The signal PS2_T is in the high state in t1, in t2 to t4 on the low state, in t5 to t7 on the high state, in t8 and t9 on the low state, in t10 and t11 on the high state, in t12 and t13 on the low state and after the starting point of the interval t14 on the high condition.

The signals SWL1 and SWL2 are located in the interval t1 the low state, and they go to the starting point of the Intervals t2 to the high state. Here the signal shows  SWL1 opposite polarity to that of the signal PS1_T, but the same transition times as the last one re. The signal SWL2 shows opposite polarity to Signal PS2_T, but the same transition times as that latter.

The waveforms of the C1N_T and C3N_T signals that the On gangs- and output lines of the sense amplifier and the Bit lines of the memory cell and reference cell blocks electrically connect are explained as follows.

The signal C1N_T keeps in all intervals with one exception of the interval t3 which forms part of the intervals in which the signals SWL1 and SWL2 are high, before Y-Add is switched back and forth, its high Zu stood by.

The signal C2N_T goes to the starting point of the interval t2 which the signal C1N_T changes to the low state, also in the low state, it keeps the low state, and then it goes to the time when the CSBpad signal goes high, too over in the high state.

The signal C4N_t goes to the start point of the interval t2 which the signals SWL1 and SWL2 transferred to the high state hen, also on the high state, and it works the low state when the CSBpad signal is deactivated fourth.

The signal P2 stops at the interval t2 at which the signals Switch SWL1 and SWL2 to the high state until the In tervall t5 the high state, and it is with Exception of these intervals in the low state.  

The signal C3N_T maintains its previous high state until At the end of the interval t1, goes to the start point of the Inter valls t2, to which the signals SWL1 and SWL2 go to high got over to the low state and it goes then to the high state when the CSBpad signal is deactivated fourth. Therefore the signal C3N_T has opposite Po larity to the signal C4N_T.

The signal SAN_C goes at the beginning of the interval t2 at which the Signals SWL1 and SWL2 change to the high state, just if over to the high state and it keeps the high State until the signal CSBpad de is activated.

The signals SAP_C and SAN_C have opposite to each other te polarity, but they show transitions at the same time points.

In this memory, which is described with the waveforms described above, when the signal Y-ATD is generated by changing the address Y and is in the write mode, the signals PS1_T and PS2_T are generated by the local control pulse generator and the signals SWL1 and SWL2 are generated by the SWL driver block 70 .

In the intervals t2, t3, t8 and t12, in which the Signals SWL1 and SWL2 are high the logical value 0 is written into the SWL memory cell. In the intervals t4, t5, t7, t11 and t13, in which one of the signals SWL1 and SWL2 is high, the logical value 1 is inserted into the SWL memory cell wrote.

Now the operation of the memory according to the invention in Le semodus explained.  

Fig. 29 shows waveforms for the operation of the pulse generator Lokalsteue approximately in the read mode, when Y address is changed.

The signal WEBpad is deactivated in the reading mode in the high state fourth. Furthermore, the Y-ATD signal goes high only when the address Y changes, i.e. in the same way as in Write mode. In other words, the address keeps Y if it at the beginning of the interval t7 undergoes a transition that ho hen state for the two intervals t7 and t8 at, and if the address Y makes a transition at the beginning of the interval t11 experienced, Y-ATD retains its value for the intervals t11 to t13 high condition. Except for these intervals Y-ATD at its low state.

The signal PS1_T holds the at intervals t2, t3 and t5 low state, and in the remaining intervals it keeps the high condition. The signal PS2_T stops in the intervals t2 to t4 the low state and in the other interval len it keeps the high state.

The signals SWL1 and PS1_T each experience at the same time point a transition of their states, however, are their pola different from each other. The same applies to the SWL2 and PS2_T signals.

The waveforms of the signals C1N_T and C2N_T, the one electrical connection between the input and output lines of the sense amplifier, the bit lines of the memory cherzellenblocks and the bit lines of the reference cell block manufacture are the following. The signal C1N_T stops in al len intervals with the exception of the interval t3, which is part of the Intervals is in which the signals SWL1 and SWL2 in the high state before Y-Add switched back and forth  will, in high condition. The signal C2N_T goes at the time at which the signal C2N_T changes to the low state, also to the low state, it keeps the low condition, and then it goes to the time that the WEBpad signal goes high, also on the high state over.

The signal C4N_T goes at the time when the signal C1N_T passes to the high state, also to the high state stood over and it returns at the time the signal CSBpad is deactivated, return to the low state.

The signal P2 goes at the time when the signals SWL1 and SWL2 go to the high state, also to the high state over, it keeps that high state, and then it goes at the time when the signal SWL1 makes a transition learns before the signal Y-Add is switched back and forth, over to the low state.

The signal C3N_T maintains its previous high state until End of the interval t1, it goes to the starting point of the Inter valls t2, to which the signals SWL1 and SWL2 go to high got over, over to the low state, and then it goes to the high state when the signal CSBpad is deactivated.

The signal SAN_C goes to the beginning of the interval t2 high state while at the same time the signals C1N_T and C2N_T experience their transitions, and it holds this closed stood until the signal CSBpad deactivated fourth.

The signals SAP_C and SAN_C point towards each other set polarity, but with transitions at the same time Point. As described above, the output signal of the  Local control pulse generator no change since in its Input signal no change exists if the address Y on the condition that the Signal CSBpad is active in its low state.

Even if the signal Y-ATD changes the address Y changes to the high state, the deactivated Maintain states of the signals SWL1 and SWL2 that the signals PS1_T and PS2_T of the local control pulse generators can be kept unchanged in read mode.

Therefore, the by the sense amplifier are buffered transferred data to the data bus in that the that column decoder is activated, that of the changed Address Y corresponds.

First, in the interval t7, in which the address Y changes, the data value from the sense amplifier to the data bus transferred and a read operation is performed. Secondly in the interval t11, in which the address Y changes, the Data value transferred from the sense amplifier to the data bus, and a read operation is also carried out. This means, that the data value stored by the sense amplifier can be transferred to the data bus in that only the Column selection is changed when the address Y reciprocates is switched.

So the input and output operations of the Spei chers in read and write mode for the case that only the address Y changes.

These operations are explained below for the case that only the addresses X, Z change.

First, the waveform for the operation of the memory  in write mode when the addresses X, Z change, divided into 21 intervals from t1 to t21.

Fig. 30 shows the waveform for the toggling of the addresses X, Z, when the memory according to the invention is in the write mode.

First, the CSBpad signal goes at the beginning of the interval t1 from its high state to the low state, it considers this state as its active state, and then it is deactivated at the beginning of the interval t12. Gleichzei The write enable signal WEBpad goes low State about, it keeps that state as its active state stood, and it goes high when the Sig nal CSBpad is deactivated. The signals WEBpad and CSBpad are fed from the outside. If the addresses X, Z to the Starting points of the intervals t7 and t14 a transition to have the (X, Z-ATD) signal at intervals t7 and t14 the high condition.

Only the signals CSBpad and WEBpad ak are in the interval t1 tiv, while all other signals keep their previous states th.

The signals CSBpad and WEBpad hold theirs in the interval t2 active states, and the signals PS1_T, PS2_T and C3N_C ge from their previous high states to the low states stood over. The signals SWL1, SWL2 and C4N_T and P2 go from their previous low states to the high ones Condition about. If the signal C4N_T due to the transition from is activated from the low to the high state Data value transferred outside to the bit line of the memory cell and the bit line of the reference cell are loaded.

All these signals hold CSBpad, WEBpad,  PS1_T, PS2_T, SWL1, SWL2, C3N_T, C4N_T and P2 the states from the interval t2, the signal SAN_C experiences an over transition from its previous low to high state, and the SAP_C signal goes from high to low about. The signals PS1_T and PS2_T change repeatedly as follows between the high and the low state.

The signal PS1_T stops in the intervals t1, t4, t6 to t8, t11, t13 to t15, t18 and t20 its high state, and it maintains the low state in the other intervals. The Signal PS2_T stops at intervals t1, t5 to t8, t12 to t15 and t19 the high state, while in the other In tervallen keeps the low state. The signals SWL1 and PS1_T experience transitions simultaneously, the polarities are different from each other. The signals SWL2 and PS2_T er drive transitions at the same time, the polarities just if they are different from each other. The signal C1N_T takes in the intervals t3, t10 and t17, in which both Sig SWL1 and SWL2 are in the high state, the low ones Condition on. The signal C2N_T goes to at the time low state, at which the signal C1N_T to the goes low and it goes back to the point in time to the high state at which the (X, Z-ATD) signal is up passes the high state. The signal C4N_T is currently going point to the high state at which the signals SWL1 and SWL2 go high and it goes again at the time the (X, Z-ATD) signal goes high stood over, into the low state. The signal P2 goes high at the time the both signals SWL1 and SWL2 go high, and it goes again at the time the two signals SWL1 and SWL2 go low, too over to the low state. The polarities of the signals SAN_C and C2N_T are different from each other, while the The polarities of the signals SAP_C and C2N_T are the same.  

Operation is as follows for the different intervals explained.

The signals PS1_T and C1N_T experience one in the interval t4 Transition to high while the signal SWL1 from high to low.

In the interval t5, the signal PS1_T goes from high to low state and the signal SWL1 goes accordingly the result, from low to high. The Signal PS2_T goes in from its previous low state goes high and the signal SWL1 goes correspond Based on the result, from high to low.

At the beginning of the interval t6, the signal PS1_T goes low go high and the signal SWL1 goes according to the result, from high to low to stood over. The signal PS2_T goes from its previous close stood, d. H. the high state, the low state about.

The addresses X, Z change in the interval t7 the (X, Z-ATD) signal starting from its previous low State now generated as a high signal. Then the signal goes C2N_T from low to high over the signals C4N_T and SAN_C each go from high to low stood over, and the signals C3N_T and SAP_C go from hers previous low state to the high state about.

At the beginning of the interval t8 only the (X, Z-ATD) signal goes from its previous high state to the low state over while all other signals are from their previous state maintain the interval t7. From the beginning of the interval  t9 become the waveforms of the intervals from t2 to t8 repeated.

At the beginning of the interval t21, the signals CSBpad and go WEBpad over in the high state, and the write mode will disabled. Then the signal C4N_T goes from its previous one State goes low, the SAN_C signal goes from its high state to the low state, and the SAP_C signal goes from low to high about.

So when the addresses X, Z are in memory in the write change mode, the signal C4N_T activated at the time which the signals SWL1 and SWL2 are activated, and from the This point in time, data is transmitted to the bit line, be before the sense amplifier is activated.

The signal curves for the operation of the memory in the reading memory If the addresses X, Z change, are in intervals t1 to t21, and they are explained as follows.

Fig. 31 shows the waveforms corresponding to the case where the addresses X, Z are switched back and forth when the memory according to the invention is in the read mode. If the waveforms in the read mode are compared with the waveforms in the write mode, there is a change at the transition time of the signal C4N_T. Furthermore, the signal WEBpad is deactivated in its high state in read mode.

The signal C4N_T keeps the low in the intervals t1 to t3 current condition. The signal goes at the beginning of the interval t4 C4N_T from low to high and then will the data value amplified by the sense amplifier to the Bit line loaded. The signal C4N_T keeps its high closed stood up to the interval t6 and it goes to the beginning of the interval  t7 to the low state. After that it stops Signal C4N_T the low state up to interval t10, and it goes high at the beginning of the interval t11 stood over. As soon as the signal C4N_T from low to ho hen state passes, the sense amplifier ver strengthened data value on the data input / output line transfer.

The sense amplifier thus acquires the data in advance when the Memory is in read mode, and then a read is done executed by the fact that the data value from the sense amplifier according to the activated signal C4N_T on the data Input / output line is given.

A ferroelectric SWL memory according to the invention has the following effects:

• - First, the complexity of the layout is essential reduced because the cell array without cell plate line is trained.
• - Secondly, the elements are stable and an impairment Use of a dummy cell is avoided as the reference level is generated without using one.
• - Third, the voltage generated on the bit line have a constant value, whereby the company's own properties of the elements are improved since the number of Main memory cells that are accessed, the number of the reference cells that are accessed.
• Fourth, the operation of the sense amplifier is stabilized, and its operating speed is increased since the belas capacity at the input and output terminals of the Sense amplifier is selectively controlled.
• - Fifth, the process of accessing a memory cell done at high speed since it is possible because by accessing a memory cell that only the Sig nal CSBpad, only one change of addresses X, Z and only one  Change of address Y can be used.

Claims (64)

1. Non-volatile ferroelectric memory with:

• - At least two bit lines (B_n, B_n + 1) and at least one word line pair from a first and a second subdivided word line (SWL1_n, SWL2_n) which intersect with the bit lines (B_n, B_n + 1);
• - at least one unit cell, the
• a first transistor (T1), the gate of which is connected to the first divided word line (SWL1_n) of the word line pair,
• a first ferroelectric capacitor (C1), one electrode of which is connected to the second divided word line (SWL2_n) of the word line pair and the other is connected to one of the bit lines via the first transistor (T1),
• - A second transistor (T2), the gate of which is connected to the second divided word line (SWL2_n) of the word line pair, and
• - has a second ferroelectric capacitor (C2), one electrode of which is connected to the first divided word line (SWL1_n) of the word line pair and the other of which is connected to the other of the bit lines via the second transistor (T2);
• - a SWL word line driver ( 100 ) connected to the first and second divided word lines (SWL1_n, SWL2_n) and each applying a SWL drive signal;
• - a reference level generator ( 101 ) for generating a reference level;
• - A sense amplifier ( 102 a; 102 b), which is connected to each of the bit lines and carries out a comparison between the reference level and the voltage induced on each of the bit lines; and
• - A control circuit with a column decoder ( 103 a, 103 b), which transmits the output signals of the sense amplifier ( 102 a; 102 b) in accordance with an address signal (Y_N, Y_N + 1) to a data bus.

2. Memory according to claim 1, characterized in that the unit cell stores two data values, each word line pair stores a row address and each bit line (B_n, B_n + 1) forms a column. 3. Memory according to claim 1 with:

• - A plurality of transistors (T21-T24), which can be switched on by a first control signal (C1), to connect a connection between the bit lines (B_n, B_n + 1, B_n + 2,...) of a memory cell area and first input ( B1, B2, B3, B4,...) Of a sense amplifier array,
• - A plurality of second transistors (T25-T28) which can be switched on by a second control signal (C2) in order to establish a connection between a reference bit line (RB0) and other input nodes (R1, R2, R3, R4,...) of the Le to manufacture amplifier arrays,
• - A bit line level control circuit ( 140 ), which is controlled by a third control signal (C3), and
• - A pull-up transistor (PU0), which can be controlled by a fourth control signal (C4), so that a pull-up voltage can be applied to the reference bit line (RB0).

4. Memory according to claim 3, characterized in that the bit line level control ( 140 ) contains third transistors (T29-T40) which can be activated by the third control signal (C3) in order to the bit lines of the main storage cells and the reference cells to the same potential pull, the bit lines are pulled down to a ground potential when the third control signal (C3) is activated while the first and the second control signal (C1, C2) are active. 5. Memory according to claim 3 or 4, characterized in that then if the reference cell and the main memory cell have the same capacity and they store the same logic value 1, a bit line voltage increment, as generated by the main memory cell, on the bit line line side of the main memory cell larger than on the bit line side of the Be train cell is. 6. Memory according to claim 3, 4 or 5, characterized in that then when the reference cell stores the logic value 1 and the main memory cell stores the logical value 0 that generated by the reference cell Voltage increment on the bit line side of the reference cell is greater than is that through the main memory cell on the bit line side of the Main memory cell is induced. 7. Memory according to one of claims 3 to 6, characterized in that that the bit line voltage of the reference source is at an intermediate level  between a voltage on the bit line of a main memory cell from this corresponds to the logic stored in the main memory cell Value 1 is generated, and a voltage builds up on the bit line of the Main memory cell of this corresponds to that in the main memory cell stored logical value 1 is generated. 8. Memory according to one of the preceding claims, with:

• a plurality of main cell arrays ( 73 ), in which the main memory cells are arranged to form unit cells in an even number of columns,
• a plurality of reference cell arrays ( 74 ) in which the reference cells are arranged in two columns,
  wherein one of the reference cell arrays ( 74 ) is assigned to each of the main cell arrays ( 73 ) so that they each form a pair, forming a multiplicity of cell array blocks ( 71 ),
  wherein the SWL word line driver ( 70 ) is arranged parallel to the columns and a plurality of control blocks ( 72 ) including the sense amplifiers and column decoders are provided which are connected to the two ends of the columns.

9. Memory according to claim 8, characterized in that the control blocks ( 72 ) for each of the cell array blocks ( 71 ) are divided into two areas and are arranged symmetrically at the two ends of the cell array blocks in the column direction. 10. The memory according to claim 8 or 9, characterized in that the control blocks are formed as core blocks ( 72 ) which contain a plurality of bit line control circuit blocks ( 75 ) and a plurality of reference bit line control circuit blocks ( 76 ), each of the Bit line control circuit blocks ( 75 ) is connected to one of the bit lines (B_n, B_n + 1, B_n + 2,...) And to a reference bit line (RB_n, RB_n + 1, RB_n + 2,...) Of the corresponding reference cell array , and each reference bit line control circuit block ( 76 ) is connected to one of the corresponding reference bit lines. 11. Memory according to one of the preceding claims, characterized shows that there are so many memory cells in the memory cell array with each bit line  are connected like reference cells in the reference cell array to a reference bit line are connected so that the capacitive component (Cb_n) each of the Bit lines in the main memory cell area equal to the capacitive components te (Crb0) of the reference bit line, and that Cb1 = Cr1, Cb2 = Cr2, Cb3 = Cr3 and Cb4 = Cr4, where Cr1, Cr2,. , , as well as Cb1, Cb2,. , , other capacitive com designate components of other areas. 12. The memory according to claim 11, characterized in that the number n of the bit lines of the main cell array is determined to be the condition Crb0 = n.Cr1 is sufficient and concerns the capacitance of the entire bit lines fend the reference cell, approximately twice the capacity of the entire bit lines related to the main memory cell.   13. Memory according to one of the preceding claims, with:
an (X, Z-ATD) generator ( 15 ) for detecting an address transition in externally supplied signals for addresses X, Z and for generating an (X, Z-ATD) signal;
a global control pulse generator ( 16 ) for receiving an output signal of the (X, Z-ATD) generator, an externally supplied signal CSBpad (chip enable signal), for itself a voltage switch-on detection signal and a basic pulse for memory control in accordance with a combination of the (X, Z-ATD) signal, the CSBpad signal and the power-on detection signal;
a Y-ATD generator ( 19 ) for detecting an address transition of an externally supplied signal for an address Y;
a local control pulse generator ( 20 ) for generating a pulse required for each memory block by combining an output signal of the global control pulse generator, a precoded signal to the address Z and the output signal of the Y-ATD generator;
an X post-decoder ( 21 ) for combining predecoded signals for addresses X, Z and for selecting a corresponding memory cell block ( 23 );
a SWL driver ( 22 ) for applying a signal obtained by combining an output of the X post-decoder and an output of the local control pulse generator to each divided word line of each SWL cell block with a cell block composed of a plurality of main memory cell arrays including a unit cells formed at the intersections between first and second equally spaced bit lines and first and second divided word lines (SWL1, SWL2) which are repeatedly formed in the direction perpendicular thereto, and a plurality of therebetween arranged reference cell arrays be;
a column controller ( 24 ) for combining the predefined signal for the address Y and the output signal of the local control pulse generator and for selecting a corresponding bit line; and
a sense amplifier input / output controller ( 25 ) for combining the output of the local control pulse generator and an output of the column controller and for controlling sensing input / output (I / O) operations of each SWL cell block. 14. The memory of claim 13, characterized in that the local control pulse generator comprises:
a first logic operation unit ( 203 ) for receiving a control signal including preparation signals (SAP, SAN) for a sense amplifier and predecoded addresses Z (Z_Add3, Z_Add4) and for generating sense amplifier control signals (SAP_C, SAN_C) and control signals (C3N_C, C3P_C) for same tension;
a first control pulse generator ( 200 ) with a second logic operation unit ( 204 ) for generating control signals (C1P_T, C1N_T, C2P_T, C2N_T, C3N_T) for bit line connection and level control from predecoded signals (Z-Add1, Z_Add2) for the address Z;
a second control pulse generator ( 201 ) for receiving a signal including a write enable signal (WEBpad) in order to generate signals (C4P_T and C4N_T) for column selection therefrom; and
a third control pulse generator ( 202 ) for receiving a signal (Y-ATD) which indicates a transition of the address Y in order to generate preparatory SWL signals UPS1_T, PS2_T). 15. The memory of claim 14, characterized in that the first logic operation unit ( 203 ) receives a third control signal (C3), the bit lines of a main memory cell and a reference cell with a low voltage preloaded before a SWL drive signal is active, and a PMOS transistor of the sense amplifier control the signal (SAP_C), an NMOS transistor of the sense amplifier control signal (SAN_C), an NMOS transistor of the block for balancing bit line signals control signal (C3N_C) and a generates a PMOS transistor of the block controlling signal (C3P C). 16. The memory according to claim 14, characterized in that the second logic operation unit ( 204 ) a first control signal (C1) which controls the signal flow of the bit lines of a main memory cell and an input / output terminal of the sense amplifier, and a second control signal (C2) receives, which controls the signal flow of the bit lines of a reference cell and an input / output terminal of the Le amplifier. 17. The memory of claim 14, characterized in that the second control pulse generator ( 201 ) receives a third control signal (C3), the bit lines of a main memory cell and a reference cell with a low voltage in advance before a SWL drive signal is activated, and which then generates a signal (C4P_T) that controls a PMOS transistor of the block to control a column selection and a signal (C4N_T that controls an NMOS transistor of the block to control a column selection. 18. Memory according to claim 14, characterized in that the third control pulse generator ( 202 ) receives preparatory signals (S1, S2) to the preparatory SWL signals, a blocking signal (P2) for preventing interference with the normal operation of each of the preparatory signals and generate a fourth control signal (C4) to control the signal flow on the bit lines of the main memory and on an external data bus. 19. The memory of claim 14, characterized in that the local control pulse generator further comprises a circuit that the second logic operation unit ( 204 ) of the first control pulse generator ( 200 ) in the output stage of a NAND gate of the first logic operation unit ( 203 ) of the first control pulse generator performs predecoded signals (Z_Add3, Z_Add4) for the address Z, and has a circuit with the same structure as that of the second, third control pulse generator ( 201 , 202 ) and controls a detection process and input / output processes for another cell array block, which has the sense amplifier and the input / output circuit together. 20. The memory according to claim 19, characterized in that the local control pulse generator a first to fourth Control signal (C1 to C4) and a preparatory SWL signal receives and signals (C1P_B, C1N_B, C2P_B, C2N_B, C3N_B) for the bit line connection and level control, Control signals (C4P_B, C4N_B) for a column selection process and other preparatory SWL signals (PS1_B, PS2_B) are generated. 21. The memory according to claim 14, characterized in that the first logic operation unit ( 201 ) has the following:
a first NAND gate ( 203-1 ) for performing an operation on Z_Add3 and Z_Add4;
a second NAND gate ( 203-2 ) for performing an operation on the output of the first NAND gate and Z_Add1 and Z_Add2 which are processed by a NAND operation;
a first inverter ( 203-4 ) for generating a signal SAP_C by inverting the output of a third NAND gate ( 203-3 ) which performs a NAND operation on the output of the second NAND gate and an input signal SAP;
a second inverter ( 203-6 ) for generating a signal SAN_C by inverting the output of a fourth NAND gate ( 203-5 ) which performs a NAND operation on the output of the second NAND gate and a signal SAN;
a fifth NAND gate ( 203-8 ) for performing a NAND operation on the output of a third inverter ( 203-7 ) which inverts a third control signal C3 relating to the equalization and column selection and the output of the second NAND -Gatters;
a fourth inverter ( 203-9 ) for generating a signal C3P_C by inverting the output signal of the fifth NAND gate; and
a fifth inverter ( 203-10 ) for generating a signal C3N_C by inverting the output signal of the fourth inverter. 22. The memory according to claim 14, characterized in that the second logic operation unit ( 204 ) has the following:
a first NAND gate ( 204-1 ) for performing an operation on Z_Add1 and Z_Add2;
a second NAND gate ( 204-3 ) for performing a NAND operation on the output of a first inverter ( 204-2 ) which inverts the output of the first NAND gate and a first control signal (C1) which connects two cell array blocks to bit lines controls which share the sense amplifier and an input / output circuit;
a second and a third inverter ( 204-4 , 204-5 ) for generating a signal C1P_T by delaying the output signal of the second NAND gate;
a fourth inverter ( 204-6 ) for generating a signal C1N_T by inverting the output signal of the second NAND gate;
a third NAND gate ( 204-7 ) for performing a NAND operation on the output of the first inverter and a second control signal (C2) which controls bit line connections of two reference cell array blocks which share the sense amplifier and a data input / output circuit ;
a fifth and a sixth inverter ( 204-8 , 204-9 ) for generating a signal C2P_T by delaying the output signal of the third NAND gate;
a seventh inverter ( 204-10 ) for generating a signal C2N_T by inverting the output signal of the third NAND gate; and
a ninth and a tenth inverter ( 204-12 , 204-13 ) for generating a signal C3N_C by delaying the output signal of a fourth NAND gate ( 204-11 ), the signal of the first inverter and the inverted signal of a third control signal (C3) performs a logic operation. 23. The memory according to claim 14, characterized in that the second control pulse generator ( 201 ) has the following:
a first inverter ( 201-1 ) for inverting a write enable signal WEBpad;
a second inverter ( 201-2 ) for inverting the output signal of the first inverter;
a third inverter ( 201-3 ) for inverting a fourth control signal (C4) relating to SWL driving and column selection of two cell array blocks that share the sense amplifier and a data input / output circuit;
a fourth inverter ( 201-5 ) for inverting the output of a NAND gate ( 201-4 ) which performs a logic operation on signals of the second and third inverters;
a NOR operation unit ( 201-6 ) for performing a NOR operation on a third control signal (C3), the output signal of the fourth inverter and the output signal of the first NAND gate ( 204-1 ) of the second logic operation unit ( 204 );
a fifth inverter ( 201-7 ) for generating a signal C4P_T by inverting the output signal of the NOR operation unit; and
a sixth inverter ( 201-7 ) for generating a signal C4P_T by inverting the output signal of the fifth inverter. 24. The memory according to claim 14, characterized in that the third control pulse generator ( 202 ) has the following:
a first inverter ( 201-1 ) for inverting a signal (P2);
a first NAND gate ( 202-2 ) for performing a logic operation on a signal Y-ATD, the output signal of the first inverter, a fourth control signal (C4) and the inverted signal from the signal WEBpad;
third to sixth inverters ( 202-4 to 202-7 ) for delaying the output of a second inverter ( 202-3 ) which inverts the output of the first NAND gate;
a first NOR gate ( 202-8 ) for performing an operation on a signal S1 and the output signal of the second inverter;
a second NOR gate ( 202-9 ) for performing a NOR operation on the output of the first NOR gate and on the output of the first NAND gate ( 204-1 ), the second logic operation unit ( 204 );
a seventh inverter ( 202-10 ) for generating a signal PS1_T by inverting the output signal of the second NOR gate;
a third NOR gate ( 202-11 ) for performing a logic operation on a second control signal (S2) and the output signal of the sixth inverter;
a fourth NOR gate ( 202-12 ) for performing a NOR operation on the output of the third NOR gate and on the output of the first NAND gate of the second logic operation unit; and
an eighth inverter ( 202-13 ) for generating a signal PS2_T by inverting the output signal of the fourth NOR gate. 25. The memory according to claim 14, characterized in that signal Y-ATD indicating a transition of address Y. will hold when the address Y makes a transition of its to experiences, and that is active with a high pulse. 26. Memory according to claim 14, characterized in that signal Y-ATD indicating a transition of address Y. will hold when the address Y makes a transition of its to experiences, and that is active with a high pulse. 27. The memory according to claim 14, characterized in that the signal for column selection, corresponding to an inter vall for precharging the main memory cell bit line and the reference cell bit line, the states of which assume values, before the divided word lines (SWL1, SWL2) are active are in write mode by a third control signal (C3) is set to an inactivity level and from then on the Sig flow between a data bus and a bit line the control signal is interrupted.   28. The memory of claim 14, characterized in that a NAND gate ( 202-2 ) of the third control pulse generator ( 202 ) is activated so that normal operation of the signals S1 and S2 is ensured when a signal P2 is in the high state is and signals S1 and S2 are in their active states in normal operation. 29. The memory according to claim 14, characterized in that in the third control pulse generator ( 202 ) the size of the third to sixth inverter ( 202-4 to 202-7 ) for delaying the output signal of the second inverter ( 202-3 ) is set such that an overlap of the low states of the signals PS1_T and PS2_T is avoided. 30. Memory according to claim 14, characterized in that the output signals (PS1_T and PS2_T) of the third Steuerim pulse generator ( 202 ), which are used as input signals of a SWL-An control block, each have opposite polarities to the signals S1 and S2. 31. Memory according to one of the preceding claims, characterized in that a core block with a sense amplifier is shared by an upper cell array block and a lower cell array block, with:
a sense amplifier ( 210 ) which is connected to bit lines (BIT_T, RBIT_T, BIT_B and RBIT_B) which are connected to a reference cell and any memory cell in the upper cell array and in the lower cell array, and which correspond to sense amplifier activation signals (SAP_C and SAN_C) data on the lines recorded and amplified;
an equalization circuit ( 211 ) for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with equalization signals (C3N_C and C3P_C);
a first and a second transmission gate ( 212 , 213 ) which are switched by connection signals (C1P_T, C1N_T, C2P_T, C2N_T) for the upper cell array, in order then to selectively connect the bit lines BIT_T and RBIT_T to the input and output lines of the sense amplifier;
a third and a fourth transmission gate ( 214 , 215 ) which are switched by connection signals (C1P_B, C1N_B, C2P_B, C2N B) for the lower cell array, in order then to selectively connect the bit lines BIT_B and RBIT_B to the input and output lines of the sense amplifier ;
a fifth transmission port ( 216 ) connected to the bit line (BIT_T) between the first transmission port ( 212 ) and the upper memory cell and controlling connection to a data bus (D_BUS) in accordance with column selection signals (Y_n_T and YB_n_T); and
a sixth transmission gate ( 217 ), which is connected to the bit line (BIT_B) between the third transmission gate ( 214 ) and the lower memory cell and controls the connection to a data bus (D_BUS) in accordance with column selection signals (Y_n_B and YB_n_B). 32. Memory according to claim 31, characterized by:
a first bit line level controller ( 218 ), one electrode of which is connected to the bit line (BIT_T) between the first transmission port ( 212 ) and the fifth transmission port ( 216 ) and which controls the level of this bit line in accordance with a control signal (C3N_T) applied to a gate ; and
a second bit line level controller ( 219 ), one electrode of which is connected to the bit line (BIT_B) between the third transfer gate ( 214 ) and the upper memory cell array block and which corresponds to the level of this bit line corresponding to a pull-down control signal applied to a gate (C3N_B) controls. 33. The memory of claim 32, characterized in that when an upper main cell column and a reference cell column are selected, the first bit line level controller ( 218 ) is turned on, it pulls down and it performs the bit lines (BIT_T and RBIT_T) are connected to the upper main memory cell or the reference cell, brings it to a low level. 34. The memory of claim 32, characterized in that when a lower main cell column and a reference cell column are selected, the second bit line level controller ( 219 ) is turned on, it performs a pull-down operation, and the bit lines (BIT_B and RBIT_B) that connected to the lower main memory cell or the reference cell, brings it to a low level. 35. Memory according to claim 32, characterized in that the first and the second bit line level control ( 218 , 219 ) consist of an NMOS transistor, the other electrode of which is in each case connected to ground. 36. Memory according to claim 31, characterized in that the data bus (D_BUS) in read mode as output transmission line of the sense amplifier is used while it is in the Write mode as transmission line for a data value is used to write to a memory cell is. 37. Memory according to claim 31, characterized by a NMOS transistor, one electrode with the sense amplifier ker is connected and the other electrode with a mas port (VSS), with its gate connected to a Sense amplifier enable signal (SAN_C) is supplied, whose low state disables the sense amplifier. 38. Memory according to claim 31, characterized by a  PMOS transistor, one electrode with the sense amplifier ker is connected and the other electrode with a ver supply voltage connection (VCC) is connected Gate with a sense amplifier enable signal (SAP_C) ver is ensured, the low state of the sense amplifier ak tiviert and its high state deactivates the sense amplifier fourth. 39. Memory according to claim 31, characterized in that the equalization circuit ( 211 ) equalizes the potentials of the bit lines (BIT_T, RBIT_T, BIT_B and RBIT_B) of the main cell and the reference cell and the potential of the sense amplifier ( 210 ) before the divided word lines (SWL1 and SWL2) can be activated. 40. Memory according to claim 31, characterized in that the first to sixth transfer ports ( 212 to 217 ) form a switching block which consists of NMOS transistors. 41. Memory according to one of claims 1-30, characterized in that
a core block with a column decoder for column selection is shared between an upper cell array block and a lower cell array block, with:
a first number of NAND gates ( 230 to 233 ) which perform a logical operation on each of addresses with predecoded addresses (Ypre_n, Ypre_n + 1, Ypre_n + 2,...) and a column selection signal (C4N_T) generated by a local control pulse generator To run;
a second number of NAND gates which have inverters ( 234 to 237 ) connected to the output terminal of each of the NAND gates and form a block for column selection when a data input / output operation is carried out in an upper cell array block, and which perform a logic operation on each of the addresses and on said column select signal; and
a column selection block with inverters connected to the output terminal of each of the NAND gates and which forms a block for column selection when a data input / output operation is performed in a lower cell array block. 42. Memory according to claim 41, characterized in that the output signals of the NAND gates ( 230 to 233 ) become addresses Y (Y_n_T, Y_n + 1_T, Y_n + 2_T,...) For selecting a memory cell bit line when the output signals pass through each of the inverters ( 234 to 237 ) corresponding to the NAND gates, thereby becoming addresses / Y (YB_n_T, YB n + 1_T, YB_n + 2_T,...) which are used to select a reference cell bit line when the Output signals do not run through the inverters mentioned, only one signal of the addresses Y being activated in the high state and only one signal of the addresses / Y being activated in the low state. 43. Memory according to claim 42, characterized in that the enable signal the state (active or inactive) of a Controls switching blocks that consists of transistors or trans gung gates, which are connected to a data bus in a reading ver stronger and connected to an input / output circuit are. 44. Memory according to any one of claims 1-30, characterized in that

• a core block with a block for controlling the level of the reference bit line is shared by an upper cell array block and a lower cell array block, a block for controlling the level of a reference bit line having:
• - a first PMOS transistor ( 240 ) whose gate is supplied with a reference bit line level control signal (C4P_T), whose source is connected to VCC and whose drain electrode is connected to a reference bit line (RBIT_T);
• - an upper reference bit line level control circuit having a first NMOS transistor ( 241 ), the drain electrode of which is connected to the reference bit line, the source electrode of which is connected to VSS, and the gate of which is supplied with a reference bit line level control signal (C3P_T), and which goes up - or generates a pull-down signal for controlling the level of the bit line connected to an upper reference cell;
• - a second PMOS transistor ( 242 ) whose gate is supplied with a reference bit line level control signal (C4P_B), whose source is connected to VCC and whose drain is connected to a reference bit line (RBIT_B); and
• a lower reference bit line level control circuit with a second NMOS transistor ( 243 ), the drain of which is connected to the reference bit line, the source of which is connected to VSS and the gate of which is supplied with a reference bit line level control signal (C3N_B), and which or generates a pull down signal to control the level of the bit line connected to a lower reference cell.

45. The memory of claim 44, characterized in that when the signal C4P_T activates the first PMOS transistor ( 240 ), the reference bit line (RBIT_T) of an upper cell array block is pulled up to a high voltage and therefore high in an upper reference cell Data value is saved. 46. Memory according to claim 44, characterized in that when the signal C4P_B activates the second PMOS transistor ( 242 ), the reference bit line (RBIT_B) of a lower cell array block is pulled up to a high voltage and therefore a high data value in a lower reference cell is saved. 47. Memory according to claim 44, characterized in that when the C3N_T signal from high state activates the first NMOS transistor ( 241 ), the reference bit line (RBIT_T) is pulled down to a low voltage. 48. Memory according to claim 44, characterized in that the signal C3N_B from high state activates the second NMOS transistor ( 243 ) and therefore the reference bit line (RBIT_B) is pulled down to a low voltage. 49. Memory according to claim 44, characterized in that the upper reference bit line level control circuit comprises: a first NMOS transistor ( 270 ), the gate of which is supplied with a reference bit line level control signal (C4N_T), the source of which is connected to VCC and the latter Drain electrode is connected to a reference bit line (RBIT_T); and a second NMOS transistor ( 271 ) whose drain is connected to the reference bit line, whose source is connected to VSS and whose gate is supplied with a reference bit line level control signal (C3N_T), and the lower reference bit line level control circuit comprising: a third NMOS transistor ( 272 ) whose gate is supplied with a reference bit line level control signal (C4N_B), whose source is connected to VCC and whose drain is connected to a reference bit line (RBIT_B), and a fourth NMOS transistor ( 273 ), whose drain is connected to the reference bit line, whose source is connected to VSS and whose gate is supplied with a reference bit line level control signal (C3N_T). 50. Memory according to one of claims 1-30, characterized in that
a core block with a sense amplifier is shared by an upper cell array block and a lower cell array block, with:
a sense amplifier ( 260 ) connected to bit lines (BIT_T, RBIT_T, BIT_B and RBIT_B) connected to a reference cell and any memory cell in the upper cell array and lower cell array, and the data on the lines corresponding to sense amplifier activation signal (SAP_C and SAN_C) records and amplifies data on the lines;
an equalization circuit ( 261 ) for equalizing the potentials of the bit lines BIT_T and RBIT_T or the bit lines BIT_B and RBIT_B in accordance with equalization signals (C3N_C and C3P_C);
a first and a second transmission gate ( 262 , 263 ), which are switched by connection signals (C1P_T, C1N_T, C2P_T, C2N_T) for the upper cell array, and then selectively bit lines BIT_T and RBIT_T, which are connected to the upper main memory, and Connect reference cells to the input and output lines of the sense amplifier;
a third and a fourth transmission gate ( 264 , 265 ), which are switched by connection signals (C1P_B, C1N_B, C2P_B, C2N_B) for the lower cell array, and then selectively the bit lines BIT_B and RBIT_B, which are connected to the lower main memory, and connect reference cells to the input and output lines of the sense amplifier;
a fifth transmission port ( 266 ) connected to the input and output ports of the sense amplifier and controlling connection to a data bus (D_BUS) in accordance with column select signals (Y_n and YB_n); and
a sixth transmission gate ( 267 ), which is connected more strongly to the reading amplifier and controls the connection to a data bus (D_BUS) in accordance with the column selection signals. 51. Memory according to claim 50, characterized by:
a first bit line level controller ( 268 ) connected between the first transfer gate ( 262 ) and the bit line (BIT_T) of the upper memory cell and controlling the level of this bit line in accordance with a pull-down control signal (C3N_T) applied to a gate; and
a second bit line level control ( 269 ), one electrode of which is connected to the bit line (BIT_B) between the third transfer gate ( 264 ) and the lower memory cell array block and which corresponds to the level of the bit line corresponding to a pull-down control signal applied to a gate (C3N_B) controls. 52. The memory of claim 51, characterized in that when an upper main cell column and a reference cell column are selected, the first bit line level controller ( 268 ) is turned on, it pulls down, and it does the bit lines (BIT_T and RBIT_T) that are connected to the upper main memory cell or the reference cell, brings them to a low potential. 53. The memory of claim 51, characterized in that when a lower main cell column and a reference cell column are selected, the second bit line level controller ( 269 ) is turned on, it performs a pull-down operation, and the bit lines (BIT_B and RBIT_B) that are connected to the lower main memory cell or the reference cell, brings it to a low potential. 54. Memory according to claim 50, characterized by an NMOS transistor, one electrode of which is connected to the sense amplifier ( 260 ) and the other electrode of which is connected to ground (VSS), its gate having a sense amplifier activation signal (SAN_C ) is supplied, the low state of which activates the sense amplifier and the high state of which deactivates the sense amplifier. 55. Memory according to claim 50, characterized by a PMOS transistor, one electrode of which is connected to the sense amplifier ( 260 ) and the other electrode of which is connected to a supply voltage connection (VCC), its gate having a sense amplifier activation signal (SAP_C) is supplied, whose low state activates the read amplifier and whose high state deactivates the sense amplifier. 56. Memory according to claim 50, characterized in that the equalization circuit ( 261 ) equalizes the potentials of the bit lines (BIT_T, RBIT_T, BIT_B and RBIT_B) of the main cell and the reference cell and the potential of the sense amplifier before the divided word lines (SWL1 and SWL2) can be activated. 57. Memory according to claim 50, characterized in that the first to sixth transmission gates ( 262 to 267 ) each consist of an NMOS transistor. 58. Method for operating a memory according to one of the preceding claims in read mode with the following steps:

• Pulling the bit lines and the reference level to a low level before the word lines are activated,
• Loading a main memory cell data onto the bit line and a reference level generator data onto a reference line, and
• - Feedback of an output signal of the sense amplifier, which is operated by egg NEN column decoder ( 103 a, 103 b) and amplifies the difference between the data level of the bit line and the data level of the reference line, on the bit line.

59. A method of operating a non-volatile ferroelectric memory having a core block having a sense amplifier and an input / output circuit shared between an upper cell array block and a lower cell array block, and having a global control pulse generator according to any one of claims 13 to 57, wherein the global control pulse generator, when an address Y is switched, generates control signals whose period from the time when a chip enable signal CSBpad is activated to a low state until the time when this signal is deactivated in a high state in 15 intervals from t1 to t15 is divided, characterized by the following steps:

• - A first step in which each of preparatory signals (S1, S2) for driving a SWL driver, preparatory signals (C1, C2) for a bit line connection, a preparatory signal (C4) for column selection, a signal (P2) to ensure normal operation of the signals S1 and S2, a preparatory signal (C3) for equalizing a bit line potential and preparatory signals for sense amplifier activation (SAN, SAP) in the interval t1, the states, L, L, H, H, L, L, H , L and H hold, respectively, in the interval t2, in which the two signals S1 and S2 change to the high state, only the signals P2 and C3 change to the high or low state, and in the interval t3, in which the two signals S1 and S2 keep the high state, the signals C1, C3 and SAP change to the low state and also the signal SAN changes to the low state;
• - A second step in which only the signals C1 and C4 in the interval t4, in which the signals S1 and S2 change to the low and high states, transition to the high state, while the other signals change their states before the interval hold t4;
• - A third step in which all signals in the interval t5, in which the signals S1 and S2 go to the high or low state, keep their previous states without transition, being in the interval t6, in which both signals S1 and S2 go low, only signal P2 goes low;
• a fourth step in which all signals in the intervals t7 and t8 in which a signal Y-ATD is activated, t9 and t10 in which this signal is deactivated again, t11 and t12 in which it is in turn activated, and t13 and t14, in which it is deactivated again, keep their state from the interval t6 of the third step; and
• - A fifth step in which all signals in the interval t15, in which the signal CSBpad is deactivated to the high state, assume the same states as in the interval t1.

60. A method of operating a non-volatile ferroelectric memory comprising a core block having a sense amplifier and an input / output circuit shared between an upper cell array block and a lower cell array block, and having a global control pulse generator according to any one of claims 13 to 57, wherein the global control pulse generator, when addresses X and Z are switched, generates control signals whose period from the time when a chip enable signal CSBpad is activated low to the time when this signal is deactivated high in 21 intervals is divided from t1 to t21, characterized by the following steps:

• - A first step in which each of preparatory signals (S1, S2) for driving a SWL driver, preparatory signals (C1, C2) for a bit line connection, a preparatory signal (C4) for column selection, a signal (P2) to ensure normal operation of the signals S1 and S2, a preparatory signal (C3) for equalizing a bit line potential and preparatory signals for sense amplifier activation (SAN, SAP) in the interval t1, the states, L, L, H, H, L, L, H , L and H hold, respectively, in the interval t2, in which the two signals S1 and S2 change to the high state, only the signals P2 and C3 change to the high or low state, and in the interval t3, in which the two signals S1 and S2 keep their high state, only the signals C1, C3 and SAP change to the low state;
• - A second step in which only the signals C1 and C4 go to the high state and the signals SAN and SAP are activated in the interval t4, in which the signals S1 and S2 go to the low and high states, respectively;
• - A third step in which all signals keep their states from the interval of the second step without transition in the interval t5, in which the signals S1 and S2 change to the high or low state, and in the interval t6, in which the both signals S1 and S2 go low, only signal P2 goes low, while all other signals maintain the states from interval t5;
• a fourth step in which signals C1 and C3 go high again and signal C4 goes low while signals SAN and SAP are deactivated;
• - a fifth step, in which all signals have the same states as in the intervals from t1 to t6, according to the corresponding intervals in the same order, in the intervals from t8 to t13, in which the (X, Z-ATD) Signal is deactivated, and they assume the same states in interval t14 in which the (X, Z-ATD) signal is activated as in interval t7; and
• - a sixth step in which all signals assume the same states as in the intervals from t1 to t6, according to the corresponding interval in the same order, in the intervals from t15 to t20 in which the (X, Z-ATD) - Signal is deactivated, and in the interval t21, in which the (X, Z-ATD) signal is activated, they assume the same states as in the interval t1.

61. A method of operating a non-volatile ferroelectric memory having a core block with a sense amplifier and an input / output circuit according to any one of claims 13-57, wherein the core block is shared by an upper cell array block and a lower cell array block, the data write mode corresponding to the switching of a signal for the address Y for the upper cell array block a period from the time when chip enable signals CSBpad and WEBpad are activated in the low state until a time when the signals are deactivated in the high state divided into 15 intervals from t1 to t15 with the following steps:

• - A first step in the preparatory SWL control signals (PS1_T, PS2_T), SWL control signals (SWL1, SWL2), control signals (C1N_T, C2N_T) for a bit line connection, a signal (C4N_T) for column selection, a blocking signal (P2 ) to prevent a disturbance in the generation process for the preparatory SWL control signal, a signal (C3N_C) for bit line equalization and sense amplifier enable signals (SAP_C, SAN_C), the states H, H, L, L, H, H, L, L, H, L and H in the interval t1, and in the interval t2, in which a detection signal Y-ATD is deactivated regarding a transition of an address Y, the signals PS1_T, PS2_T and C3N_T change to the low state, while the signals SWL2 and C4N_T change to the high state, and in the interval t3 the signals C1N_T and C2N_T change to the low state and the signals SAN_C and SAP_C are activated, while all the other signals each retain their previous state ;
• - A second step in which the signals PS1_T and C1N_T go high in the interval t4 and the signal SWL1 goes low, in the interval t5 the signals PS1_T and SWL2 go low and the signals PS2_T and SWL1 go to the high state, in the interval t6 the signal PS1_T goes to the high state and the signals SWL1 and P2 go to the low state, while all the other signals maintain their previous state;
• - A third step in which the signal PS1_T goes low in the interval t7 and the signal SWL1 goes high while the signal Y-ATD is active, and in the interval t8 the signal PS2_T goes low passes and the signal SWL2 goes to the high state, while all the other signals maintain their previous state;
• a fourth step, in which the signal PS1_T goes high in the interval t9 and the signal SWL1 goes low while the signal Y-ATD is deactivated, and in the interval t10 the signal PS2_T goes high and the signal SWL2 changes to the low state, while all the other signals each retain their previous state;
• a fifth step in which, at intervals t11 and t12, each of the signals PS1_T, SWL1, PS2_T and SWL2 has the same change of state as in the third step, while the signal Y-ATD maintains the active state, while all of their signals have their previous ones Maintain condition; and (X, Z-ATD) signal is activated, assume the same states as in the interval t7; and
• a sixth step in which, at intervals t13 and t14, each of the signals PS1_T, SWL1, PS2_T and SWL2 has the same change of state as in the fourth step, while the signal Y-ATD maintains the inactive state, while all the other signals each have their previous state maintained.

62. A method of operating a non-volatile ferroelectric memory having a core block with a sense amplifier and an input / output circuit according to any one of claims 13-57, wherein the core block is shared by an upper cell array block and a lower cell array block, wherein the data semodus corresponding to the switching of a signal for the address Y for the upper cell array block a period from the point in time when the chip enable signal CSBpad is activated in the low state until a point in time when the signal WEBpad is deactivated in the high state, which in 15 intervals are divided from t1 to t15, with the following steps:

• - A first step in the preparatory SWL control signals (PS1_T, PS2_T), SWL control signals (SWL1, SWL2), control signals (C1N_T, C2N_T) for a bit line connection, a signal (C4N T) for column selection, a blocking signal (P2) to prevent a disturbance in the generation process for the preparatory SWL drive signal, a signal (C3N_C) for bit line compensation and sense amplifier enable signals (SAP_C, SAN_C), the states H, H, L, L, H, H, L, L, H, L and H in the interval t1, and in the interval t2, in which a detection signal Y-ATD is deactivated regarding a transition of an address Y, the signals PS1_T, PS2_T and C3N_T change to the low state while the Signals SWL2 and P2 go high and where in interval t3 signals C1N_T and C2N_T go low and signal C4N_T goes high and signals SAN_C and SAP_C are activated while all others signals always retain their previous state;
• - A second step in which the signals PS1_T and C1N_T go high in the interval t4 and the signal SWL1 goes low, in the interval t5 the signals PS1_T and SWL2 go low and the signals PS2_T and SWL1 go to the high state, in the interval t6 the signal PS1_T goes to the high state and the signals SWL1 and P2 go to the low state while all other signals each maintain their previous state;
• - a third step in which in the intervals t7 and t8 all signals each retain their previous state, while the signal Y-ATD is activated;
• a fourth step, in which, at intervals t9 and t10, all signals maintain their previous state while the signal Y-ATD is deactivated;
• a fifth step, in which, at intervals t11 and 12, all signals maintain their previous state while the Y-ATD signal is activated; and
• - A sixth step, in which, in intervals t13 and t14, all signals maintain their previous state, while signal Y-ATD is deactivated.

63. A method of operating a non-volatile ferroelectric memory, comprising a core block with a sense amplifier and an input / output circuit according to any one of claims 13-57, wherein the core block is shared by an upper cell array block and a lower cell array block, wherein the data semodus corresponding to the switching of a signal for the addresses X, Z for the upper cell array block a period from the time at which chip enable signals CSBpad and WEBpad are activated in the low state until a time at which the signals are deactivated in the high state , which is divided into 21 intervals from t1 to t21, with the following steps:

• - a first step, in the preparatory SWL control signals (PS1_T, PS2_T), SWL control signals (SWL1, SWL2), control signals (C1N_T, C2N_T) for a bit line connection, a signal (C4N_T) for column selection, a blocking signal ( P2) to prevent a disturbance in the generation process for the preparatory SWL drive signal, a signal (C3N_C) for bit line compensation and sense amplifier enable signals (SAP_C, SAN_C), the states H, H, L, L, H, H, L, L , H, L and H in the interval t1, and the signals PS1_T, PS2_T and C3N_T in the interval t2, in which a (X, Z-ATD) detection signal relating to a transition of an address X, Z is deactivated go low while signals SWL1, SWL2, C4N_T and P2 go high, and in interval t3 signals C1N_T and C2N_T go low and signals SAN C and SAP C are activated while all others Signal each their previous Maintain condition;
• - A second step in which the signals PS1_T and C1N_T go high in the interval t4 and the signal SWL1 goes low, in the interval t5 the signals PS1_T and SWL2 go low and the signals PS2_T and SWL1 go to the high state, in the interval t6 the signal PS1_T goes to the high state and the signals SWL1 and P2 go to the low state, while all the other signals maintain their previous state;
• - a third step in which, in the interval t7, in which the (X, Z-ATD) signal is activated, the signals SAN_C and SAP_C are deactivated, the signals C2N_T and C3N_C go into the high state, the signal C4N_T into the goes low and each of the other signals maintains its previous state without transition;
• - A fourth step in which, in the intervals from t8 to t14, when the next (X, Z-ATD) detection signal is activated for a transition of the addresses X, Z, all signals have the same states as in the intervals from t1 to t7, in the same order according to the corresponding intervals, and in the intervals from t15 to t20 the signals assume the same states as in the intervals from t1 to t6, in the same order; and
• - A fifth step in which the signals CSBpad and WEBpad are deactivated in the high state in the interval t21 and all other signals are in the same state as in the interval t1.

64. A method of operating a non-volatile ferroelectric memory having a core block with a sense amplifier and an input / output circuit according to any one of claims 13-57, wherein the core block is shared by an upper cell array block and a lower cell array block, the Data reading mode corresponding to the switching of a signal for the address Y for the upper cell array block a period from the time at which the chip enable signals CSBpad and WEBpad are activated in the low state until a time at which the signals are deactivated in the high state , which is divided into 21 intervals from t1 to t21, with the following steps:

• - A first step in the preparatory SWL control signals (PS1_T, PS2_T), SWL control signals (SWL1, SWL2), control signals (C1N_T, C2N_T) for a bit line connection, a signal (C4N_T) for column selection, a blocking signal (P2 ) to prevent a disturbance in the generation process for the preparatory SWL control signal, a signal (C3N_C) for bit line equalization and sense amplifier enable signals (SAP_C, SAN_C), the states H, H, L, L, H, H, L, L, H, L and H in the interval t1, and in the interval t2, in which a Y-ATD detection signal is deactivated regarding a transition of an address Y, the signals PS1_T, PS2_T and C3N_T change to the low state, while the signals SWL1, SWL2 and P2 change to the high state, and in the interval t3 the signals C1N_T and C2N_T change to the low state and the signal C4N_T changes to the high state and the signals SAN_C and SAP_C are activated while all a change signal to maintain their previous state;
• - A second step in which the signals PS1_T and C1N_T go high in the interval t4 and the signal SWL1 goes low, in the interval t5 the signals PS1_T and SWL2 go low and the signals PS2_T and SWL1 go to the high state, in the interval t6 the signal PS1_T goes to the high state and the signals SWL1 and P2 go to the low state, while all the other signals maintain their previous state;
• - a third step in which, in the interval t7, in which the (X, Z-ATD) signal is activated, the signals SAN_C and SAP_C are deactivated, the signals C2N_T and C3N_C go into the high state, the signal C4N_T into the goes low and each of the other signals maintains its previous state without transition;
• - A fourth step in which, in the intervals from t8 to t14, when the next (X, Z-ATD) detection signal is activated for a transition of the addresses X, Z, all signals have the same states as in the intervals from t1 to t7, in the same order according to the corresponding intervals, and in the intervals from t15 to t20 the signals assume the same states as in the intervals from t1 to t6, in the same order; and
• - A fifth step in which the signals CSBpad and WEBpad are deactivated in the high state in the interval t21 and all other signals are in the same state as in the interval t1.