DE19908446A1 - Dynamic random access memory (DRAM) cell capacitor fabricating method - Google Patents

Abstract

The method involves providing a semiconductor substrate (10) with a pair of source/drain regions aligned with the lateral edges of a gate electrode. A pair of storage contact pads is formed to the source/drain regions. A first insulating layer is formed over the substrate. A conductive layer pattern (24a) is formed over the first insulating layer (18,20), overlapping one of the storage contact pads (16) and extending in a lateral direction of the one of the pads. A second insulating layer (28) and a first material layer (30) are sequentially formed over the first insulating layer including the conductive layer pattern. The first material layer has etch selectivity with respect to the second insulating layer. The first material layer, the second insulating layer, and the conductive layer pattern are sequentially etched using a first photolithography. A first opening (32) is formed to the first insulating layer over the one storage contact pad and penetrates one end of the conductive pattern. Conductive sidewall spacers (34) formed in the first opening are used with the first material layer as a mask. The first insulating layer is etched down to the one storage contact pad. A second opening (36) is also formed. A conductive material deposited in both openings and over the first material layer is planarized down to the second insulating layer to form a first conductive pole (38). The second insulating layer is etched until the first insulating layer and the other end of the conductive layer pattern is exposed using a second photolithography. A third opening, formed spaced apart from the first opening, is filled with the same material as the first conductive pole to form a second conductive pole (44) which is connected to the first through the conductive layer pattern. The poles and the conductive layer pattern constitute a storage electrode of the DRAM capacitor. An Independent claim is included for a DRAM cell capacitor.

Description

The invention relates to a semiconductor component and in particular a DRAM cell capacitor with increased Surface contents and a method for the same Manufacturing.

Achieving sufficient charge storage capacity in a small area is one of the strongest challenging development problems of the technology of the dynamic random access memory (DRAMs) with Ultra-Highest Integration (ULSI). Since the push on DRAMs with higher density increases, the charge storage device each memory cell physically into an ever smaller area fit. The reduction in cell capacity caused by the reduced memory cell area is caused by a serious obstacle to increasing Packing density in DRAMs. So the problem of reduced cell capacity to be solved in one Semiconductor memory device to a higher packing density to reach.

To have a capacitance of such a capacitor on a to keep usable value, stack capacitors were used proposed a three-dimensional structure. Such  Stacked capacitors include, for example, cylindrical and simple box-shaped capacitors. Since both the outside and also the inner surfaces as an effective capacitor surface can be used is the cylindrical structure advantageously for the three-dimensional Stack capacitor suitable. Recently, the Increasing the effective surface area by Modifying the surface morphology of the polysilicon Storage electrode itself by etching or controlling the Nuclear formation and growth condition of polysilicon new Technologies developed. A polysilicon layer with hemispherical granules (HSG) can over a Storage electrode to be deposited around the To increase surface area and capacity.

However, the limits of the photolithography process make it difficult to put in such a cylindrical capacitor Circuit applications with ultra-high integration too structure, and the formation of HSG silicon is the Exposed to danger of a short circuit between neighboring ones To cause storage electrodes and requires one complex process. On the other hand, the simple one box-shaped capacitor in that it has disadvantages cannot provide sufficient capacity.

Accordingly, there is a strong need for a process that a capacitor with a very large surface area or area of a storage electrode for a high Can provide capacity while the complexity of the Process is minimized.

It is therefore an object of the invention to provide a capacitor with significantly increased surface areas and a Process for its production with a simple process to provide.  

To this end, the present invention provides one two-pole capacitor ready, with one conductive pole out Polysilicon with the other conductive pole made of polysilicon via a polysilicon line layer structure (i.e. a connecting bridge) is electrically connected. One of conductive poles penetrates through the polysilicon structure and through the insulation layers and extends to underlying contact point (or diffusion layer) The connecting bridge is formed after the formation of one of the Contacts of the conductive pole with the contact point and before the formation of the other conductive pole. Of the conductive pole in contact with the contact point (or Diffusion layer) is placed in a self-adjusting manner Use conductive sidewall spacers Polysilicon formed. In short, will be a first Opening formed in an insulation layer and then sidewall spacers are formed therein. After that, a second opening is made in an underlying one further isolation to the contact point using the Spacer layers formed as a mask. A conductive Layer for a storage electrode is used in the first and second openings deposited to the first conductive pole to train. Therefore there is no possibility of one Misalignment between the first opening and the second Opening, corresponding to a misalignment between the Memory contact hole and the storage electrode.

To achieve these and other advantages in accordance with the purpose of the invention To achieve, the process for producing the bipolar capacitor forming a component Insulation layer on a semiconductor substrate to make active and define inactive areas. A gate electrode and a source / drain area will be on and in the Semiconductor substrate formed. A first oxide layer is formed over the entire semiconductor substrate. Through a suitable method is a memory contact point in the Oxide layer formed to the source / drain region. A  second oxide layer is over and over the first oxide layer the contact point. A bit line is on the second oxide layer is formed. A third oxide layer and a silicon nitride layer are successively over the second oxide layer and formed on the bit line.

A first polysilicon layer is over the Silicon nitride layer for use as a connecting bridge deposited between two leading poles. The first The polysilicon layer is then patterned to a first To form a polystructure that is new to this invention, which overlaps the contact point and is in Lateral direction of the contact point extends. A fourth Oxide layer, which is called protective oxide layer, is about the silicon nitride layer and on the polystructure educated. This protective oxide layer has a thickness which determines the height of the storage electrode, therefore changes their thickness depending on the desired Capacity. Preferably the thickness is about 8000 Å to 11,000 Å. A layer of material with an etch selectivity regarding The fourth oxide layer is for use as an etching mask during the subsequent etching of the fourth oxide layer over it deposited. For example, a polysilicon layer be used as this layer of material.

A first layer of photoresist is applied to the material layer made of polysilicon and structured to form a adjusted over an end part of the polystructure Form the opening area. Using this first structured photoresist layer Material layer, the fourth oxide layer, the polystructure and etch the silicon nitride layer around a first opening with essentially vertical side walls up to the third Form oxide layer down. It should be noted that part of the polystructure in the fourth oxide layer is buried and to a side wall of the first opening and is adjusted over the silicon nitride layer. After  Removing the first structured photoresist layer are made of conductive sidewall spacers Polysilicon in the first opening with a thickness of approximately 250 Å trained. Using the polysilicon Material layer and the side wall spacer layers The third and second polysilicon as an etching mask Oxide layer etched down to the contact point in order to thereby forming a second opening. Based on these Sidewall spacers is the second opening to the self-adjusting first opening. A Storage electrode material, i. H. a polysilicon layer, is in the first and second openings and over the Polysilicon material layer deposited and then up to fourth planarized layer down, creating a first conductive pole made of polysilicon for the bipolar Storage electrode is formed.

A second layer of photoresist is applied to the fourth Oxide layer applied and structured to one over the Polystructure and part of the silicon nitride layer trained adjusted opening area. Under use the second structured photoresist layer is the fourth oxide layer to the polystructure and the Etched down silicon nitride layer to form a third Training opening. This is part of the polystructure buried in the fourth oxide layer and to the side wall of the first conductive pole adjusted. This third opening is separated from the first conductive pole by about 100 nm and with the first conductive pole over that in the fourth Oxide layer buried remaining polystructure electrically connected. The rest of the polystructure protrudes from the a sidewall of the first conductive pole into the third Opening into it. After removing the second structured photoresist layer becomes a conductive Material for a storage electrode, i. H. Polysilicon, in the third opening deposited to a second conductive pole for the two-pole storage electrode  to train. As from the explanation above is the second conductive pole with the first conductive pole over the rest of the polystructure at the bottom Part connected. Hence the bipolar capacitor fully trained. The size of the second senior Pols can be increased to the surface contents or areas to be further increased. Then one dielectric layer and an upper electrode over the Storage electrode formed, causing the capacitor is trained.

This capacitor has advantages in that it by forming an additional storage electrode (second conductive pole) and connecting to the Main storage electrode over the connecting bridge (Polystructure) an increased surface area owns. In addition, the main storage electrode (first conductive pole) through the use of side wall Spacers made of polysilicon in self-adjusting Trained way and the process step for the Main storage electrode can be simplified.

An embodiment of the invention is shown below explained in more detail with reference to the drawing. Show it:

. Fig. 1A through 1G show at selected stages of manufacture, the cross-sectional views taken along the bit line of a DRAM cell capacitor according to an embodiment of the invention;

. Fig. 2A to 2G show at selected stages of manufacture, the cross-sectional views along the word line direction of a DRAM cell capacitor according to an embodiment of the invention;

Fig. 3 is a plan view of a DRAM cell capacitor after forming a Polystruktur according to the embodiment of the invention;

Fig. 4 is a plan view of a DRAM cell capacitor after forming a first opening according to the embodiment of the invention;

Fig. 5 is a plan view of a DRAM cell capacitor after forming poly sidewall spacers in the first opening and then forming a second opening according to the embodiment of the invention;

Fig. 6 is a plan view of a DRAM cell capacitor after forming a second conductive pole according to the embodiment of the invention; and

Fig. 7 shows schematically the resulting bipolar memory electrode structures according to the embodiment of the invention.

The invention relates to a DRAM cell capacitor and a method for producing the same. The process of forming the field oxide layer and the structure of the field effect transistor that is currently practiced in the manufacture of DRAM cells is only briefly described in order to better understand the current invention. Fig. 1A to Fig. 1G show at selected stages of manufacture, the cross-sectional views taken along the bit line of a DRAM cell capacitor in accordance with an embodiment of the invention, and Fig. 2A to Fig. 2G show at selected stages of manufacture, the cross-sectional views along the word line direction of a DRAM cell capacitor according to an embodiment the invention. In Fig. 2A to Fig. 2G, the same function parts that are shown in Fig. 1A to Fig. 1C are denoted by identical reference numerals, and for the sake of a better understanding of this invention, the preferred embodiment of the invention with reference to FIGS. 1 and Fig. 2 described simultaneously.

With reference to Fig. 1A and Fig. 2A is a Bauelement- insulating layer 12, ie, a field oxide layer, formed in a predetermined region of a semiconductor substrate 10, an active region 11 and defining an inactive region thereon. The device isolation layer 12 is formed by conventional methods, such as. B. shallow trench insulation. Local oxidation of silicon can alternatively be used. A plurality of gate electrodes 14 having a protective insulation layer (ie, a hard mask and sidewall spacers) are formed on the semiconductor substrate 10 using a conventional photolithography and etching process. A plurality of source / drain regions (not shown) are formed in the semiconductor substrate 10 , aligned with the side edges of the gate electrodes 14 , using a conventional ion implantation process. A first oxide layer 15 is formed over the entire semiconductor substrate 10 , including the gate electrodes 14 . A plurality of memory pads 16 are formed in the first oxide layer 15 to the source / drain regions by a suitable method. A second oxide layer 18 is formed over the first oxide layer 15 and on the contact points 16 . A plurality of bit lines 19 are formed on the second oxide layer 18 . A third oxide layer 20 is formed over the second oxide layer 18 and on the bit lines 19 . A layer 22 that has an etch selectivity with respect to the third oxide layer 20 , for example a silicon nitride layer 22 , is formed on the third oxide layer 20 . This silicon nitride layer 22 is used as an etching stop layer in the subsequent etching of a fourth oxide layer and does not have to be formed.

The next step is critical to this invention. A first polysilicon layer 24 is deposited over the silicon nitride layer 22 for use as an electrical connection bridge 24 a between two conductive poles 38 and 44 of FIG. 1G, which form a storage electrode 46 together with the connection bridge 24 a. This first polysilicon layer 24 is formed with a thickness of about 550 Å to 1000 Å.

With reference to Fig. 1B and Fig. 2B, a first photoresist layer is deposited on the first polysilicon layer 24 and patterned. Using this first patterned photoresist layer 26 , the first polysilicon layer 24 is then etched down to the silicon nitride layer 22 to form a variety of polystructures (bridges) that are new to this invention. For example, a polystructure 24 a is formed which overlaps the contact point 16 and extends in the lateral direction of the contact point 16 . A detailed explanation is given with reference to FIG. 3, a top view of a DRAM cell capacitor after the formation of the polystructures 24 a. In Fig. 3, the polystructure 24 a is formed over the silicon nitride layer 22 with a predetermined structure. The polystructure 24 a is formed such that it overlaps a part of the active region 11 , in particular is adjusted above the contact point 16 for the storage electrode, and at the same time the contact point 16 is arranged below it at one end of the polystructure 24 a. The polystructure 24 a has an elliptical shape or a rectangular shape and the longer dimension ("a") of the polystructure 24 a is approximately 350 nm, the shorter dimension ("c") of the same is approximately 150 nm. The distance between adjacent polystructures along the Bit line direction ("b") is approximately 250 nm and the distance between adjacent polystructures along the word line direction ("d") is approximately 150 nm.

With reference to Fig. 1C and Fig. 2C, the first patterned photoresist layer 26, the protective oxide layer is called after removing a fourth oxide layer 28 is formed over the silicon nitride layer 22 and on the Polystruktur 24 a. This protective oxide layer 28 has a thickness which defines the height of the storage electrode, therefore its thickness changes depending on the desired capacitance. In this embodiment, the protective oxide layer 28 is formed in a thickness of about 8000 Å to 11000 Å. A material layer 30 with an etch selectivity with respect to the fourth oxide layer 28 is deposited over the fourth oxide layer 28 for use as an etching mask during the subsequent etching of the fourth oxide layer 28 . For example, a polysilicon layer can be used as this material layer and has a thickness of about 1500 Å to 2000 Å.

A second layer of photoresist is applied to the material layer 30 and structured in order to form opening regions which are adjusted over one end of the polystructure 24 a, which is adjusted over the contact point 16 . Using this second structured photoresist layer 31 , the material layer 30 , the fourth oxide layer 28 , the polystructures 24 a and the silicon nitride layer 22 are etched to form a plurality of first openings. For example, a first opening 32 is formed which has essentially vertical side walls down to the third oxide layer 20 . It must be noted that part of the polystructure 24 a is buried in the fourth oxide layer 28 and is adjusted to a side wall of the first opening 32 and above the silicon nitride layer 22 . The first opening 32 is formed with an opening size ("e") of approximately 150 nm. Fig. 4 is a plan view of a DRAM cell capacitor after formation of the first opening 32. With reference to Fig. 4, the first opening is a calibrated 32 at one end of the Polystruktur 24 via the pad 16.

After removing the second patterned photoresist layer 31 conductive sidewall spacers 34 are formed in the first openings 32 of polysilicon having a thickness of about 250 Å as shown in Fig. 1E and shown Fig. 2E. Using the polysilicon material layer 30 and the sidewall spacer layers 34 made of polysilicon as an etching mask, the third and second oxide layers 20 and 18 are etched down to the contact points 16 , thereby forming a plurality of second openings. For example, a second opening 36 is formed with an opening size of approximately 100 nm. Because of these side wall spacing layers 32 , the second opening 36 is self-aligning with the first opening 32 . Here, the second opening 32 corresponds to the contact hole for the storage electrode of a conventional simple box-shaped capacitor. Therefore, the misalignment encountered in the prior art between the memory contact hole and the memory electrode can be avoided. Fig. 5 is a plan view of a DRAM cell capacitor after forming the poly sidewall spacers 34 in the first opening 32 and the forming the second opening 36. As can be seen, the second opening 36 is smaller than the first opening 32 by the thickness of the poly sidewall spacers 34 .

With reference to Fig. 1F and Fig. 2F, a conductive material, such as is. B. polysilicon, for the storage electrode in the first and second openings 32 and 36 and deposited over the polysilicon material layer 30 . Planarization etching is performed on the polysilicon and the polysilicon material layer 30 down to the fourth oxide layer 28 to form a plurality of first conductive poles for the storage electrodes. For example, a first conductive pole 38 is formed to the contact point 16 . The planarization etching can be a CMP (chemical mechanical polishing) or an etch back process. As described above, the polystructure 24 a is electrically connected to a side edge of the first conductive pole 38 and extends outward on the silicon nitride layer 22 .

The formation of the second conductive poles is next addressed. The second conductive pole must be connected to the first conductive pole 38 via the polystructure 24 a, which protrudes from the side edge of the first conductive pole 38 . For this purpose, a second photoresist layer is applied to the fourth oxide layer 28 and structured in order to form aligned opening regions over the other end part of the polystructure 24 a and the silicon nitride layer 22 . Using this patterned third photoresist layer 40 , the fourth oxide layer 28 is etched to form a plurality of third openings. For example, a third opening 42 is formed to the other end part of the polystructure 24 a and the silicon nitride layer 22 . Here, the polystructure 24 a and the silicon nitride layer 22 serve as etch stop layers. If the silicon nitride layer 22 is not formed, this etching of the fourth oxide layer 28 is carried out by time-controlled etching. In this embodiment, the third opening 42 has an opening size ("h") of about 200 nm and is spaced from the first conductive pole 32 by about 100 nm ("g").

After removal of the third structured photoresist layer 40 , a conductive material for the storage electrode, ie polysilicon, is deposited in the third openings and over the fourth oxide layer 28 . Planarization etching is performed on the polysilicon down to the fourth oxide layer 28 , thereby forming a plurality of second conductive poles for the storage electrodes. For example, a second conductive pole 44 is formed so that it is electrically connected to the first conductive pole 38 via the polystructure 24 a. Thereafter, the fourth oxide layer 28 is then removed in a wet etchant, thereby forming a plurality of two-pole storage electrodes 46 , each formed by the first conductive pole 38 , the second conductive pole 44 and the polystructure 24 a, as in Fig. 1G and Fig. 2G shown. The size of the second conductive pole 44 can be increased to further increase the surface areas.

Fig. 6 is a plan view of a DRAM cell capacitor after forming the second conductive pole 44th With reference to FIG. 6, the two-pole storage electrode comprises the first conductive pole 38 , which is in contact with the memory contact point (not shown), the second conductive pole 44 and the polystructure 24 a, which connects them to one another. The distance ("i") between adjacent memory electrodes, measured along the bit line direction, is approximately 150 nm. The distance between adjacent memory electrodes, measured along the word line direction, is approximately 150 nm.

Then, a dielectric layer (not shown) and an upper electrode (not shown) are formed on the storage electrode 46 , thereby forming the two-pole capacitor. The capacitor formed in this way has advantages in that it has an enlarged surface area by forming an additional storage electrode (second conductive pole) and connecting it to the main storage electrode via the connecting bridge (polystructure). In addition, by using the side wall spacers made of polysilicon, the main storage electrode (first conductive pole) is formed in a self-adjusting manner, and the process step for the main storage electrode can be simplified. According to this invention, since the surface area of the capacitor is enlarged sufficiently, the desired capacitance can be obtained using Ta ₂ O ₅ as the dielectric layer, although no ferroelectric dielectric material such as e.g. B. BST, is used, the formation of which requires a high temperature and causes an undesirable voltage.

Fig. 7 shows schematically two adjacent bipolar electrodes memory structures according to the invention. The bipolar memory electrode structure with reference to FIG. 1G and FIG. 7 reference taken. The two-pole storage electrode 46 includes the first conductive pole 38 , the second conductive pole 44 and the polystructure 24 a. The first and second conductive poles 38 and 44 are electrically connected to one another by the polystructure 24 a. The first conductive pole 38 penetrates one end of the polystructure 24 a and extends to the memory contact point 16 , which is in contact with the source / drain region. The second conductive pole 44 is in contact with the other end of the polystructure 24 a. The first conductive pole below the polystructure 24 a has a smaller size than that above the polystructure 24 a. It is apparent to a person skilled in the art that the size of the second conductive pole 44 can increase due to its size and the size of the polystructure 24 a. The upper dimension of the first conductive pole 38 is approximately 150 nm and its lower dimension is approximately 100 nm. The size of the second conductive pole 44 is approximately 200 nm. The distance between adjacent storage electrodes is approximately 150 nm and the distance between the first and the second conductive pole is about 100 nm.

Although this invention is particularly related to its preferred embodiments have been shown and described, it will be a matter of course for experts that various changes in form and details can be made without thinking and Depart from the scope of this invention.

Claims (14)

1. Method for producing a DRAM cell capacitor with the steps:
Providing a semiconductor substrate ( 10 ) having a gate electrode ( 14 ) and a pair of source / drain regions which are aligned with the side edges of the gate electrode ( 14 );
Forming a pair of memory pads ( 16 ) to the source / drain regions;
Forming a first insulation layer ( 20 ) over the semiconductor substrate ( 10 );
Forming a line layer structure ( 24 a) over the first insulation layer ( 20 ), the line layer structure overlapping one of the memory contact points ( 16 ) and extending in the lateral direction of one of the memory contact points, the conductive structure having two opposite ends;
sequentially forming a second insulation layer ( 28 ) and a first material layer ( 30 ) over the first insulation layer, including the conductive layer structure, the first material layer ( 30 ) having an etch selectivity with respect to the second insulation layer ( 28 );
sequentially etching the first material layer ( 30 ), the second insulation layer ( 28 ) and the conductive layer structure ( 24 a) using a first photolithography and forming a first opening ( 32 ) to the first insulation layer over the one of the memory pads ( 16 ), the first Opening ( 32 ) penetrates one end of the conductive structure;
Forming conductive sidewall spacers ( 34 ) in the first opening ( 32 );
Using the sidewall spacers ( 34 ) and the first material layer ( 30 ) as a mask and etching the first insulation layer down to one of the memory pads and forming a second opening ( 36 );
Depositing a conductive material in the first and second openings ( 32 , 36 ) and over the first material layer ( 30 ) and planarizing down to the second insulation layer ( 28 ) to form a first conductive pole ( 38 );
Etching the second insulation layer ( 28 ) until the first insulation layer and the other end of the conductive layer structure are exposed using a second photolithography and forming a third opening ( 42 ) spaced from the first opening; and
Filling the third opening ( 42 ) with the same material as the first conductive pole to form a second conductive pole ( 44 ), the second conductive pole ( 44 ) being connected to the first conductive pole ( 38 ) via the conductive layer structure ( 24 a) becomes,
wherein the first conductive pole ( 38 ), the second conductive pole ( 44 ) and the conductive layer structure ( 24 a) form a storage electrode ( 46 ) of the DRAM cell capacitor. 2. The method of claim 1, wherein the conductive layer structure ( 24 a) is made of the same material as the first conductive pole ( 38 ). 3. The method according to claim 1, wherein the second insulation layer ( 28 ) has at least the same thickness as the storage electrode ( 46 ). 4. The method of claim 1, wherein the second insulation layer ( 28 ) comprises an oxide layer and the first material layer ( 30 ) comprises a polysilicon layer. 5. The method of claim 1, wherein the conductive layer structure ( 24 a) has a thickness of about 550 Å to 1000 Å and the second insulation layer ( 28 ) has a thickness of about 8000 Å to 11000 Å and the first material layer ( 30 ) has a thickness from about 1500 Å to 2000 Å. 6. The method of claim 1, wherein the sidewall spacers ( 34 ) are made ( 38 ) of the same material as the first pole. 7. The method of claim 1, wherein the planarizing is carried out by CMP or etching back. 8. The method of claim 1, wherein the first opening ( 32 ) has a diameter of about 150 nm, the second opening ( 36 ) has a diameter of about 100 nm and the third opening ( 42 ) has a diameter of about 200 nm. 9. The method of claim 1, wherein the first conductive pole ( 38 ) and the second conductive pole ( 44 ) are spaced about 100 nm apart and the storage electrode ( 46 ) is spaced from an adjacent storage electrode by about 150 nm. 10. The method of claim 1, further comprising, prior to the step of forming the conductive layer structure ( 24 a), forming a second material layer ( 22 ) over the first insulation layer ( 20 ), the second material layer ( 22 ) having an etch selectivity with respect to the second insulation layer and serves as an etch stop layer during the step of forming the third opening ( 42 ). 11. The method according to claim 10, wherein the second material layer ( 22 ) is produced from a silicon nitride layer. 12. DRAM cell capacitor with:
a memory pad ( 16 ) formed over a semiconductor substrate ( 10 ) and electrically connected to a source / drain region of the semiconductor substrate;
an insulation layer ( 20 ) over the semiconductor substrate ( 10 ), including the memory pad ( 16 ); and a storage electrode ( 46 ) for the DRAM cell capacitor with a first and a second conductive pole ( 38 , 44 ), the first and the second conductive pole being spaced apart, but via a conductive layer structure ( 24 a), which over the insulation layer ( 20 ) is formed, are electrically connected to one another, the first conductive pole ( 38 ) penetrating through the insulation layer and being electrically connected to the memory contact point ( 16 ). 13. DRAM cell capacitor according to claim 12, wherein the first conductive pole ( 38 ) has a diameter of about 150 nm at the upper part and a diameter of about 100 nm at the lower part in the insulation layer and the second conductive pole ( 44 ) one Has a diameter of about 200 nm. 14. The DRAM cell capacitor of claim 12, wherein the first and second poles ( 38 , 44 ) are spaced apart by approximately 100 nm and the storage electrode ( 46 ) is spaced apart by an adjacent storage electrode by approximately 150 nm.