DE19905749A1 - CMOS standby current reduction circuit - Google Patents

Abstract

A PMOS transistor is connected to a power supply voltage terminal (Vcc). An NMOS transistor is connected to a ground voltage terminal (Vss). A switching device (33) is connected between the two transistors to cut off leakage current flowing to the NMOS transistor from the PMOS transistor.

Description

The invention relates to semiconductor devices, and more particularly it relates to a circuit for reducing the current in the loading Ready state of a low voltage circuit.

In general, the transistor voltage is lowered to the Signal transmission speed in a low voltage circuit to decrease, resulting in a substantial increase of the threshold leakage current in the standby state, des Reduction is a key problem.

Known circuits for reducing the current in the standby state will now be explained with reference to the accompanying FIGS. 1 and 2. In known circuits for reducing the current in the standby state in order to reduce leakage currents as they flow through multiple logic circuit units, PMOS and NMOS transistors, both with high threshold voltages, are present outside the logic circuit units to control the leakage currents, that flow through the entire circuit.

Fig. 1 illustrates a first exemplary prior art circuit to reduce the current in the standby state. This circuit is provided with a main voltage supply line Vcc and a ground line Vss, a sub-voltage supply line Vcc-L and a sub-ground line Vss-L, a PMOS transistor HPM1 between the main voltage supply line and the sub-voltage supply line, one NMOS transistor HNM1 between the main ground line and the sub-ground line and a plurality of logic circuits, between the sub-voltage supply line and the sub-ground line. Each of the logic circuits 11 is provided with a plurality of PMOS and NMOS transistors, both of which have low threshold voltages. The PMOS transistor HPM1 between the main and the sub-voltage supply line and the NMOS transistor HNM1 between the main and the sub-ground line have threshold voltages that are relatively higher than those of the transistors in the logic circuits 11 . The NMOS transistor HNM1 has a gate which is designed such that an active signal ACT can be applied to it, and the PMOS transistor HPM1 has a gate which is designed such that an active negative signal ACT is applied to it is created.

Now the function of this first exemplary known one Circuit for reducing the current in the standby state explained.

As shown in Fig. 1, when the circuit is active, the PMOS transistor HPM1 and the NMOS transistor HNM1 are turned on to the under-voltage supply line Vcc-L to a voltage of the level Vcc and the sub -Mass line Vss-L to charge a voltage of the level Vss. Accordingly, the circuit functions as a conventional circuit in which an output signal is supplied in accordance with the system of the logic circuit 11 . When the circuit is in the standby state, the PMOS transistor HPM1 and the NMOS transistor HNM1 are turned off, which causes the sub-voltage supply line and the sub-ground line to be separated from the main voltage supply line and the main ground line, respectively In order to ensure that the voltage on the sub-voltage supply line corresponds to the supply voltage applied to the plurality of logic circuits 11 and the voltage on the sub-ground line corresponds to the ground voltage applied to the logic circuits 11 . In this case, the leakage current flowing through the logic circuit increases when the supply voltage is higher, and vice versa. By separating the sub-voltage supply line and the sub-ground line from the main voltage supply line and the main ground line, respectively, the supply voltage via the logic circuit 11 can be lower, which leads to a reduction in the leakage current.

Fig. 2 illustrates a second exemplary prior art circuit to reduce the current in the standby state. This circuit is provided with a main voltage supply line Vcc, a main ground line Vss, a sub-voltage supply line Vcc-L, a sub-ground line Vss-L, a PMOS transistor HPM1 between the main and the sub-voltage supply line, one NMOS transistor HNM1 between the main and the sub-ground line, a first logic circuit part 21 between the main voltage supply line and the sub-ground line and a second logic circuit part 21 a between the sub-voltage supply line and the main ground line. In addition to the first and second logic circuits 21 and 21 a, several logic circuits can be present depending on the circuit system. The first and second logic circuit parts 21 and 21 a are provided with a plurality of PMOS and a plurality of NMOS transistors, wherein logic circuits whose transistors are switched on in order to predict ready states beforehand are connected to the main voltage supply line and the sub-ground line , while logic circuit parts whose transistors are turned off to predict standby states in advance are connected to the sub-voltage supply line and the main ground line, thereby halving loads on the sub-voltage supply line and the sub-ground line when the two logic circuit parts 21 and 21 a work.

However, in these known circuits for reducing the current in the standby state, there are the following problems:

• - First, the optimization of the sizes of the Transisto is required the main and sub-voltage supply lines connection as well as the main and the sub-ground line, to set the time period required to return from the ready state to the active state ren, a lot of time.
• - Second is the application of the circuit to automatic Circuit design difficult when the circuit is on working from top to bottom using a Netlist is designed in the circuit design formats as texts are available.
• - Third, the circuit takes up a lot of space and is complicated graces.
• - Fourthly, the transistors operate with a high threshold voltage voltage between the main and the low voltage supply supply line and between the main and sub-mass  line like capacitors when in standby the active state is returned, causing the under-voltage supply line and the under-ground line long periods of time need to recover voltages manufacture that with the tensions on the main chip Power supply line and the main ground line identical are.

The invention has for its object a circuit for Reducing the standby power to create can minimize leakage currents and maximize the time period can shorten that for the return from standby stood in the active state is required.

This task is accomplished by the circuits according to the th independent claims 1, 6 and 10 solved.

Additional advantages, tasks and other characteristics of the Er Invention are shown in part in the following description placed, and in part they are the specialist at the sub looking for the following or when practicing the invention recognizable. The objects and advantages of the invention will be discussed achieved through the measures as set out in the attached th claims are set out.

The invention will become apparent from the detailed Be description and the accompanying drawings, which are only for ver serve illustrative and therefore not for the invention restrictive, should be understood more fully.

Figs. 1 and 2 show a first and second exemplary be known circuit for reducing the current in the standby state;

FIGS. 3 and 4 respectively show a circuit for reducing current in a standby state according to a first or second preferred embodiment of the invention;

Fig. 5 shows an application of the first and second exporting approximately example of the invention in a NAND gate;

Fig. 6 shows a circuit for reducing current in a standby state according to a third preferred exporting approximately example of the invention; and

Fig. 7 and Fig. 8 illustrate respectively different sections of a CMOS transistor for explaining Fig. 6.

In a circuit according to the invention for reducing the Electricity is in standby for each of several Lo gikschaltungen a switching component (in the embodiment an NMOS or a PMOS transistor) is present, to reduce leakage currents.

Referring to FIG. 3, the circuit includes according to the first example of the invention exporting approximately a Spannungsversorgungsan circuit Vcc, a ground voltage terminal Vss, and a plurality of logic circuits 31 between these terminals. Each of the logic circuits 31 includes a PMOS transistor LPM1 with a low threshold voltage and an NMOS transistor LNM1 with a low threshold voltage, the source of the PMOS transistor LPM1 being connected to the voltage supply connection and the source of the NMOS transistor LNM1 being connected to the ground voltage connection . Between the PMOS transistor LPM1 and the NMOS transistor LNM1 is a switching component 33 , for. B. an NMOS transistor HNM1 with a high threshold lens voltage (hereinafter referred to as "selection transistor") to reduce leakage currents. A selection transistor 33 is provided for each of the plurality of logic circuits, and is turned on in active mode and off in standby mode.

The selection transistor may be an NMOS transistor with a low threshold voltage instead of the NMOS transistor HNM1 with a high threshold voltage. In Fig. 4 a circuit for reducing current in a standby state of the NMOS sistors Tran with low applied voltage is shown. It is a circuit according to the second preferred embodiment of the invention, and it shows a selection transistor in the form of an NMOS transistor with a low threshold voltage.

Now the functions of the above circuits become Decrease the standby current according to the first th and second preferred embodiment of the inventions explained.

. Referring to Figures 3 and 4 is supplied with a high signal to the gate of the selection transistor in the active mode and in standby mode, there is a low signal ver provides (0 V in the case of Figure 3, and a negative (-.) Voltage for reducing of the leakage current in the case of Fig. 4). I.e. that when a low signal is applied to the gate of the selection transistor 33 in the standby state, this transistor is switched off, as a result of which a leakage current path from the PMOS transistor LPM1 to the NMOS transistor LNM1 is interrupted. This interruption of the leakage current path can significantly reduce the threshold current below the threshold (according to a simulation, the reduction is approximately 10,000 times compared to the case in the prior art). In addition, the time period, as is necessary to achieve the standby state from the active state, is greatly reduced compared to the prior art, in which the main and under-voltage supply line and the main and sub-ground line available. For example, in the first and second embodiments, selection transistors in logic circuits with a PMOS transistor LPM1 and an NMOS transistor LNM1 are present in order to interrupt leakage currents such as can flow from the PMOS transistor LPM1 to the NMOS transistor LNM1. In the first and second exemplary embodiments, logic circuit parts are shown as examples, each consisting of a PMOS and an NMOS transistor with inverters, but the invention is independent of the number of PMOS and NMOS transistors in it on all logic circuit parts applicable. That is, such logic circuit parts include all logic circuits, such as. B. Inverter, NAND gate ter and NOR gate.

Fig. 5 illustrates an application of the first and second embodiments of the invention in a NAND gate with a first PMOS transistor LPM1 and a first NMOS transistor LNM1, the operating states of which are determined by a first input signal, a second PMOS transistor LPM2 and a second NMOS transistor LNM2, the operating states of which are determined by a second input signal, and a selection transistor 33 between the second PMOS transistor LPM2 and the second NMOS transistor LNM2. In this case, the selection transistor 33 is switched on in the active mode and is switched off in the standby mode. This selection transistor 33 is also present in the logic circuit of the NAND gate between the said transistors in order to interrupt leakage currents from the second PMOS transistor LPM2 to the second NMOS transistor LNM2 in the standby state. So there is applicability not only with a NAND gate, but with all logic circuits such as a NOR gate.

Referring to FIG. 6, the third exemplary embodiment of the invention includes a plurality of logic circuit sections 61-1, 61-2, 61-3, 61-4,. . ., Which are present between a voltage supply connection Vcc and a ground voltage connection Vss, a selection transistor 33 only for the odd-numbered logic circuit parts 61-1 , 61-3 , 61-5,. . . is available. In this case, as examples of the logic circuit parts 61-1 , 61-2 , 61-3 , 61-4 ,. . . Inverter used, the PMOS transistors LPM1, LPM2, LPM3, LPM4,. . . and NMOS transistors LNM1, LNM2, LNM3, LNM4,. . . exist, each showing low threshold voltages. Each of these PMOS transistors is formed in an n-well in a p-type semiconductor substrate 71 (see FIG. 7). The n-well is biased when Vcc is active. However, in the standby state, when the voltage of the n-well is raised to a voltage above Vcc (e.g. Vpp of a DRAM), the threshold voltages of the PMOS transistors LPM become higher, which reduces the leakage current below the threshold. In other words, as shown in Fig. 6, when a selection transistor 33 is provided only for the odd-numbered logic circuits, the circuit device can be kept in the standby state by applying a low level signal to the gate of the selection transistor 33 and the voltage on the n-well increases. With this procedure, a node 1 can be charged to a high state via the PMOS transistor LPM1 in the first logic circuit part 61-1, regardless of the input signal to the logic circuit part. Then the NMOS transistor LNM2 is turned on in the second logic circuit part 61-2 , which enables a leakage current to flow through the PMOS transistor LPM2, but at a significantly reduced rate due to the increased threshold voltage of the PMOS transistor LPM2 due to the voltage the n-tub.

While in the described embodiment, an n-well is formed in a p-substrate 71 and the voltage of the n-well is increased, as shown in FIG. 7, the structure can also be such that a p-well in an n -Substrate 81 is formed and the voltage of the p-well is reduced, as shown in Fig. 8. That is, the NMOS transistors LNM1, LNM2, LNM3, LNM4,. . . are shown in FIG. 6 is now formed in a p-well, as shown in Fig. 8, was prepared in a n-type semiconductor substrate 81. The p-well is biased by Vss in the active state. However, if the voltage on the p-well is reduced to a voltage below Vss (e.g. Vbb on a DRAM) in the standby state, the threshold voltages of the NMOS transistors LNM1, LNM2, LNM3, LNM4,. . . become higher, which reduces the leakage currents below the threshold voltage. Thus, the third embodiment of a circuit for reducing the current in the standby state with an n or a p well can be applied to an output driver such as a DRAN to improve the processing speed of the driver.

The circuit according to the invention for reducing the current in the standby state has the following advantages:

• - First, the leakage current can be significantly reduced be that simple switching components in logic circuits brought without a separate undervoltage supply line and a sub-ground line len are.
• - Second, an output driver with a preloaded tub improve the processing speed of a driver.
• - Third, the optimum made possible by the invention Transistor size significantly reduce the time it takes is required from the ready state to the active CL stood to get.
• - Fourth, the circuit according to the invention for reducing the standby power in automation of the circuit design applicable.

Claims (17)

1. Circuit for reducing the current in the standby state with:

• - With a voltage supply connection (Vcc) connected PMOS transistor and
• - An NMOS transistor connected to a ground voltage terminal (Vss);

marked by

• - A switching component ( 33 ) between the PMOS and the NMOS transistor to interrupt a leakage current as it would flow from the PMOS to the NMOS transistor.

2. Circuit according to claim 1, characterized in that the switching component ( 33 ) is a PMOS transistor, an NMOS transistor or another semiconductor component. 3. Circuit according to one of the preceding claims, characterized in that the threshold voltage of the switching component ( 33 ) is either higher or lower than the threshold lens voltage of the PMOS or NMOS transistor. 4. Circuit according to one of the preceding claims, since characterized in that one or more PMOS Transistors and one or more NMOS transistors each available. 5. A circuit according to claim 2, characterized in that the switching component ( 33 ) is switched on with the NMOS transistor in the active state and is switched off in the standby state. 6. Circuit for reducing the current in the standby state with:

• - A voltage supply connection (Vcc) and a ground voltage connection (Vss) as well
• - A plurality of logic circuit parts ( 31 , 31 a,...), Which have a plurality of PMOS transistors and a plurality of NMOS transistors between the voltage supply connection and the ground voltage connection;

marked by

• - A selection transistor ( 33 ) which is present in each of the logic circuit parts between the PMOS transistor (LPM1, LPM2,...) and the NMOS transistor (LNM1, LNM2,...) in order to provide a leakage current path from PMOS to interrupt NMOS transistor.

7. Circuit according to claim 6, characterized in that the selection transistor ( 33 ) is an NMOS or a PMOS transistor gate. 8. The circuit according to claim 7, characterized in that the selection transistor ( 33 ) either an NMOS transistor with a threshold voltage below that of the NMOS transistor (LNM1, LNM2,...) In the logic circuit part ( 31 , 31 a,.. .) or it is a PMOS transistor with a threshold voltage below the threshold voltage of the PMOS transistor (LPM1, LPM2,...) in the logic circuit part. 9. Circuit according to one of claims 6 to 8, characterized in that the logic circuit part ( 31 , 31 a,...) Contains any logic circuits, such as inverters, NAND-Gat ter and / or a NOR gate. 10. Circuit for reducing the current in the standby state with:

• - A voltage supply connection (Vcc) and a ground voltage connection (Vss) as well
• - Several logic circuit parts ( 61-1 , 61-2 , 61-3 , 61-4 , ... ), the several PMOS transistors (LPM1, LPM2, LPM3, LPM4, and several NMOS transistors (LNM1, LNM2, LNM3 , LNM4,...) Between the voltage supply connection and the ground voltage connection;

marked by

• - A selection transistor ( 33 ), which is present between the PMOS transistor (LPM1, LPM3,...) and the NMOS transistor (LNM1, LNM3,...) of each of the odd logic circuit parts of the several logic circuits by the Interrupt leakage current path from PMOS to NMOS transistor in standby mode.

11. The circuit according to claim 10, characterized in that the logic circuit part ( 61-1 , 61-2 , 61-3 , 61-4 , ... ) Contains any logic circuits, such as inverters, NAND-Gat ter and / or a NOR -Gate. 12. The circuit according to claim 10, characterized in that the selection transistor ( 30 ) is an NMOS or a PMOS transistor. 13. The circuit according to claim 12, characterized in that the selection transistor ( 33 ) has a threshold voltage below the threshold voltage of the NMOS transistor (LNM1, LNM2, LNM3, LNM4,...) And the PMOS transistor (LPM1, LPM2, LPM3, LPM4,...) In the logic circuit part. 14. Circuit according to claim 13, characterized in that the PMOS transistor (LPM1, LPM2, LPM3, LPM4,...) In the logic circuit part ( 61-1 , 61-2 , 61-3 , 61-4 , ... ) is formed in an n-well. 15. Circuit according to claim 14, characterized in that the PMOS transistor (LPM1, LPM2, LPM3, LPM4,. . .) a relative increase in the thresholds voltage by a preload on the n-tub in the ready experienced state of health. 16. Circuit according to claim 13, characterized in that the NMOS transistor (LNM1, LNM2, LNM3, LNM4,...) In the logic circuit part ( 61-1 , 61-2 , 61-3 , 61-4 , ... ) is formed in a p-tub. 17. Circuit according to claim 16, characterized in that the NMOS transistor (LNM1, LNM2, LNM3, LNM4,. . .) a relative increase in the thresholds tension by a pre-tension on the p-tub in the ready experienced state of health.