DE19844717A1 - Large scale integrated circuit (LSI) with external coupling electrode on chip - Google Patents

Abstract

The insulated electrode has at least one intermediate connection, formed on an active region and coupled to the insulated electrode and is insulated with respect to an internal electrode. There are numerous aerial pairs, each formed by the above mentioned insulated, outer coupling electrode. The numerous outer coupling electrodes are fitted in a planar manner and enclose a chip active region, with the insulated electrode so connected as to be directly above it.

Description

The present invention relates to an integrated circuit (hereinafter referred to as LSI (= Large-Scale Integrated) circuit draws) among semiconductor devices and in particular an LSI circuit which is designed such that the source le of their electromagnetic radiation noise (hereinafter only referred to as noise) or their interference radiation be easily specified at the internal element level can.

Increases in the degree of integration and the operating ge speed of an LSI circuit as a result of the micromu The internal elements of the LSI circuit are known remarkable. With increasing degree of integration and increasing Operating speed also increases the noise that is generated by the LSI circuit, and serious ones occur Problems on such. B. the operating error of the LSI itself and Malfunctions in the operation of peripheral devices caused by the noise. To these problems too must solve a section that acts as a source of noise in the LSI circuit that generates the noise can be specified and there must be countermeasures to reduce noise in or on this section can be done to re noise reduce that is generated by the LSI circuit. For this Purpose must be a method of measuring noise in the LSI circuit can be set up and the noise source in the LSI be specified.

Conventionally, as a method for specifying or determining of the noise source of an electronic device Method for scanning the top surface of a substrate  applied with an electromagnetic field sample to the Noise distribution at the substrate level to measure and demented speaking to determine the noise source. This shows more precisely Image 1 from "Denshi Gijutsu", August 1997, page 8, this measurement contraption. According to this procedure, a loop sample is made (electromagnetic field sample) over a target measurement substrate keyed to the distribution of a magnetic near field measure up. The loop sample is driven by a motor and can move in the directions of the X-axis and Y-axis to cover the entire surface of the target measurement substrate Keys.

With this measurement method, although it can be determined which LSI circuit generates the noise on the substrate, it is difficult to specify which element in the LSI circuit generates the noise due to the following problems:

• 1) The size of the electromagnetic field sample relative to that Size of the internal element in the LSI circuit is very large large and the noise generation distribution with a positi onbound resolution at the level of the internal element the LSI circuit cannot be measured.
• 2) Due to the size of the electromagnetic field sample, such as previously described, and also due to restrictions against the LSI package, the LSI measuring board and the like the electromagnetic field sample is not sufficiently fine be moved to the noise of the internal element of the LSI circuit to measure and therefore a Rauschver division measurement with a required position accuracy or position resolution are not carried out.

As just described, the measurement method for the LSI circuit that comes in a package or case is sealed from the outside using the conventional Chen electromagnetic field sample due to the size of the electromagnetic field test and the restrictions imposed by the LSI circuit pack, the LSI circuit evaluation board and the like, the noise source with positional accuracy or resolution at the level or in the order of magnitude internal elements of the LSI circuit are not accurate or high to be determined exactly.

The present invention has been made in view of the present invention the problems of the prior art and has therefore as a task to specify an LSI circuit in which the Noise source of the LSI circuit so easily specified countermeasures can be taken, including a scarf modification for the purpose of suppressing the LSI circuit generated noise can be done accurately.

This task is performed by the circuit or highly integrated LSI circuit according to claim 1, claim 2 or claim 3 solved. Accordingly, the task formulated above is according to a first aspect of the present Er Finding an LSI circuit provided a variety of external connection electrodes or connections on one Chip that has an insulated outer connection electrode, which is not an electrode used as a power supply Connection connection, as earth connection connection or as Signal connection is used, and at least one interconnection or connecting device having any shape has and is trained in an active area where in the interconnection with the isolated, outer Ver  Binding electrode is connected and opposite an internal Element is isolated.

According to a second aspect of the present invention provided an LSI circuit that a variety of Outer connection electrodes on a chip, the one Variety of antenna pairs, each with an iso gated, outer connection electrode, which is not an electrical de, which is the voltage supply connection Connection, reference potential, earth or ground connection connection or serves as a signal connection, and by a Zwi is formed which has any shape, connected to the insulated outer connection electrode and is isolated from an internal element.

According to a third aspect of the present invention provided an LSI circuit in which a variety of external connecting electrodes planar or level closing or enclosing an active region of a chip is arranged, wherein at least one of the outer connection electrodes is an isolated electrode and wherein a Zwi connection that has any shape and opposite an internal element is isolated, with the isolated, external Outer connection electrode is connected so that it un is indirectly below or below this.

The shape of the interconnect that connects with the outer connector in the first to third aspect of the present ing invention described above verbun that is, can be different or vary. E.g. can the interconnect a rectangular shape, a zigzag Shape have a spiral shape or a loop shape.  

In particular, an interconnection which is a zigzag Pattern or a spiral or helical pattern within a plane parallel to the LSI substrate, or ei ne interconnect, which is a loop shape in a rich vertical, normal or perpendicular to the LSI substrate ter use of different connection layers of the LSI circuit has the detection sensitivity of the magnet further improve the field.

As seen from the aspects described above goes, according to the present invention becomes an isolated one Interconnection with any shape in one LSI circuit installed or integrated from the outset. Then it will be an outer connecting electrode connected to this intermediate ver bond is connected to an outer electrode of the LSI circuit by bonding or a similar connection technology and this external connection is connected to a Noise measurement unit connected. When a noise measurement is complete leads, the position or location of the source of the Noise caused by the internal element of the LSI circuit generated, can be detected with high precision because of the intermediate connecting section, which has any shape, as an antenna serves or works.

As has been described, the LSI circuit of the present Invention the isolated interconnect that acts as an antenna serves, which detects the noise caused by the internal Element of the LSI circuit is generated, and the isolated, outer connecting electrode built in or inte with which only this interconnection is connected. If the measuring unit for the noise measurement with the external An conclusion is connected to the isolated outer electrical  de is connected, and the LSI circuit in usually in In operation, the noise caused by the LSI circuit is generated at this time or at this time point can be easily determined.

If the isolated interconnect, which serves as an antenna, which detects the noise described above, and the insulated outer connecting electrode, with which only this Zwi is connected in a suitable manner in About in tune with the function of those to be developed LSI circuit can be arranged, the noise source section highly precise easily at the level of the internal element of the LSI chips are specified and appropriate noise countermeasure can be carried out within the LSI circuit the.

In the LSI circuit according to the present invention the noise at the time of development or design the LSI circuit and the noise source section can be at the level or within the order of magnitude of tern levels or elements of the LSI chip determined or forth be found out. Therefore, suitable noise countermeasures took place and an LSI circuit that only generates little noise, can be developed quickly.

Further advantageous developments of the present invention can be found in subclaims 4 to 15.

Further advantages, advantageous further training and applications Possible uses of the present invention are according to following description of preferred embodiments of the  present invention in conjunction with the accompanying Take drawings. Show it:

Figure 1 is a schematic plan view of an LSI chip according to a first preferred embodiment of the present invention.

Figs. 2A to 2C examples of an interconnection pattern, which serves as an antenna, in which Fig. 2A is an example of a zig-zag pattern or a meander pattern is shown in Fig. 2B is an example of a spiral pattern is shown within a plane that is parallel to the LSI substrate and is shown in FIG. 2C an example in which a loop is formed in a direction normal to the LSI substrate using different interconnect layers of the LSI circuit;

Fig. 3 is a schematic sectional view that never runs along the Li III-III of Fig. 1;

FIG. 4 is a schematic block diagram showing a method of measuring electromagnetic radiation noise for the LSI circuit of the present invention;

Fig. 5 is a schematic plan view according to an LSI chip of a second preferred embodiment of the present invention; and

FIG. 6 is a schematic sectional view along the line VI-VI of FIG. 5.

Various preferred embodiments of the present Invention are described below with reference to the accompanying Described drawings.

In Fig. 1 is a plan view showing an LSI chip according ei ner first embodiment of the present invention ge. Antennas 12 , which have no circuit connections to their circuits, are arranged in an active region 15 of an LSI chip 11 and are connected to insulated external connection electrodes 13 , which are not external connection electrodes 16 , which, as conventional voltage supply connection connections, Ground or earth (GND) connection connections or signal connection connections. These antennas 12 are arranged in a plurality of sections on the LSI chip 11 in consideration of the arrangement of an outer member which is anticipated to act as a noise source, so that the position of the noise source in the LSI chip 11 can be speci ed.

As far as the arrangement of the antennas 12 is concerned, the antennas 12 are preferably arranged next to or in the vicinity of internal elements, e.g. B. a clock output buffer that have a high operating frequency Be and a large driver current or working current. Interconnections 14 are preferably made as short as possible since they are intended to detect the noise.

In Fig. 1, the antennas 12 are shown alone as rectangles ge. When an antenna 12 having a zigzag pattern within a plane parallel to the LSI substrate, an antenna 12 having a spiral pattern within a plane parallel to the LSI substrate or an antenna 12 are used , in which a loop is formed in a direction perpendicular to the substrate using different connection layers of the LSI substrate, as shown in FIGS . 2A, 2B and 2C, the effective magnetic field direction sensitivity can further be improved.

FIG. 3 is a schematic sectional view taken along the line III-III of FIG. 1. The antenna 12 or the detector or sensor is arranged directly above an element 31 , which is assumed or predicted to easily generate noise in the LSI chip 11 . The antenna 12 is isolated from the element 31 by an intermediate layer film 33 or insulator. The outer connec tion electrode 13 connected to the antenna 12 is also an insulated electrode. The antenna 12 has no circuit connection at all with other circuits of the LSI chip 11 with the exception of noise.

The function of the antennas 12 in an LSI circuit 42 , which has the antennas 12 on the LSI chip 11 , which was previously described, will be described below with reference to the schematic block diagram of FIG. 4, the method of measuring Shows noise of the LSI circuit according to the present invention.

First, the LSI circuit 42 is placed on a measuring board 41 . The antenna connections 43 , which are connected to the antennas 12 on the LSI chip 11 , are connected to a measuring device 44 , for. B. a spectral analyzer. If the noise generated by the LSI circuit 42 is ge ring, an amplifier 45 can be inserted between the antenna connections 43 and the measuring device 44 . With this circuit configuration, when the LSI circuit 42 is operating normally, the noise during this normal operation with the antennas 12 in the LSI circuit 42 is detected and measured with the measuring device 44 . The antenna connections 43 , which are assigned to the antennas 12, which are arranged or integrated on the LSI chip 11 , are selected sequentially by a switch box 46 in order to measure the noise. The level distribution or value distribution of the noise, which depends on the positions of the antennas 12 , can be checked and, accordingly, the noise source can be found on the LSI chip 11 . This noise measurement is made at the time the LSI circuit 42 is developed, and the presence or absence of noise at a level or value that is a problem is checked. If the noise is a problem, this is taken into account in the design of the LSI 42 so that the portion that creates the problem can be corrected. As a result, an LSI circuit that does not generate much noise can be quickly developed.

FIG. 5 shows a second embodiment of the present the invention. Fig. 5 is a schematic plan view of an LSI circuit, except that external connec tion electrodes 52 , z. B. flip-flops, an LSI chip 51 plan ar are arranged, which enclose or enclose an active region 55 of the LSI chip 51 , and that the LSI chip 51 has insulated, outer connection electrodes 53 .

FIG. 6 is a schematic sectional view taken along the line VI-VI of FIG. 5. In this case, the insulated outer connection electrode 53 , which has been described above, can practically be arranged next to, preferably immediately above, an element 61 , which is assumed to generate noise, and the antenna 12 , which is connected to the external connection electrode 53 is connected, can be disposed below this electrode un indirectly 53rd Then the outer connecting electrode 53 is directly connected to the antenna 12 through through holes 62 or through connections. An extra intermediate connection is not formed and a noise measurement with higher accuracy can be carried out. In this embodiment, the function of the antenna 12 is the same as in the embodiment shown in Fig. 1, and a detailed description of this function is therefore omitted here.

Claims (15)

1. LSI circuit with a variety of external connection electrodes on a chip that have an insulated outer connector voltage electrode that is not an electrode that acts as a voltage Supply connection connection, earth or earth Connection connection or serves as a signal connection, and too has at least one interconnect that is any Has shape and is formed on an active area, wherein the interconnection with the isolated outer connector is connected to an internal electrode Element is isolated. 2. LSI circuit with a variety of external connection electrodes on a chip that have a variety of antenna pairs ren, each by an isolated, external connection extension electrode, which is not an electrode that acts as a chip voltage supply connection terminal, as a ground or as Er de-connection connection or serves as a signal connection, and is formed by an interconnection, which is an arbitrary ge shape, with the insulated outer connecting electrode is connected and isolated from an internal element is. 3. LSI circuit in which a variety of external conn planar, an active area of a chip is arranged in which at least one of the outer Connecting electrodes is an insulated electrode and wherein an interconnect that has any shape and ge is isolated from an internal element, with the isolier th outer connecting electrode connected such that they is immediately below.   4. LSI circuit according to claim 1, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, a zigzag pattern within a plane parallel to one LSI circuit substrate forms. 5. LSI circuit according to claim 2, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, a zigzag pattern within a plane parallel to one LSI circuit substrate forms. 6. LSI circuit according to claim 3, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, a zigzag pattern within a plane parallel to one LSI circuit substrate forms. 7. LSI circuit according to claim 1, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, forms a spiral pattern within a plane that is in parallel with an LSI circuit substrate. 8. LSI circuit according to claim 2, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, forms a spiral pattern within a plane that is in parallel with an LSI circuit substrate.   9. LSI circuit according to claim 3, characterized in that the interconnect, which has the arbitrary shape and with the insulated outer connection electrode is connected, forms a spiral pattern within a plane that is in parallel with an LSI circuit substrate. 10. LSI circuit according to claim 1, characterized in that the interconnect, which has any shape and connected to the insulated outer connection electrode is a loop in a direction perpendicular to one LSI circuit substrate using different Zwi Interconnect layers of the LSI circuit forms. 11. LSI circuit according to claim 2, characterized in that that the interconnect, which has any shape and connected to the insulated outer connection electrode is a loop in a direction perpendicular to one LSI circuit substrate using different Zwi Interconnect layers of the LSI circuit forms. 12. LSI circuit according to claim 3, characterized in that the interconnect, which has any shape and connected to the insulated outer connection electrode is a loop in a direction perpendicular to one LSI circuit substrate using different Zwi Interconnect layers of the LSI circuit forms. 13. LSI circuit according to claim 1, characterized in that that the interconnect, which has any shape and connected to the insulated outer connection electrode is near an internal element, e.g. B. a clock  gang buffer, which has a high operating frequency and a large Has drive current is arranged. 14. LSI circuit according to claim 2, characterized in that that the antenna pair, which has the arbitrary shape and with the insulated, outer connecting electrode is connected, in close to an internal element, e.g. B. a clock output puff fer, which has a high operating frequency and a large An drive current has been arranged. 15. LSI circuit according to claim 3, characterized in that the interconnect, which has any shape and connected to the insulated outer connection electrode is near an internal element, e.g. B. a clock gang buffer that has a high operating frequency and a large one Has drive current is arranged.