DE19815906A1 - Encapsulated power semiconductor device - Google Patents
Encapsulated power semiconductor deviceInfo
- Publication number
- DE19815906A1 DE19815906A1 DE19815906A DE19815906A DE19815906A1 DE 19815906 A1 DE19815906 A1 DE 19815906A1 DE 19815906 A DE19815906 A DE 19815906A DE 19815906 A DE19815906 A DE 19815906A DE 19815906 A1 DE19815906 A1 DE 19815906A1
- Authority
- DE
- Germany
- Prior art keywords
- chip
- leadframe
- component
- lead frame
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 9
- 238000000465 moulding Methods 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Die Erfindung betrifft ein Bauelement, das einen Chip (2) auf einem Leadframe (1) mit mehreren Leads (4) umfaßt, wobei der Chip (2) mit einem oder mehreren Bonddrähten (3a, 3b) mit einzelnen der Leads (4) verbunden ist. DOLLAR A Um in dem Bauelement eine größere Oberfläche für Halbleiterchips zur Verfügung zu stellen, wird das gattungsgemäße Gehäuse erfindungsgemäß so weitergebildet, daß sowohl auf einer ersten (7) als auch auf einer zweiten Oberfläche (8) des Leadframes (1) jeweils mindestens ein Chip (9, 10) angeordnet ist.The invention relates to a component comprising a chip (2) on a leadframe (1) with a plurality of leads (4), the chip (2) being connected to one of the leads (4) with one or more bonding wires (3a, 3b) is. DOLLAR A In order to provide a larger surface for semiconductor chips in the component, the generic housing is further developed according to the invention in such a way that at least one chip in each case on a first (7) and on a second surface (8) of the lead frame (1) (9, 10) is arranged.
Description
Die Erfindung betrifft ein Bauelement, das einen Chip auf ei nem Leadframe mit mehreren Leads umfaßt, wobei der Chip mit einem oder mehreren Bonddrähten mit einzelnen der Leads ver bunden ist.The invention relates to a component that has a chip on egg nem lead frame with several leads, the chip with one or more bond wires with individual leads is bound.
Bauelemente der genannten Art sind z. B. in ein TO220-Gehäuse eingebaute Leistungshalbleiter. Bei diesem Gehäuse wird ein Halbleiter-Chip mit auf einem "Leadframe" aufgelötet bzw. aufgeklebt. Das Leadframe besteht aus mehreren "Leads", die einerseits als elektrischer Anschluß des Chips nach außen dienen und andererseits als mechanische Halterung für den Chip dienen. Die Leads des Leadframes bestehen aus Cu oder Cu-Legierungen. Nach dem Befestigen des Chips auf dem Lead frame werden ein oder mehrere Drähte (Al, Cu oder Au etc.) auf Kontaktflächen auf dem Chip, d. h. auf die Chippad's und die entsprechenden Leads des Leadframes gebondet.Components of the type mentioned are z. B. in a TO220 housing built-in power semiconductors. In this case, a Semiconductor chip with soldered on a "lead frame" or glued. The leadframe consists of several "leads" that on the one hand as an electrical connection of the chip to the outside serve and on the other hand as a mechanical holder for the Serve chip. The leads of the leadframe consist of Cu or Cu alloys. After attaching the chip to the lead frame one or more wires (Al, Cu or Au etc.) on contact areas on the chip, d. H. on the Chippad's and the corresponding leads of the lead frame are bonded.
Ein Bauelement in einem TO220-Gehäuse ist in Fig. 2 im Quer schnitt dargestellt. Das Leadframe ist mit 1 bezeichnet. Es umfaßt mehrere Leads 4, die voneinander isoliert sind. Auf dem Leadframe 1 ist ein Chip 2 angeordnet. Der Chip 2 ist mit Bonddrähten 3a mit einzelnen der Leads 4 verbunden, die den elektrischen Anschluß des Chips 2 nach außen darstellen. Zum Schutz des Chips 2 und der feinen Bonddrähte 3a wird am Ende des Herstellungsprozesses des Bauelements der Aufbau aus Leadframe 1, Chip 2 und Bonddrähten 3a in einer Preßmasse 5 umhüllt.A component in a TO220 housing is shown in cross section in Fig. 2. The lead frame is labeled 1 . It comprises several leads 4 which are isolated from one another. A chip 2 is arranged on the leadframe 1 . The chip 2 is connected with bond wires 3 a to individual leads 4 , which represent the electrical connection of the chip 2 to the outside. To protect the chip 2 and the fine bond wires 3 a, at the end of the manufacturing process of the component, the structure of leadframe 1 , chip 2 and bond wires 3 a is encased in a molding compound 5 .
Das Leadframe 1 dient neben der elektrischen Verbindung des Chips 2 nach außen und der mechanischen Stabilisierung des Aufbaus außerdem auch als Wärmesenke, in die die von dem Chip 2 erzeugte Wärme abfließt. Daher ist das Leadframe 1 mit ei nem Kühlkörperfortsatz 11 versehen, mit dem eine Befestigung des Leadframes 1 auf einem größeren Kühlkörper möglich ist. Die Befestigung kann mittels Verschraubung oder Anklemmen er folgen. Zur Vergrößerung der wärmeabstrahlenden Oberfläche und zu Befestigungszwecken ist in dem Kühlkörperfortsatz 11 eine Bohrung 6 vorgesehen.In addition to the electrical connection of the chip 2 to the outside and the mechanical stabilization of the structure, the lead frame 1 also serves as a heat sink into which the heat generated by the chip 2 flows. Therefore, the leadframe 1 is provided with a heat sink extension 11 with which the leadframe 1 can be fastened to a larger heat sink. The attachment can be followed by screwing or clamping. A bore 6 is provided in the heat sink extension 11 to enlarge the heat-radiating surface and for fastening purposes.
Die maximale Chipgröße des Chips 2 ist damit einerseits durch die Größe des "heatsink" des Leadframes 1 bestimmt. Als Grundfläche für den Chip 2 kann aber andererseits auch deswe gen nicht die gesamte Oberfläche des Leadframes 1 ausgenutzt werden, weil noch Metalloberfläche z. B. für die Haftung der Preßmasse benötigt wird. Wird diese Oberfläche für die Haf tung der Preßmasse auf dem Leadframe zu klein gewählt, so be steht die Gefahr, daß sich die Preßmasse von dem Leadframe löst und das Gehäuse zerstört wird. In einem Gehäuse vom Typ TO220 z. B. haben Chips daher nur bis zu einer maximalen Grö ße von etwa 25mm2 Platz.The maximum chip size of the chip 2 is thus determined on the one hand by the size of the "heatsink" of the lead frame 1 . As a base for the chip 2 , however, the entire surface of the leadframe 1 cannot be used because the metal surface is still z. B. is required for the adhesion of the molding compound. If this surface is chosen too small for the adhesion of the molding compound on the lead frame, there is a risk that the molding compound will detach from the lead frame and the housing will be destroyed. In a TO220 housing, e.g. B. chips have therefore only up to a maximum size of about 25mm 2 space.
Die Einschränkung der in dem Bauelement verfügbaren Fläche für Chips ist nachteilig und verhindert den Einsatz von Halb leiter-Chips mit größerer Oberfläche für höhere Leistungen oder mit zusätzlichen Funktionen.The limitation of the area available in the component for chips is disadvantageous and prevents the use of half conductor chips with a larger surface for higher performance or with additional functions.
Es ist die Aufgabe der vorliegenden Erfindung, das gattungs gemäße Bauelement so weiterzubilden, daß in dem Bauelement eine größere Oberfläche für Halbleiter-Chips zur Verfügung steht.It is the object of the present invention, the genus according to the component so that in the component a larger surface area for semiconductor chips is available stands.
Die Aufgabe wird erfindungsgemäß gelöst durch ein Bauelement mit den Merkmalen nach Anspruch 1. Bevorzugte Ausführungsfor men des erfindungsgemäßen Bauelements sind Gegenstand der Un teransprüche.The object is achieved according to the invention by a component with the features of claim 1. Preferred embodiment Men of the component according to the invention are the subject of the Un claims.
Die Lösung beruht im wesentlichen darauf, daß nicht nur eine Seite des Leadframes für die Chips verwendet wird, sondern auch die zweite Seite. Durch die Ausnutzung beider Seiten des Leadframes wird einerseits an sich bereits eine Verdopplung der zur Verfügung stehenden Oberfläche erreicht. Andererseits ergibt sich aus der erforderlichen beidseitigen Umpressung des Leadframes mit den Chips, daß die für die Haftung der Preßmasse auf dem Metall des Leadframes erforderliche Ober fläche auf dem Leadframe reduziert werden kann. Mit anderen Worten, die auf einer Seite des Leadframes zur Verfügung ste hende Oberfläche kann zu einem höheren Grad ausgenutzt werden als beim Stand der Technik.The solution is essentially based on the fact that not only one Side of the lead frame is used for the chips but also the second page. By using both sides of the On the one hand, leadframes are already doubling the available surface. On the other hand results from the required double-sided extrusion of the leadframe with the chips that are responsible for the liability of the Molding compound on the metal of the leadframe required upper area on the leadframe can be reduced. With others Words available on one side of the leadframe The surface can be used to a higher degree than in the prior art.
Bei dem gattungsgemäßen Bauelement wird erfindungsgemäß so wohl auf einer ersten als auch auf einer zweiten Oberfläche des Leadframes jeweils mindestens ein Chip angeordnet.In the generic component is according to the invention probably on a first as well as on a second surface of the leadframe each arranged at least one chip.
Dabei können bei dem erfindungsgemäßen Bauelement mehrere Chips auf jeweils einer Oberfläche des Leadframes angeordnet werden. Dadurch kann das Bauelement für mehrere unterschied liche Funktionen ausgelegt werden und an verschiedene Anfor derungen angepaßt werden.In this case, several can be used in the component according to the invention Chips arranged on one surface of the leadframe become. This allows the component to differ for several functions are designed and adapted to different requirements changes are adjusted.
Der Vorteil des Bauelements liegt darin, daß die Montageflä che für Halbleiter-Chips verdoppelt wird. Außerdem ist bei Bauelementen mit symmetrisch umpreßten Gehäusen eine Umstel lung der Werkzeuge für die Montage der Bauelemente für die Weiterverarbeitung nicht erforderlich.The advantage of the component is that the assembly area surface for semiconductor chips is doubled. In addition, at Components with symmetrically molded housings a change development of the tools for the assembly of the components for the No further processing is necessary.
Weitere Merkmale und Vorteile der Erfindung ergeben sich aus der nachfolgenden Beschreibung eines Ausführungsbeispiels, bei der Bezug genommen wird auf die beigefügten Zeichnungen.Further features and advantages of the invention result from the following description of an exemplary embodiment, reference is made to the accompanying drawings.
Fig. 1 zeigt eine Ausführungsform des erfindungsgemäßen Bau elements im Querschnitt. Fig. 1 shows an embodiment of the construction element according to the invention in cross section.
Fig. 2 zeigt das bereits beschriebene Bauelement in einem Aufbau nach dem Stand der Technik im Querschnitt. Fig. 2 shows the component already described in a structure according to the prior art in cross section.
In Fig. 1 ist eine Ausführungsform des erfindungsgemäßen Bau elements dargestellt. Gleiche Komponenten in der Darstellung in Fig. 1 wie in der Darstellung in Fig. 2 sind mit den glei chen Bezugszeichen versehen.In Fig. 1 an embodiment of the construction element according to the invention is shown. The same components in the illustration in Fig. 1 as in the illustration in Fig. 2 are provided with the same reference numerals.
Das erfindungsgemäße Bauelement nach Fig. 1 unterscheidet sich von dem Bauelement nach dem Stand der Technik in Fig. 2 dadurch, daß sich auf der oberen Seite und der unteren Seite in der Figur jeweils ein Chip 9 und 10 befindet. Mit anderen Worten, durch die Anordnung von Halbleiter-Chips sowohl auf einer ersten Oberfläche 7 des Leadframes 1 als auch auf einer zweiten Oberfläche 8 des Leadframes 1 wird die für die Posi tionierung von Halbleiter-Chips verfügbare Fläche des Lead frames 1 verdoppelt. Es können statt nur eines Chips 2 auf dem Leadframe 1 zwei Chips 9 und 10 angeordnet werden.The component according to the invention according to FIG. 1 differs from the component according to the prior art in FIG. 2 in that a chip 9 and 10 is located on the upper side and the lower side in the figure. In other words, by the arrangement of the semiconductor chip, both on a first surface 7 of the lead frame 1 and on a second surface 8 of the lead frame 1, for posi tioning of semiconductor chips available area of the lead is frames 1 doubled. Instead of just one chip 2, two chips 9 and 10 can be arranged on the leadframe 1 .
Der Chip 9 auf der Oberseite des Leadframes 1 in Fig. 1 wird wie beim Stand der Technik über Bonddrähte 3a je nach Ver drahtungs- und Anschlußplan des Bauelements mit einigen der Leads 4 verbunden. Der Chip 10 auf der Unterseite des Lead frames 1 in Fig. 1 wird über Bonddrähte 3b je nach Funktion des Chips mit den entsprechenden Leads 4 verbunden. Die Rei henfolge des Bondens, also ob erst der obere Chip 9 und dann der untere Chip 10 verdrahtet wird oder umgekehrt, hängt von dem Montageverfahren der Chips bei der Herstellung des Bau elements ab.The chip 9 on the top of the lead frame 1 in Fig. 1 is connected to some of the leads 4 as in the prior art via bond wires 3 a depending on the wiring and connection diagram of the component. The chip 10 on the underside of the lead frame 1 in FIG. 1 is connected to the corresponding leads 4 via bond wires 3 b, depending on the function of the chip. The order of the bonding, that is, whether only the upper chip 9 and then the lower chip 10 are wired or vice versa, depends on the assembly method of the chips in the manufacture of the component.
Der Einbau der Halbleiter-Chips 9 und 10 in das Gehäuse des erfindungsgemäßen Bauelements erfordert gegenüber den Stand der Technik keine wesentliche Modifikation des Herstellungs verfahrens. Es kann z. B. eine Seite komplett montiert werden, d. h. der Chip 9 auf dem Leadframe 1 positioniert werden und gegebenenfalls das Drahtbonden bereits durchgeführt werden, und anschließend kann das gleiche Verfahren auf der Rückseite durchgeführt werden - wobei das Lot auf der Vorderseite 7 u. U. nochmals aufgeschmolzen wird. Die Chips 9 und 10 werden beim Aufschmelzen des Lots jedoch durch die Oberflächenspan nung festgehalten. Auch beim Umdrehen des Leadframes, um nach dem ersten Chip 9 den zweiten Chip 10 auf den Leadframe 1 zu positionieren, kann damit der erste Chip 9 nicht verrutschen oder herunterfallen, wobei davon ausgegangen wurde, daß sich der erste Chip 9 sich beim Löten des zweiten Chips 10 auf der Unterseite des Leadframes befindet. Beim Kleben der Chips 9 und 10 tritt das Problem der Haftung der Chips auf dem Lead frame ohnehin nicht auf.The installation of the semiconductor chips 9 and 10 in the housing of the component according to the invention requires no significant modification of the manufacturing process compared to the prior art. It can e.g. B. one side can be completely assembled, ie the chip 9 can be positioned on the leadframe 1 and, if necessary, the wire bonding has already been carried out, and then the same method can be carried out on the rear side - the solder on the front side 7 and. U. is melted again. The chips 9 and 10 are held in place by the surface tension when the solder is melted. Even when the leadframe is turned over in order to position the second chip 10 on the leadframe 1 after the first chip 9 , the first chip 9 cannot slip or fall off, it being assumed that the first chip 9 will become detached when the second one is soldered Chips 10 is located on the underside of the lead frame. When the chips 9 and 10 are glued, the problem of the chips adhering to the lead frame does not occur anyway.
Die Reihenfolge der Montage (Löten, Kleben) der beiden Chips 9 und 10 und des Bondens der Drähte 3a und 3b ist beliebig und stellt keine Einschränkung bei der Herstellung des erfin dungsgemäßen Bauelements dar. Dem Fachmann sind darüber hin aus mögliche Abänderungen des Herstellungsverfahrens für Bau elemente mit dem gattungsgemäßen Aufbau zur Verbesserung beim "Clamping" der Kontaktflächen und beim Drahtbonden der Leads 4 bekannt, die daher hier nicht weiter erläutert zu werden brauchen.The order of assembly (soldering, gluing) of the two chips 9 and 10 and the bonding of the wires 3 a and 3 b is arbitrary and does not constitute any restriction in the manufacture of the component according to the invention. The person skilled in the art is also aware of possible changes in the manufacturing process known for construction elements with the generic structure to improve the "clamping" of the contact surfaces and wire bonding of the leads 4 , which therefore need not be explained here.
Nach dem Umpressen des Leadframes 1 mit den darauf montierten Chips 9 und 10, das nach dem Vorbild des Fullpack erfolgt, ist eine geringe Wärmeabfuhr der von einem oder beiden der Chips 9 und 10 erzeugten Wärme wie im Standardgehäuse nach dem Stand der Technik möglich. Wegen der höheren zur Verfü gung stehenden Chipfläche beim erfindungsgemäßen Bauelement gegenüber dem Bauelement nach den Stand der Technik ist für alle Anwendungen mit hohem Strom, die keine zusätzliche Küh lung brauchen, das erfindungsgemäße Bauelement aber sehr gut einsetzbar. Dabei sind Bauelemente, die keine zusätzliche Kühlung benötigen, z. B. Bauelemente mit kleinem Einschaltwi derstand.After pressing the leadframe 1 with the chips 9 and 10 mounted thereon, which is modeled on the full pack, a slight heat dissipation of the heat generated by one or both of the chips 9 and 10 is possible, as in the standard housing according to the prior art. Because of the higher available chip area in the component according to the invention compared to the component according to the prior art, for all applications with high current that do not require additional cooling, the component according to the invention can be used very well. Components that do not require additional cooling, for. B. components with small Einschaltwi resistance.
Auch symmetrisch umpreßte Gehäuse, z. B. PDSO, brauchen für die hier beschriebene Anwendung nicht geändert zu werden; der Kunde, der kundenspezifische Chips 9 und 10 auf dem Leadframe 1 anbringt, braucht sein Montageequipment für die Anordnung der Chips auf dem Leadframe 1 also nicht umzustellen. Also symmetrically molded housing, e.g. B. PDSO, need not be changed for the application described here; the customer who attaches the customer-specific chips 9 and 10 to the leadframe 1 does not have to change his assembly equipment for the arrangement of the chips on the leadframe 1 .
In der Beschreibung wurde jeweils ein Chip 9 und 10 auf jeder der Oberflächen des Leadframes 1 erläutert. Es können jedoch selbstverständlich auch mehrere Chips auf jeder Oberfläche angeordnet werden. Dadurch läßt sich das erfindungsgemäße Bauelement an spezielle Anforderungen anpassen. In the description, a chip 9 and 10 was explained on each of the surfaces of the lead frame 1 . However, several chips can of course also be arranged on each surface. As a result, the component according to the invention can be adapted to special requirements.
11
Leadframe
Leadframe
22nd
Chip
chip
33rd
a Bonddraht oben
a bond wire above
33rd
b Bonddraht unten
b Bond wire below
44th
Lead/Draht
Lead / wire
55
Preßmasse
Molding compound
66
Bohrung
drilling
77
erste Oberfläche des Leadframes
first surface of the leadframe
88th
zweite Oberfläche des Leadframes
second surface of the leadframe
99
erster Chip
first chip
1010th
zweiter Chip
second chip
1111
Kühlkörperfortsatz
Heat sink extension
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19815906A DE19815906A1 (en) | 1998-04-08 | 1998-04-08 | Encapsulated power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19815906A DE19815906A1 (en) | 1998-04-08 | 1998-04-08 | Encapsulated power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE19815906A1 true DE19815906A1 (en) | 1999-10-14 |
Family
ID=7864086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19815906A Withdrawn DE19815906A1 (en) | 1998-04-08 | 1998-04-08 | Encapsulated power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE19815906A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10315532A1 (en) * | 2003-04-04 | 2004-11-11 | Infineon Technologies Ag | Current sensing integrated circuit has two magnetic field sensor chips arranged on opposing sides of framework and an evaluation unit all contained within sensor housing |
| US20120081109A1 (en) * | 2010-09-30 | 2012-04-05 | Infineon Technologies Ag | Hall sensor arrangement for the redundant measurement of a magnetic field |
| US9368434B2 (en) | 2013-11-27 | 2016-06-14 | Infineon Technologies Ag | Electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996013855A1 (en) * | 1994-10-27 | 1996-05-09 | National Semiconductor Corporation | A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die |
| US5640044A (en) * | 1994-04-15 | 1997-06-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing said semiconductor device |
-
1998
- 1998-04-08 DE DE19815906A patent/DE19815906A1/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640044A (en) * | 1994-04-15 | 1997-06-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing said semiconductor device |
| WO1996013855A1 (en) * | 1994-10-27 | 1996-05-09 | National Semiconductor Corporation | A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10315532A1 (en) * | 2003-04-04 | 2004-11-11 | Infineon Technologies Ag | Current sensing integrated circuit has two magnetic field sensor chips arranged on opposing sides of framework and an evaluation unit all contained within sensor housing |
| DE10315532B4 (en) * | 2003-04-04 | 2014-08-14 | Infineon Technologies Ag | Integrated-type current sensor device and method of manufacturing |
| US20120081109A1 (en) * | 2010-09-30 | 2012-04-05 | Infineon Technologies Ag | Hall sensor arrangement for the redundant measurement of a magnetic field |
| DE102010047128A1 (en) | 2010-09-30 | 2012-04-05 | Infineon Technologies Ag | Hall sensor arrangement for redundantly measuring a magnetic field |
| US9151809B2 (en) | 2010-09-30 | 2015-10-06 | Infineon Technologies Ag | Hall sensor arrangement for the redundant measurement of a magnetic field |
| US9368434B2 (en) | 2013-11-27 | 2016-06-14 | Infineon Technologies Ag | Electronic component |
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