DE19731634A1 - Apparatus and method for finding an interrupt request associated with a source - Google Patents

Abstract

The invention concerns a device and a process for the locating of an interrupt request (interrupt) allocated to a source from a multitude of possible sources, several of which in each case are combined into a group, with a software (SW) for locating the wanted interrupt within a group and for the subsequent execution of a routine provided for the source allocated to the wanted interrupt in the case of an interrupt and with a hardware facility (HW) having an identification facility (A) which, in the case of an interrupt request provides the software (SW) with an address vector identifying the group. In order to enable a preferential reaction to interrupt requests of high priority and simultaneously ensure rapid reaction to an interrupt request, the sources of interrupt requests are combined into groups in the hardware device by means of interrupt group registers, one of at least two different priorities are allocated to each group and the hardware facility (HW) is provided with a separate identification facility (A) for each priority provided.

Description

The invention relates to an apparatus and a method to find a source assigned Interrupt request from a variety possible sources with a hardware device (HW) an interrupt group register for Includes interrupt requests, in each several sources are grouped together, and with a software (SW) to localize the searched Interrupts within its group and to the subsequent one Processing one for the interrupt you are looking for assigned source in the event of an interruption provided routine.

Events in hardware that respond quickly The software that are required are usually about Interruption requests to the software reported. The software then interrupts its normal process, to that of a particular source Corresponding interrupt request To be able to carry out processing routines. First of all however, the software for this is the source of the Localize the interrupt request. With growing Hardware complexity is an increasing number of possible sources for interrupt requests in one Hardware setup included and more and more independent Hardware devices are in a system or on one Circuit board arranged. Often these facilities are managed by  a single processor with limited performance and a limited number of lines for the Interrupt requests serviced. For this reason needs a simple device to locate the Origin of an interrupt request is available be put.

Devices and methods for locating the source of an interrupt request in hardware devices are known from practice. Such devices provide that several possible sources of an interrupt request are combined in groups in a hardware device, the number of possible sources which can be checked by the software with a single access usually being combined in each case. So z. B. eight possible sources can be checked with a 1-byte read access. If there is still a large number of these groups after this summary, further hierarchy levels are formed, in which several groups are combined to form new groups ( FIG. 1) . The groups are generally combined until the software can be accessed with a single access can access all groups at the highest hierarchical level. Accordingly, the more possible levels for interrupt requests, the more hierarchical levels are required. When an interrupt request is reported, the software must trace the path of the request through all levels of the hierarchy to locate the source of the interrupt request. For each additional hierarchy level, additional hardware access and the completion of an evaluation process in the software to determine the next group in the subordinate level, which must be read, are necessary.

A disadvantage of this device is therefore that in a hardware facility with a large number of possible sources for interrupt requests Very long time to find a requesting source is because the time needed to source a To locate interrupt request by number depends on the hierarchy levels that the software must go through. If some of the Interruption requests can occur frequently, so this is the software to an unacceptable extent slow it down.

Accordingly, it is an object of the invention to provide a device or to create a process, the one find the sources of Allows interrupt requests.

This object is achieved with a device for detection an interrupt request associated with a source from a variety of possible sources in one Hardware device according to the invention solved in that the hardware device (HW) one Identification device (A) contains the inputs are assigned to all groups, with the Identification device determines in which group there is an interrupt request and its Output on of the interrupt request containing group corresponding address vector the software passes on that the address vector as Assignment vector for the software for locating the Group containing interrupt request is used.

The advantage of the solution according to the invention is that that the identification device is a continuous Review of individual groups with high Can perform speed and that the software with  the information of the identification device Group from which the interrupt request comes already clearly identify and thereby one Interrupt request usually after two Accesses (reading out the address vector and checking the Register in the affected group) on the hardware can locate. For hardware with a large one Number of possible sources for one This device claims interrupt request thereby significantly less processor power and is much faster than devices so far be used.

In a preferred embodiment of the invention next to the identification unit Notification unit provided with all Groups is linked, and their output one Outputs logic information to the software when on an interrupt request to at least one group is present, such that when setting the logic information the current value of the address vector of Identification device can be adopted by the software is.

Furthermore, another are preferred Embodiment of the invention the groups one each assigned by at least two different priorities, with a separate query device for each priority is available and interrupt requests Groups with higher priority preferred to the software be passed on. By assigning the groups to various priorities are also ensured that the software is usually the first Highest priority interrupt request processed.  

Further preferred embodiments of the invention go from the subclaims.

The invention is based on the Drawings containing exemplary embodiments closer explained. Show:

Fig. 1 is a group in hierarchical levels for a device according to the prior art,

Fig. 2 shows a first embodiment according to the invention,

Fig. 3 shows a second embodiment according to the invention,

Fig. 4 shows a third embodiment according to the invention, and

Fig. 5 shows a fourth embodiment according to the invention with different priorities.

The principle of the device according to the invention is clear from FIG . All states for interrupt requests stored in an interrupt group register are linked via an OR gate (OR1-ORX). The outputs of the OR gates (OR1-ORX) are connected to an identification device (A) which is connected to the software (SW) via an output. For example, if the number of interrupt sources combined in a group is up to eight, all interrupt sources in a group can be accessed with a 1-byte read access.

In the event of an interrupt request, the value of the requesting interrupts assigned from "0" "1" set. After linking the outputs one  Interrupt group registers through the OR gates (OR1-ORX) is at the output of the interrupt, the one Interruption requests belonging to the OR gate also issued a "1".

The identification device (A) checks sequentially and continuously the outputs of the OR gates (OR1-ORX) then whether an interruption from one of the groups is requested (for example with the clock frequency of the Microprocessor). As long as this is not the case, points he uniquely identifies the group queried Address vector and continues with the next group. However, if an interrupt request occurs, the current address vector for the software for reading out made available. The query mechanism can be interrupted here.

The software then reads the address vector with which it can clearly identify the group in question and searches for the relevant one within this group Interrupt. The interrupt source that is an interrupt can be requested by the software with only two Hardware accesses can be localized. If the The query mechanism has been interrupted, the Hardware (HW) after reading out the address vector the software (SW) automatically checking the Groups continue while the software is interrupting processed.

Fig. 3 shows a further embodiment of the invention, which corresponds to the example in Fig. 2, but which also contains a notification block (B). Again, all states for interrupt requests stored in an interrupt group register are linked via an OR gate (OR1-ORX). The outputs of the OR gates (OR1-ORX) are connected on the one hand to the notification device (B), which in turn is connected to the software (SW). On the other hand, the outputs of the OR gates (OR1-ORX) are connected to the identification device (A), which is also connected to the software (SW).

In the event of an interrupt request, the value of the requesting interrupt assigned interrupt from "0" "1" set. After linking the outputs one Interrupt group registers through the OR gates (OR1-ORX) is at the output of the interrupt, the one Interruption requests belonging to the OR gate also issued a "1".

The identification device (A) checks sequentially and continuously the outputs of the OR gates (OR1-ORX) then whether an interruption from one of the groups is requested (for example with the clock frequency of the Microprocessor). As long as this is not the case, points he uniquely identifies the group queried Address vector and continues with the next group. However, if an interrupt request occurs, the current address vector for the software for reading out made available.

Is one at the output of one of the OR gates (OR1-ORX) "1" for an interrupt request, reports the Notification block (B) of the software (SW) that a There is an interrupt request and an address vector can be read out from the identification device (A) got to.

The software then reads the address vector with which it can clearly identify the group in question and searches for the relevant one within this group Interrupt. The interrupt source that is an interrupt  can be requested by the software with only two Hardware accesses can be localized.

In FIG. 4 a further preferred embodiment of the invention is illustrated. All states for interrupt requests stored in an interrupt group register are linked via an OR gate (OR1-ORX).

The outputs of all X OR gates (OR1-ORX) become one linked with another OR gate (G1). Of the The output of this OR gate (G1) is via an input an AND gate (G2) connected to a flip-flop (F), whose output connects to the (not shown) Software delivers, for example with the Clock frequency of the microprocessor is clocked (up clk).

On the other hand, the X outputs of the OR gates (OR1-ORX) with the X inputs of a multiplexer (M1) connected. The output signal of the multiplexer (M1) on the one hand supplies one of the input signals another OR gate (G3), the output of which is the second Provides input for the AND gate (G2). On the other hand, the output signal of the multiplexer provides (M1) an input signal of a counter (Z) which for example, also with the clock frequency of Microprocessor is clocked (up clk). The exit of the Counter (Z) is via another multiplexer (M2) also connected to the software. At the second entrance of the multiplexer (M2) there is an "idle" value. This "idle" value should be a value that is otherwise not can be issued, e.g. B. the maximum counter value or another value above the counter's reset value. The output signal of the first multiplexer (M1) delivers additionally a control signal to the second multiplexer (M2). The counter (Z) has another input, the  is directly connected to the software. The output signal the counter (Z) also provides a control vector for the first multiplexer (M1).

The second input signal for the OR gate (G3) is from the output signal of the flip-flop (F).

The mode of operation of the described embodiment of the invention according to FIG. 4 is explained below:

First, a situation without Hardware interrupt request considered. On all outputs of the interrupt group registers a "0" is output to the OR gates (OR1-ORX). The outputs of all OR gates are correspondingly (OR1-ORX) "0". Linking the outputs of the OR gates (OR1-ORX) with the OR gate (G1) leads to one another signal "0", which via the AND gate and the Flip flop is output to the software. Here means a signal from "0" to the software that none Interruption request is pending and the software is normal can continue to work.

The output signals "0" of the OR gates (OR1-ORX) lie also at the inputs of the multiplexer (M1). This multiplexes the signals one after the other and outputs the "0" to the OR gate (G3) and to the counter (Z) further. As long as the counter receives a "0", it counts with every cycle (up clk) the counter reading from zero to X um one up. As soon as the value "X" is reached, a Reset carried out and the counter starts again at zero on. This means that every time a group is checked clear counter reading available. The current Counter value is sent to the second multiplexer (M2) passed on. However, since the second multiplexer (M2) is a Receives control signal of "0" from the first multiplexer (M1),  the counter value of the software is not available but the "idle" value, which is at the second input of the multiplexer (M2). The baseline of the Counter also provides the information to the first Multiplexer (M1), which input signal next should be let through.

The output signal of the OR gate (G3) is "0" because both input signals - the output signal of the first Multiplexer (M1) and the output signal of the flip-flop (F) - provide a "0". The input signal for the Flip-flop (F) is therefore also "0" because of both Inputs of the AND gate (G2), which is the output signal the input signal of the flip-flop delivers a "0" is present.

Next, a situation will be described in which there is at least one interrupt request. At the Output from at least one of the OR gates (OR1-ORX) a "1" is output. That leads to that too the output of the OR gate (G1) with which the OR gate (OR1-ORX) are linked, a "1" to one Input of the AND gate delivers.

The multiplexer (M1) continues to give the successively Values supplied by the OR gates (OR1-ORX) be forwarded to the counter (Z), the output of the Counter (Z) a control signal to the multiplexer (M1) returns which group signal is passed on next becomes. The counter counts the counter value for each cycle one high as long as it has a "0" at the "disable" input receives. However, it receives a "1" as one of them Multiplexer (M1) forwarded group signal, so has the multiplexer (M1) locates the requesting group and the counter (Z) stops until it gets one from the software Count-up pulse for further counting (+1) received. Of the  stopped value is sent to an input of the second Multiplexers (M2) given that also a signal from first multiplexer receives that no longer the "idle" value should be output, but the counter value that now the software as an address vector for reading out Available.

At the same time, the output of the first multiplexer (M1) a "1" to the OR gate (G3). Because the exit of the OR gate (G3) at the second input of the AND gate (G2) is present and at the first input of the AND gate (G2) already from the OR gate (G1) a "1" as Message that there was an interruption at all was requested, the flip-flop (F) receives one "1" as an input signal. The flip-flop (F) indicates the "1" the software, which is notified that at the output of the second multiplexer (M2) an address vector is available for reading, which identifies the group, from which the interrupt request comes. The software gives the counter (Z) after reading the address vector free to continue counting and searches in the group concerned according to the exact origin of the Interrupt request to the appropriate To be able to process the processing routine.

If there are several interruption requests, it receives the software from finding the first group, the one Interruption requests, a continuous message about an interrupt request to a constant Jump back and forth between the actual routines the software and the interrupt routines. This is achieved in that the output of the flip-flop (F) is fed back via the OR gate (G3), so that the output of the OR gate (G3) is either "1" if the origin of an interrupt request from the Interrogator has been located, or it is  is an interrupt request that is already system before the previous one was processed. In a lot In rare cases, there may be a large number of possible sources of interrupts occur that the Software the previous interrupt request has processed before the hardware the next has located the requesting group so that at the exit of the Multiplexers (M2) are not yet the new address vector Available. However, the software is already reading the Output of the multiplexer (M2) out as it is from the signal the flip-flop (F) is asked to do so. That's why it says an "idle" value at an input of the multiplexer (M2) available, controlled by the output of the first Multiplexers (M1), from the second multiplexer (M2) is output as long as no group with Interrupt request is recognized. The software recognizes the "idle" value clearly as such and leads then another attempt to read.

If, on the other hand, there are no further interrupt requests exist after the software has an address vector has read out, the counter can be in the same group stop again when the software Interrupt has not yet been fully processed. The Signal of an interrupt request to the software is maintained until the software all pending Processed interrupts.

The maximum time within which the counter has located the next pending interrupt depends on the number of interrupt group registers:

Max. Time = number_Interrupt_Group_Register_Quellen. Cycle time.

Finally, FIG. 5 shows a further preferred embodiment of the invention, in which the possible sources for an interrupt request have been assigned two different priorities (high / low).

Connections (not shown) of the outputs of an interrupt group register lead, depending on the priority assignment of the groups, to a first interrogation device (A1) or to a second interrogation device (A2), each of which has the features according to FIG. 2 or 3 included. In this example, the first 20 groups have a high priority and the other 63 groups have a low priority. However, this example can be expanded to any number of priority levels with any number of groups.

A first exit of each of the two Interrogators (A1 / A2) is through an OR gate (G4) connected to the software (not shown). A second exit from each of the two Interrogator (A1 / A2) is through a multiplexer (M3) connected to the software. The multiplexer (M3) also receives a control signal from the first output the high priority interrogator (A1) This output signal also sets a bit of Output value of the multiplexer (M3: [6]), which in this Example itself only sets 6 bits ([0: 5]), which it as Get address vector from the interrogators. Of Another is an additional connection from the Software provided for the two interrogators.

The first of the two output signals Interrogators (A1 / A2) is through an OR gate  (G4) linked as an interrupt request to the Software issued.

The second output signals that are sent to the inputs of the Multiplexers (M3) are given the Address vector of a group that has an interrupt requests, or "idle" values. The first exit of the Interrogator with the high priority (A1) delivers also a control signal to the multiplexer (M3) that ensures that with simultaneous input of a Address vector from both interrogators (A1 / A2) of the Address vector from the interrogator with the high Priority (A1) is issued first. For Information to the software from which Query facility of the provided Address vector originates, sets the first output signal of the Interrogator with high priority (A1) one for this intended bit ([6]) of the multiplexer (M3) output word to "0" or "1". The resulting Word can then be read out by the software and are processed.

After reading the from the multiplexer (M3) to The address vector provided activates the software again the counter of the corresponding interrogation device (A1 or A2) via the input of the corresponding Interrogator.

Claims (21)

1. Device for finding an interrupt request associated with a source (source) from a large number of possible sources with a hardware device (HW) which contains an interrupt group register for interrupt requests, in each of which several sources are combined into groups, and with software (SW) for locating the searched interrupt within its group and for subsequently executing a routine provided for the source assigned to the searched interrupt in the event of an interruption, characterized in that the hardware device (HW) contains an identification device (A) whose Inputs are assigned to all groups, the identification device determining in which group there is an interrupt request, and the output of which passes an address vector corresponding to the group containing the interrupt request to the software in such a way that the address vector is assigned is the vector for the software to find the group containing the interrupt request. 2. Device according to claim 1, characterized in that the Hardware device (HW) one with all groups linked notification device (B) contains the output of which sends logic information (1/0) to the software (SW) outputs if at least one group has one Interruption request exists, such that when  Set the logic information of the address vector Identification device (A) from the software is adoptable. 3. Device according to one of the preceding claims, characterized in that each eight possible sources of interrupt requests in an interrupt group register to a group are summarized. 4. Device according to one of the preceding claims, characterized in that the Outputs of a group within the interrupt group Registers are summarized via an OR gate. 5. Device according to one of the preceding claims, characterized in that the identification device (A)

• - A multiplexer (M1), whose input signals are formed by the output signals of the groups, for sequential sampling of the output signals with a certain clock frequency
• - And a counter (Z), one input (disable) of which is connected to the output of the multiplexer (M1), for changing an address vector at the clock frequency, for stopping the change of the address vector upon input of a stop signal by the output value of the multiplexer (M1 ), to provide the address vector for the software (SW) and to control the multiplexer (M1) with the current address vector.

6. The device according to claim 5, characterized in that the Counter (Z) with each clock by the value of the address vector counts up one as long as no interrupt request  was detected, and is reset to "zero" when the address vector has reached the value "X", where X is the Number of groups corresponds. 7. The device according to claim 6, characterized in that a There is a connection between software (SW) and counter (Z), to transmit a signal from the software (SW) to the Counter (Z), after which the value has been accepted incremented by one by the software and the further query of the groups is activated again. 8. Device according to one of claims 5 to 7, characterized in that the Identification device (A) another Multiplexer (M2) comprises, at one input "Idle" value and at its other input the address vector output by the counter (Z) is present, to output the according to the output of the Multiplexers (M1) selected value to the software. 9. The device according to claim 5, characterized in that the Address vector of the interrupt request found a group without interrupting the polling mechanism the software can be passed on. 10. Device according to one of the preceding claims 2 to 9, characterized in that the Notification device a flip-flop (F) for Pass an interrupt request from the Groups whose output signals via an OR gate (G1) are linked to the software includes.   11. The device according to claim 10, characterized in that the Notification device (B) an AND gate (G2) comprises, at the first input of the output signal of the OR gate (G3) is present and at its second input the output signal of the multiplexer (M1) is present for Issuing an interrupt request to the flip-flop (F) if both an interrupt request from the All of the groups were reported as well concrete group from which the message came, from Multiplexer (M1) has already been detected. 12. The apparatus of claim 10 or 11, characterized in that the Notification device (B) another OR gate (G4) comprises the output signal at its first input of the multiplexer (M1) is present at its second input the output signal of the flip-flop (F) is present and its Output signal the second input signal of the AND gate (G3) returns. 13. Device according to one of the preceding claims, characterized in that the individual groups at least two different ones Priorities are assigned, with each group a priority has its own identification facility (A) is assigned. 14. The apparatus according to claim 13, characterized in that each the groups of a priority their own Notification device (B) is assigned.   15. The device according to one of claims 13 or 14, characterized by an OR gate (G4), whose inputs are the outputs of all Form notification facilities and its exit with the software (SW) for notification of a Interrupt request is connected. 16. The device according to one of claims 13, 14 or 15, marked by a multiplexer (M3) whose inputs match the outputs the identification devices (A) are connected, the multiplexer (M3) from the outputs of the Notification devices are controlled for Output a top priority address vector to the Software (SW) 17. Method of finding a source assigned interrupt request a variety of possible sources, in which in one Hardware device (HW) a register (interrupt group register) is included for interrupt requests, in which several sources are grouped together are, and in which software (SW) is used for Localize the searched interrupt within its Group and for subsequent processing one for the Interrupt assigned source in case of a Interruption scheduled routine, characterized in that by means of one contained in the hardware device (HW) Identification device (A), the inputs of all Groups are assigned, it is determined in which Group has an interrupt request, and from whose output is one of the interrupt request containing group corresponding address vector the software is passed on that the address vector as  Assignment vector for the software for locating the Group containing interrupt request is used. 18. The method according to claim 17, characterized in that by means of one contained in the hardware device (HW) with notification device associated with all groups (B) logic information (1/0) to the software (SW) is output if at. at least one group Interruption request is such that when Set the logic information of the address vector Identification device (A) from the software is taken over. 19. The method according to any one of the preceding claims 17 or 18, characterized in that the Input signals one in the identification device (A) contained multiplexers by the output signals of the groups are formed for sequential scanning the output signals with a certain clock frequency and that by means of a in the identification device (A) contained counter (Z), one input (disable) is connected to the output of the multiplexer (M1) Address vector is changed at the clock frequency that Change of the address vector when entering a stop signal stopped by the output value of the multiplexer (M1) is, and the address vector for the software (SW) and for Controlling the multiplexer (M1) with the current one Address vector is provided. 20. The method according to any one of the preceding claims 17 until 19, characterized in that the individual groups at least two different ones Priorities are assigned, with each group  a priority has its own identification facility (A) is assigned. 21. The method according to claim 20, characterized in that each the groups of a priority their own Notification device (B) is assigned.