DE19538002A1 - Time-share mixer circuit, esp. for microwave monolithic superheterodyne receiver - Google Patents

Abstract

A time-share mixer circuit that receives an input signal and provides a time-share output signal differing in frequency from the input signal by Delta f, the circuit comprising: a mixer having a primary input port, an oscillator input port, and an output port; a switching signal source that provides a switching signal having a frequency off fc2; a local oscillator that provides an oscillator signal differing in frequency from Delta f by the frequency of the switching signal; and a clocked inverter in series with a port of the mixer, the clocked inverter operating in response to the switching signal to cause the time-share output signal to alternate between an in-phase output signal and a quadrature-phase output signal, the in-phase output signal being that output signal which the mixer would provide if the input signal were applied to the primary input port and an oscillator signal of frequency Delta f were applied to the oscillator input port, the quadrature-phase output signal being that output signal which the mixer would provide if the input signal were provided to the primary input port and the oscillator signal of frequency Delta f were phase-shifted by 90 degrees and then applied to the oscillator input port

Description

The present invention relates generally to the Radio system and in particular to a radio circuit that one Time sharing mixer and a local oscillator used to modulate the carrier frequency of an RF signal, de modulate and change.

A superimposed radio receiver sets the carrier frequency nes input signal to an intermediate frequency while the modulation (amplitude, phase or frequency modules tion) of the input signal is maintained. The reason for this is that a radio receiver must be able to Input signals over a range of carrier frequencies received and amplified. However, a larger Ge winn can be obtained as a fixed frequency amplifier by one who has to amplify over a frequency range. A conversion of the carrier of the input signal to a fixed one Intermediate frequency only allows the amplifier stages work at a frequency, creating more profit from everyone Level can be created as otherwise available would. Each such amplifier stage is a bandpass filter stronger of any signal with a frequency inside half of a defined range, the middle of which is on the frequency of the receiver is amplified. Other Signa le are suppressed.

An ordinary AM or FM receiver (AM = amplitude mod lation; FM = frequency modulation) of the type used at home typically has an intermediate frequency and a small number of intermediate frequency amplifier stages on. Receivers, however, in the microwave spectrum or several IF amplifiers (IF = Inter mediate frequency), each  the same at a different intermediate frequency ar works. This is the case because the total profit from egg Such a receiver is required to be up to 10⁵ high can. Multiple amplifier stages with high gain must ver be used to get such a high profit. The Operate each stage at a different frequency reduces the risk of amplifier instability due to egg ner parasitic feedback from one stage to another ren.

From the previous it is obvious that everyone Superimposed receiver needs a frequency converter to the frequency of the input signal to the correct frequency to implement for the IF amplifier. If the recipient is multiple IF amplifier has that at different frequencies work, then multiple frequency converters are needed where at different for each used in the receiver Intermediate frequency a frequency converter is used.

A frequency converter has two elements: a local oscillator and a mixer. The local oscillator generates a signal with a frequency (f _LO ) which differs from the frequency (f _D ) (D = Desired = desired) of a desired input signal. The mixer combines the desired input signal with the local oscillator signal to generate two new signals, one signal having a frequency (f _SUM ) equal to the sum of the desired input signal frequency and the local oscillator frequency,

f _SUM = f _D + f _LO (1)

and the other signal has a frequency (f _DIFF ) which is the same as the difference between the desired input signal frequency and the local oscillator frequency:

f _D IFF = f _D - f _LO (2).

Typically, the user sets the frequency of the local oscillator below the desired input signal frequency such that when the local oscillator signal is mixed with the desired input signal, the mixer produces a difference signal that has the same frequency as the IF amplifier frequency (f _IF ). owns. If f _{IF is} used for f _DIFF and equation (2) is changed, the following equation results:

f _D = f _LO + f _IF (3).

If further signals are present at the receiver input, they are also mixed with the local oscillator signal in order to generate sum and difference signals. In general, however, the frequencies of these sum and difference signals will not have the same frequency as f _IF , and therefore who these sum and difference signals will be suppressed by the IF amplifier. Thus, only an input signal with a frequency f _D , which is the sum of the local oscillator frequency f _LO and the intermediate frequency f _IF , is converted to the correct intermediate frequency and amplified by the IF amplifier.

With a radio receiver as he typically ver at home is used, the oscillator using the Ab voice control tuned. Although the dial shows the Fre display of the desired station, the voting control the local oscillator frequency actually so a that the same the difference between the desired Frequency and the intermediate frequency of the receiver corresponds. So the desired radio station is selected. With others Other types of receivers can be used to tune the frequency of the local oscillator.

Although most input signals are suppressed except the one you want, an unwanted signal can get through. This is because, as noted above, the mixer produces both sum and difference frequencies. Equation ( 3 ) shows that an input signal with a frequency corresponding to the sum of f _LO and f _IF is more strongly accepted by the IF ver. Thus, equation (1) shows that an unwanted input signal with a frequency corresponding to the difference between f _LO and f _IF is also converted to the receiver IF and accepted by the IF amplifier. This undesired signal f _U is referred to as the "mirror" signal:

f _U = f _LO - f _IF (4).

The subtraction of equation (4) from equation (3) shows that the difference between the desired and the undesired frequency is 2 f _IF . Most receivers are able to suppress such image frequencies by means of a bandpass filter in front of the mixer. Such a filter prevents the unwanted image frequency from entering the mixer. Thus, the mixer only processes the desired signal because the amplitude of the unwanted mirror signal has been attenuated by the bandpass filter before it reaches the mixer.

The procedure of the input bandpass filter to mirror below pressure is in receivers such. B. AM, FM and television recipients of the type generally found at home will, sufficient. This procedure also results in the second and third frequency conversion stage of a receiver satisfactory results with multiple intermediate frequencies, because the desired mixer input frequencies are fixed and be are already relatively low. In the first frequency conversion tion circuit of a receiver over a range of Input frequencies in the microwave section of the spectrum or beyond that, the situation is different.

Consider a frequency conversion circuit in a receiver designed to operate in a frequency band, such as. B. one of the industrial, scientific or medical frequency bands to work, which have a range of desired input frequencies between about 902 MHz and 928 MHz. It would be desirable to use an adequately inexpensive fixed input band pass filter to mask out the unwanted image signals. However, in order to separate a desired input signal with a frequency in this range from its undesired mirror signal by means of such a filter, at least a protective band of 100 MHz would have to be present between the two range limits. This would require an f _IF of at least 63 MHz.

For a monolithic radio receiver (a receiver manufactured on a single integrated circuit substrate), it is advantageous to limit all intermediate frequencies to less than 10 MHz. This is because there is no practical way to make IF amplifiers that operate at higher frequencies in a monolithic design. Inductor-capacitor-tuned IF amplifiers that can be tuned to frequencies above 10 MHz are difficult to manufacture because there are no low-loss inductors available on the chip. The alternative to an inductor-capacitor-tuned IF amplifier would be an active filter. However, an active filter that works at frequencies above 10 MHz requires a relatively large amount of power. This makes it impractical to place both the filter and the rest of the receiver on a single chip. If the filter is remotely located from the receiver chip, an additional gate must be provided on the receiver chip to connect the receiver to the filter, and driving the additional parasitic capacitance that accompanies the gate requires even more power. Accordingly, the only practical way to design monolithic receivers is to limit the receiver's f _IF to no more than 10 MHz.

As previously discussed, a receiver intended to receive signals in the 900 MHz band needs an f _IF of at least 63 MHz if mirror frequencies are to be suppressed using an input bandpass filter. However, a practical receiver with an f _IF of over 10 MHz cannot be made on a single substrate. Thus, another way to suppress mirror frequencies must be found to manufacture a receiver at 900 MHz on a single substrate.

One type of frequency converter that has the ability to suppress a mirror signal without using a fixed bandpass filter in front of the mixer is shown in FIG . In this system according to the prior art, two adapted mixers 11 and 13 are driven in parallel by an input signal. A local oscillator 15 drives the first mixer 11 directly. The local oscillator drives the second mixer 13 through a first 90 ° phase shifter 17 . The first mixer provides an output to a summer circuit 19 . The second mixer provides an output to the summing circuit through a second 90 ° phase shifter 21 . The output of the summing circuit becomes the input of an IF amplifier 23 . The IF amplifier is tuned to the intermediate frequency f _{IF of} the receiver.

The first mixer passes both the desired signal and the unwanted mirror signal, which are shifted in frequency from their respective carrier frequencies f _D and f _U to f _IF , to the summing circuit. The second mixer does the same. The two phase shifters, however, have the effect of introducing a 180 ° phase shift into the frequency-converted mirror signal provided by the second mixer, while the phase of the frequency-converted desired signal remains unaffected. In the summing circuit, the mirror signal from the first mixer and the 180 ° phase-shifted mirror signal from the second mixer cancel each other out. Thus, only the desired signal is routed from the summing circuit to the IF amplifier.

The effect of the two mixers and the two phase shifters is explained in more detail below. The desired on  output signal D (t) can be expressed as follows:

D (t) = Dsin (ω _D t + Φ _D ) (5)

where D is the amplitude of the desired input signal, ωD the angular frequency and Φ _D the phase. Applying the definition ω = 2πf to equation (3) gives the following:

ω _D = ω _LO + ω _IF (6).

By using (6) in (5), the fol expression for the desired input signal:

D (1) = Dsin ((ω _LO + ω _IF ) t + Φ _D ) (7).

In a similar way, the unwanted mirror signal U (t) can be expressed as follows:

U (t) = Usin ((ω _LO - ω _IF ) t + Φ _U ) (8).

The phase angles Φ _D and Φ _U are arbitrary and will not be considered in the rest of this discussion.

The first mixer 11 combines the desired input signal with the local oscillator signal, which can be expressed as cos (· _LO t), which results in the following component in the mixer output signal:

Dsin {(ω _LO + ω _IF ) t} Cos (ω _LO t) (9).

Applying the trigonometric identity sinx · cozy = ½ (sin (x + y) + sin (xy)) to expression ( 9 ) gives the following equation:

½D (sin (²ω _LO + ω _IF ) t + sinω _IF t) (10).

The first term of equation (10) has a frequency ( 2 ω _LO + ω _IF ), a frequency that is attenuated and ignored by the IF amplifier. Thus, the second term of expression (10) after mixing in the first mixer is the only component of the desired signal that is amplified by the IF amplifier. The second term is expressed as follows:

1Dsinω _IF t (11).

Similarly, the only component of the Mirror signal after mixing in the first mixer, the amplified by the bandpass amplifier by the following Given equation:

-½ Usinω _IF t (12).

The second mixer 13 combines the desired input signal with the phase-shifted local oscillator signal. The phase-shifted local oscillator signal is expressed as sin (· _LO t). The desired input signal after mixing in the second mixer therefore has only one component that is accepted by the IF amplifier:

½Dcosω _IF t (13)

which is similar to expression (11), but with a phase displacement of 90 ° exists. The mirror signal has after mixing in the second mixer only one component, which is accepted by the IF amplifier:

½Ucosω _IF t (14)

which corresponds to expression (12), but with a phase shift of 90 °. The second phase shifter over 18 delays the phase of both expressions (11) and (12) by 90 °, which results in:

½Dsinω _IF t (15)

for the remaining component of the desired signal and

½Usinω _IF t (16)

for the remaining component of the mirror signal. If the Expressions (11), (12), (15) and (16) in the summer scarf tion are added together, the sum is:

DSinω _IF t (17).

It is obvious that the amplitudes of the undesired mirror components in the outputs of the mixers 11 and 13 , which were previously set out as expressions (12) and (16), must be adjusted exactly if the undesired mirror signal is to be completely eliminated. This requirement is particularly critical in mobile applications of a monolithic receiver, since the power of an undesired mirror signal at the receiver antenna may be 60 dB greater than the power of a desired signal due to the so-called "near-far" effect. Suppressing a signal by more than 60 dB (to suppress it below the desired signal, which is the worst case) requires that the difference between the gains of the two mixers be less than 0.1% and that any Phase error between mixers is less than one milliradian. These tolerances cannot be achieved with a practical monolithic receiver. Mirror rejection frequency conversion circuits of the type shown in Fig. 1 have not been able to suppress unwanted mirror signals by more than 20 dB despite the superior component matching achievable with integrated circuits.

Attempts to build practical IQ modulation and demodulation (I = in-phase; Q = quadrature) circuits that operate at frequencies at or above the 900 MHz range encountered similar difficulties. Consider an IQ modulation circuit as shown in FIG. 2. This circuit modulates a single carrier signal with two different signals f₁ (t) and f₂ (t). The first Si signal f₁ (t) is applied to the signal input of a mixer 25 , while the second signal f₂ (t) is applied to a signal input of a second mixer 27 . A local oscillator 29 delivers a carrier signal at the desired carrier frequency F _D. This signal is expressed as cosω _D t and is applied to the first mixer, which combines its two input signals to provide a signal which is expressed as f₁ (t) cosω _D t. The oscillator signal is also applied to a 90 ° phase shifter 31 . The output from the phase shifter, which is expressed as sinω _D t, is applied to the second mixer, which in turn provides an output which is expressed as f₂ (t) sinω _D t. These two mixer output signals are combined in a summer 33 to provide a final output signal F (t) which is expressed as follows:

F (t) = f (t) cosω _D t + f₂ (t) sinω _D t (18).

An IQ demodulator is shown in FIG. 3. A signal such as B. the signal F (t) of equation (18) is applied to the inputs of two mixers 35 and 37 . A local oscillator 39 delivers a signal at the carrier frequency F _D. This signal, which was previously expressed as cosω _D t, is applied to the first mixer 35 , which in turn provides the following output:

F (t) cosω _D t = f₁ (t) cos²ω _D t + f₂ (t) cosω _D tsinω _D t (19).

Equation (19) is obtained using trigonometric Identities to the following equation:

F (t) cosω _D t = ½f₁ (t) + ½f₁ (t) cos²ω _D t + ½f₂ (t) sin2ω _D t (20).

This output is applied to a low-pass filter 41 , which attenuates the terms with 2ω. Thus, the filter output is ½f₁ (t), which simply corresponds to the original first signal f₁ (t) after amplification.

The oscillator signal is also applied to a 90 ° phase shifter 43 , which delivers a signal that is expressed as sinω _D t. This signal is applied to a second mixer 37 , which in turn provides an output which reads as follows:

F (t) sinω _D t = f₂ (t) sin²ω _D t + f₁ (t) cosω _D tsinω _D t (21).

Equation (19) is written after the application of tri gonometric identities as follows:

F (t) sinω _D t = ½f₂ (t) + ½f₁ (t) sin2ω _D t - ½f₁ (t) cos2ω _D t (22).

This output is applied to a low-pass filter 45 , which attenuates the terms with 2ω in a manner similar to filter 43 . Thus, the output of the filter is 45 ½f₂ (t), which simply corresponds to the original second signal f₂ (t) after amplification.

From this description it is obvious that the phase shifters 31 (in the modulator) and 43 (in the demodulator) have to shift the phase of their respective oscillator signals by exactly 90 ° in order to avoid that the two signals f 1 (t) and accidentally mix up f₂ (t). It is also necessary that mixers 25 and 27 of the modulator are precisely matched and that mixers 35 and 37 of the demodulator are also matched precisely. In the 900 MHz range, these restrictions are difficult to meet.

Accordingly, it is apparent that a need for one practical, realizable monolithic frequency conversion tion circuit, which is a desired signal that be especially at or above the 900 MHz range gen and can suppress a mirror signal that 60 dB has more power than the desired signal. It exists also a need for I-Q modulator and I-Q demodula gate circuits that are good at similar frequencies keep showing.

An object of the present invention is to provide a simple time division mixer circuit to suppress to create the image frequency.

This task is accomplished through a time sharing mixer scarf tion solved according to claim 1.

Another object of the present invention is there rin, a simple I-Q modulator to suppress the  To create image frequency.

This object is achieved by an I-Q modulator 8 solved.

Another object of the present invention is there rin, a simple I-Q demodulator to suppress the To create image frequency.

This task is performed by an I-Q demodulator according to An saying 9 solved.

Another object of the present invention is there rin to create a simple frequency converter in which the image frequency is suppressed.

This task is performed by a frequency converter according to An Spell 10 solved.

Another object of the present invention is there rin to create another simple frequency converter, at which the image frequency is suppressed.

This task is performed by a frequency converter according to An Proverb 11 solved.

Another object of the present invention is there rin, yet another simple frequency converter too create, in which the image frequency is suppressed.

This task is performed by a frequency converter according to An saying 12 solved.

Another object of the present invention is there rin, yet another simple frequency converter too create, in which the image frequency is suppressed.

This task is performed by a frequency converter according to An  saying 13 solved.

The present invention provides a time division Mi. circuit that meets the need for precisely matched Mi shear eliminated in frequency conversion and the same creates an I-Q modulation circuit on any one Frequency up to the range of 900 MHz and above. A fre quenz converter which carries out the principles of the invention, suppresses a mirror signal that is 60 dB more power as a desired signal.

Briefly and in general terms, a time division Mixer circuit according to the invention has the following features: a mixer with a main and an oscillator on gangstor, a local oscillator that was an initial oscillator latorsignal provides, a circuit signal source, and one Alternating signal device ge by the circuit signal is driven. The alternating signal device controls the Circuit such that the output between an in-phase Output signal and a quadrature phase output signal and changes here. The in-phase output signal corresponds to that Signal sent by the mixer in response to a given Si gnal would deliver when the initial oscillator signal on the oscillator input gate would be created. The Qua Drature phase output signal corresponds to the signal that the Mixer would deliver if the original oscillator signal out of phase by 90 ° and then to the oscillator entrance gate would be created.

In a first embodiment, the input signal placed directly on the main entrance gate of the mixer, whereby the time division output directly from the mixer gangstor is delivered. In this embodiment, be the alternating signal device consists of a phase shifter, which ver the phase of the initial oscillator signal by 90 ° pushes, and from a circuit element that alternately the initial oscillator signal and the phase-shifted Oscillator signal coupled to the input gate of the mixer.  

In other exemplary embodiments, there is a change Signal device from a clocked inverter, the se riell is arranged to one of the gates of the mixer. With egg nem such embodiment is the getak tied inverter to the oscillator gate of the mixer, the main entrance gate receiving the input signal and the output gate delivers the output signal. With a wide one Ren embodiment is the clocked inverter seri ell connected to the mixer exit gate, with one additional further embodiment, the input signal through the clocked inverter to the main input gangway is created. In all of these execution examples len the clocked inverter is switched at a rate which is half the switching rate of the scarf tion element in the first embodiment.

A time division mixer as described above delivers an output signal at a fast rate between the in-phase output and the quadrature-phase output be switches back and forth. In some applications it is nice it's worth noting the operating cycles of these two editions same. An operating cycle balancer, which at an even multiple of the rate of the circuit signal switches, gives the in-phase output and the qua alternately Dratur-phase output free for equal periods of time.

An I-Q modulator that embodies the principles of the invention has a time division mixer and an I-Q Circuit element on. The I-Q circuit element which is driven by the circuit signal, couples alternately selectively a first and a second information signal to the Entrance of the time division mixer. The expenditure of time split mixer is bandpass filtered to an I-Q-Out to create the output signal that with both information signals is modulated.

An I-Q demodulator according to the invention also has  I-Q circuit element and a time division mixer. The I-Q circuit element which, as in the case of the Mod lators is driven by the circuit signal connects alternating the output of the time division mixer with egg nem first and a second low-pass filter. These filters again create the demodulated first and demodulated te second signal.

A time sharing mixer in conjunction with an off Gait phase shifter creates a frequency converter, which Carrier frequency of a desired high-frequency signal (HF-Si gnal) moves while unwanted mirror signals under be pressed. The output phase shifter that is on the Circuit signal responds, shifts the phase alternately of the time division output by a first and by ei ne second phase shift, the second phases shift from the first phase shift by 90 ° below separates. A filter is on after the output phase shifter ordered which the desired frequency-shifted signal delivers.

In one embodiment, the output phase shifter is a resistance-capacitor filter (RC filter; RC = Resi stor-Capacitor) with two switchable capacitors with un different values. Switching back and forth between the two capacitors provides the two different Chen phase shifts. In another execution for example, the output of the time division mixer is by a plurality of cascaded low-pass RC filters, an Ab key-and-hold circuit, an analog / digital converter and a digital phase shifter connected to a circuit signal responses, directed to the two different To create phase shifts. Another one Embodiment becomes a second time division mixer used as the phase shifter.

Preferred embodiments of the present invention are referred to below with reference to the attached drawing  nations explained in more detail. Show it:

Fig. 1 is a block diagram of a frequency conversion circuit of a heterodyne receiver according to the prior art.

Fig. 2 is a block diagram of an IQ modulator according to the prior art.

Fig. 3 is a block diagram of an IQ-demodulator according to the prior art.

Fig. 4 is a conceptual diagram of a time division mixer circuit according to the invention.

Fig. 5A is a block diagram of a time division mixer circuit comprising a local oscillator and a Pha shifters and according to a first embodiment of the present invention.

FIG. 5B is a block diagram similar to FIG. 5A, except that two phase shifters are used to generate the initial and out-of-phase local oscillator signals.

Fig. 6 is a block diagram of a time division mixer circuit having a clocked inverter which is arranged serially to the output port of the mixer according to a second embodiment of the invention.

Fig. 7 is a block diagram of a time division mixer circuit having a clocked inverter which is arranged in series with the oscillator input port of the mixer according to a third embodiment of the invention.

Fig. 8 is a block diagram of a time division mixer circuit having a clocked inverter which is arranged serially to the main entrance gate of the mixer according to a fourth embodiment of the invention.

FIG. 9 is a conceptual diagram of a time division mixer circuit which is similar to that of FIG. 4 and further includes an operating cycle balancer.

FIG. 10 is a timing chart showing the relationship between the circuit signal and the signal that controls the duty cycle adjuster shown in FIG. 9.

Fig. 11 is a block diagram of an IQ modulator, which has a time division mixer circuit which is similar to that of Fig. 5A.

Figure 12 is a block diagram of an IQ demodulator having a time division mixer circuit similar to that of Figure 5A.

FIG. 13 is a block diagram of a frequency converter having a time division mixer circuit similar to that of FIG. 5A.

Fig. 14 is a block diagram of a frequency converter, which is similar to that of Fig. 13, but which uses a Zeitauf-division mixer with a clocked inverter, wherein the mixer is similar to the mixer shown in Fig. 6.

FIG. 15 is a timing diagram of the circuit signals of the circuit of FIG. 14.

Fig. 16 is a block diagram of a frequency converter, which is similar to that of Fig. 13, the diagram in partially schematic form shows a specific embodiment of the phase shifter.

Fig. 17 is a block diagram of a frequency converter which is similar to that of Fig. 13, but which uses a second time division mixer circuit as the phase shifter.

Fig. 18 is a partially schematic diagram of a circuit with two matched filters and a digital processing circuit that can be used instead of the phase shifter used in Fig. 13.

Fig. 19 is a partially schematic diagram of a circuit with a switched low-pass filter and a digital processing circuit which can be used instead of the phase shifter used in Fig. 13.

As shown in the drawings for purposes of illustration, is the invention of a novel time division mixer circuit, which is the heart of a frequency converter, an I-Q modulator and an I-Q demodulator. It there is a need for a monolithic frequency setter for the band at 900 MHz, which un a mirror signal can suppress that 60 dB more power than a desired Signal. There is also a need for economy monolithic I-Q modulators and demodulators, that work in the same frequency band.

A time division mixer circuit according to the invention has the following features: a local oscillator, a Circuit signal source and an alternating signal device, which is driven by the circuit signal. The bills signaling device controls the circuit so that the off between an in-phase output signal and a Qua Drature phase output signal switches back and forth quickly.  

In one embodiment, the alternating signal is on direction from a 90 ° phase shifter, which the phase of the Lo calos oscillator moves, and from a circuit element, the original and the phase-shifted oscillator signal alternately coupled to the mixer. With others The alternating signal device consists of exemplary embodiments from a clocked inverter that is serial to one of the Gates of the mixer is switched.

A frequency converter according to the invention has a time partition mixer in combination with an output Pha on the phase of the time division output signals alternately shifted by 90 °. An I-Q modulator according to the invention comprises a time division mixer and an I-Q circuit element comprising a first and a two tes information signal alternately to the mixer input couples. Similar to this, an I-Q demodulator has an I-Q Circuit element and a time division mixer. The Circuit element connects the output of the time division solution mixer alternating with a first and a two th low-pass filter, which in turn causes the demodulated first and the demodulated second signal are supplied.

Circuits that implement the invention are straightforward adaptable for a monolithic structure. The Zeittetei solution mixer eliminates any need for precisely-tailored Mixers and precisely-matched amplifiers. The usage of a clocked inverter eliminates the need for egg ner precise phase shift of the local oscillator signal. A frequency converter embodying the invention can be a Suppress unwanted mirror signal that strengthens by 60 dB ker than a desired signal.

Referring now to the drawings, a time division mixer circuit embodying the invention is conceptually shown in FIG. 4. The circuit receives an input signal at an input port 101 and provides a time division output signal at an output port 103 . The circuit comprises a mixer 105 with a main input port 104 , an oscillator input port 109 and an output port 111 . A local oscillator 113 provides an initial oscillator signal. A circuit signal source 115 provides a circuit signal. Alternating signal means 117 is responsive to the circuit signal to cause the time division output to alternate between an in-phase output and a quadrature-phase output. The in-phase output signal is the output signal that the mixer would provide if the input signal to the main input gate and the initial oscillator signal to the oscillator input gate were applied. The quadrature phase output signal is the output signal that the mixer would provide if the input signal were supplied to the main input gate and if the initial oscillator signal was phase shifted by 90 ° and then applied to the oscillator input gate.

The circuit signal is also used by external components, as described below, and is provided to a circuit signal output port 119 for this purpose.

Fig. 5A illustrates a particular embodiment of a time division mixer circuit as previously described conceptional tionally. In this exemplary embodiment, the input signal at the input gate 101 is applied to a main input gate 121 of a mixer 123 . The time division output signal at the output port 103 is provided by an output port 125 of the mixer 123 . A local oscillator 127 provides an initial oscillator signal. A circuit signal source 129 provides a circuit signal. An alternating signal device 131 is implemented as a phase shifter 133 and a circuit element 135 . The phase shifter 133 shifts the phase of the initial oscillator gate signal by 90 ° to provide a phase-shifted oscillator signal. Circuit element 135 is responsive to the circuit signal to alternately couple the initial oscillator signal and the phase-shifted oscillator signal to an oscillator gate 137 of mixer 123 .

Circuit element 135 is shown as a mechanical circuit contact for purposes of illustration. However, it is apparent that a circuit transistor or other electronic circuit element of a type known to those skilled in the art is normally used, and that no mechanical switch is used in this and other embodiments described herein.

Phase shifter 133 is shown as a separate element from local oscillator 127 . In fact, there may be two phase shifters here, e.g. B. one of a phase shift of + 45 ° and one that introduces a phase shift of -45 °, so that the net effect is that two local oscillator signals are supplied, which have a phase difference of 90 ° between them. The phase shifter and the oscillator can be combined in a single quadra turoszillator circuit that provides two signals of the same frequency, but with a phase difference of 90 °.

The difference between the phases of the two local oscilla Gate signals must be controlled precisely. For some applications gen this phase shift must be controlled so that it within a milliradian at a local oscillator frequency frequency is in the range of 1 GHz. This requirement can vary can be avoided by using a clocked inverter as the alternating signal device is used. This eliminates the need for two local oscillator signals. The clocked Inverter, which ver serially with one of the mixer gates is similar to a synchronous rectifier Lich that he either an input signal according to a clock gnal inverted or not inverted. With a synchronous The clock signal has the same phase and rectifier  Frequency as the input signal on what is in an output results, which is a sequence of half-cycles, all have the same polarity. The output has a DC Component, which is why the component a "rectifier" is called. In contrast, points with a clocked inverter, as in the present Invention is used, the clock signal is not the same Phase and frequency like the input signal, which means none DC component is present in the output.

Of course, the initial oscillator signal can be shifted by a phase shift of the local oscillator output by a first phase shift, such as. B. + 45 °, while the phase-shifted initial oscillator signal can be generated by the local oscillator output by a second phase shift, such as. B. -45 °, is phase shifted. There must be a net phase difference of 90 ° between the two signals, which are applied alternately to the oscillator input. This is shown in Fig. 5B. Fig. 5B, Fig. 5A similar except for the fact that the alternating signal device 131 selsignaleinrichtung by a slightly different Wech 131 A was replaced. The device 131 A has two phase shifters 133 A and 134 A, with de receiving the initial oscillator signal from the local oscillator 127 . The slider 133 A shifts the phase by a first amount, for example + 45 °, the slider over 134 A shifts the phase by a second amount, for example -45 °. The amounts of these phase shifts are not critical as long as the difference between them is 90 °. A circuit element 135 A alternates between the two phase-shifted local oscillator signals in accordance with the circuit signal from the signal source 129 .

An embodiment of a time division mixer using a clocked inverter is shown in FIG. 6. An input signal is applied to a main input port 139 of a mixer 141 . An initial oscillator signal provided by an oscillator 143 is applied to an oscillator input port 145 of the mixer 141 . A clocked inverter 147 has an input gate 149 which is connected to an output gate 151 of the mixer 141 . A circuit signal source 153 supplies a circuit signal to the clocked inverter 147 through a 2: 1 frequency divider 154 and an input gate 155 . A time division output signal is provided to an output gate 157 of the clocked inverter. As will be described in more detail below, the frequency of the local oscillator in this embodiment differs from the frequency f _{LO of} the local oscillator in the embodiment of FIG. 5A by half the circuit frequency f _C.

The clocked inverter can be connected in series to one of the mixer input gates instead of the output gate. This is shown in Figs. 7 and 8. Fig. 7 shows an embodiment in which a clocked inverter 159 is connected between a local oscillator 161 and an oscillator input port 163 of a mixer 165 . The input signal at the gate 101 is applied to a main input gate 167 of the mixer, the time division output signal being supplied to a mixer output gate 169 . The clocked inverter receives a circuit signal from a source 171 through a 2: 1 frequency divider 172 .

Fig. 8 shows an embodiment in which a clocked inverter 173 is switched between the input signal at the input gate 101 and a main input gate 175 of a mixer 177 ge. An initial oscillator signal provided by an oscillator 179 is applied to an oscillator input port 181 of the mixer 177 , and the time division output signal is provided to a mixer output port 183 . The clocked inverter receives a circuit signal from a source 185 through a 2: 1 frequency divider 186 .

The frequency of the oscillators 161 and 179 , like the frequency of the oscillator 143, differ from the frequency f _LO by half the circuit frequency f _C.

The use of a clocked inverter also provides eliminating the need for a precision phase ver shifting the local oscillator signal another advantage. Any power returned by the local oscillator at the mixer input could be at frequencies be from the area of the desired input fre distinguish sequences strongly, even if the first intermediate frequency is low. So there’s less risk that such a leaked performance the desired Operation of the circuit or other similar receivers that are located nearby.

Each of the described embodiments provides an output signal that quickly switches between an in-phase signal and a quadrature-phase signal. It may happen that one of these signals is provided for a slightly longer section of each circuit cycle than the other. In some applications this is not desirable. A time division circuit having an operating cycle balancer to correct this problem is conceptually shown in FIG. 9. This view is similar to that of FIG. 4, where the components that are similar in both views are expediently given the same reference numerals and are not discussed further.

The duty cycle balancer includes an duty cycle signal source 187 which provides a duty cycle control signal at a frequency which is an even multiple of the circuit signal, and a duty cycle circuit element 189 responsive to the duty cycle control signal to provide the To release the in-phase output signal and the quadrature-phase output signal alternately for the same time periods. The timing of the output signals and the duty cycle control signal for the case where the frequency of the duty cycle signal is twice that of the circuit signal is shown in FIG. 10. The presence of the in-phase signal at the output port 103 is represented by a high logic level of the lower track 191 , and the presence of the quadrature-phase signal at the output port 103 is shown by a high logic level of the middle track 193 is. The operating cycle circuit element 189 is in a conductive state only when the operating cycle control signal is at a high logic level. The duty cycle control signal, shown as the upper track 195 , is high during a period in which the in-phase signal and the quadrature-phase signal are to be provided at the output port 103 . As long as each of these output signals is present for at least the length of time that the duty cycle circuit element is in a conductive state, each output signal at the output port will be as long as the other.

For the purpose of illustration, the circuit signal source 115 and the operating cycle signal source 187 are shown as separate signal generators. If two separate generators are used in an actual implementation, they should be synchronized, as is never shown by a dashed line that extends between the two signal generators in FIG. 9. Of course, a single oscillator equipped with a suitable frequency dividing circuit can serve as the source of both signals.

An IQ modulator that embodies the teachings of the invention is shown in FIG . The modulator includes an IQ circuit element 199 and a time division mixer circuit, of the type previously described and illustrated. The modulator shown includes a time division mixer similar to that of FIG. 5A in combination with an operating cycle balancer similar to that of FIG. 9, but it is apparent that one of the other time division mixers is also used could be used in place of the mixer shown, and that the operating cycle balancer could be omitted if desired. Conveniently, the components in FIG. 11 that are similar to the components of FIGS. 5 and 9 have the same reference numerals and the same will no longer be described below unless it is necessary.

The IQ circuit element 199 provides an input signal to the main input gate 121 of the mixer 123 under the control of the circuit signal provided by the circuit signal source 129 . The circuit element 199 alternates between a first input signal f 1 (t) and a second input signal f 2 (t). At the same time, the local oscillator signal, which is applied to the input port 137 of the mixer, is switched back and forth between two signals with the same frequency, but a phase difference of 90 °. During these times, at which the circuit element 199 couples the first signal f 1 (t) to the mixer, the mixer receives the local oscillator signal without a phase shift and delivers at its output the in-phase signal, ie a signal with a carrier frequency as it is is supplied by the local oscillator, and which is modulated with the first input signal f₁ (t). During the times when the circuit element 199 couples the second signal f₂ (t) to the mixer, the mixer receives the local oscillator signal with a 90 ° phase shift and provides the quadrature phase signal, ie a signal with, at its output a carrier frequency, as supplied by the Lo kaloszillator, and which is modulated with the second input signal f₂ (t). The mixer output, after passing through the duty cycle adjuster, is filtered by a bandpass filter 201 to provide the IQ output signal, which is modulated with both input signals.

An IQ demudulator that embodies the teachings of the invention is shown in FIG . The demodulator has an IQ circuit element 203 in combination with a time division mixer circuit of the type previously described and illustrated and a pair of filters 205 and 207 . The demodulator shown includes a time division mixer similar to that of Fig. 5A, but it is evident that one of the other time division mixers could be used instead of the one used, and that an operating cycle adjustment device can be provided if it is desirable. Appropriately, the components in Fig. 12, which are similar to the components in Fig. 5, have the same reference numerals, which will not be described further below, unless it is necessary.

Under the control of the circuit signal, the IQ circuit element 203 alternately couples the mixer output to the first low-pass filter 205 and the second low-pass filter 207 . During the times when the circuit element couples the output to the first low-pass filter, the mixer receives the local oscillator signal without phase shift and demodulates the input signal to provide the in-phase component. During the times when the circuit element couples the output to the second low-pass filter, the mixer receives the local oscillator signal with a 90 ° phase shift and demodulates the input signal to provide the quadrature component. The low-pass filters smooth the switched inputs that they receive to deliver the first and second signals to the respective filter output.

If the information transmitted by the first and second signals has a DC component, then the filters 205 and 207 can optionally be designed so that they do not pass DC signals. If this were the case, the filters would strictly be referred to as a "bandpass" filter because their frequency response does not extend entirely to the DC signals, and a proper "lowpass" filter has a frequency response that is up to extends to the DC signals. However, in both cases the filters perform the smoothing function to provide the demodulated first and demodulated second signals.

The use of a clocked inverter instead of switching between the two local oscillators, which must be exactly 90 ° out of phase, eliminates the need for precise phase control of the oscillator signal and for the accuracy required by the circuit element. The use of the clocked inverter requires that the local oscillator frequency f _LO be shifted up or down by an amount which corresponds to half the switching frequency f _C. The phase pointer of this shifted local oscillator frequency rotates relative to the phase pointer of the original local oscillator frequency f _LO by 180 ° per complete cycle of the circuit signal f _C. Four consecutive half cycles (ie, two consecutive cycles) of the circuit signal are considered. The average phase difference between the shifted and the original oscillator signal is incremented by 90 ° in each of the four half cycles. By assigning any reference frame, the four average values can be assigned the values 0 °, 90 °, 180 ° and 270 °. Controlling the clocked inverter with a signal having half the frequency of the circuit signal does not alternately invert or invert the polarity of the shifted local oscillator signal such that each of the two states (the inverted state and the non-inverted state) is one full cycle of the circuit signal lasts. Due to the polarity inversion (the 180 ° phase shift) during every other cycle of the circuit signal, the 180 ° average phase shift is shifted another 180 °, resulting in a net average phase shift of 0 °. Similarly, the average phase shift of 270 ° is phase shifted by an additional 180 °, resulting in an average net phase shift of 270 ° + 180 ° = 90 °. Thus, the average phase shift between the shifted and the original local oscillator frequency during four consecutive half cycles of the circuit signal f _{C is} 0 °, 90 °, 0 ° and 90 °.

In summary, the clocked inverter replaces the circuit element that switches back and forth between two local oscillator signals that are 90 ° out of phase with one another by alternating phase angles, each of which wobbles over 90 ° during every half cycle, which means an average phase difference of 90 ° results. Provided that a subsequent circuit, such as. B. a bandpass or low-pass filter, which has the property of averaging over its input in an average time that is significantly longer than the period of the circuit signal f _C , is the result of using the clocked inverter to the result of the and switching between two local oscillators that are 90 ° out of phase with each other is completely equivalent.

A mirror rejection frequency converter according to the invention is shown in FIG. 13. This converter includes a time-sharing mixer similar to that of FIG. 5A in conjunction with an operating cycle balancer similar to that of FIG. 9, but it is apparent that one of the other time-sharing mixers used instead of the one used Mixer could be used and the operating cycle balancer could be omitted if desired. Conveniently, the components in FIG. 13 that are similar to the components in FIGS. 5 and 9 have the same reference numerals and will not be discussed further unless necessary.

In addition to the time division mixer, the frequency converter comprises an output phase shifter 209 and a bandpass filter 211 . The output phase shifter 209 receives the time division mixer output from the gate 103 and, in response to the circuit signal, alternately shifts the phase of the time division output signal by a first and a second phase shift, the second phase shift being 90 ° different from the first. The bandpass filter receives the phase shifter output from a phase shifter output port 113 and in turn provides the desired frequency shifted signal.

The operation of the frequency converter as shown in FIG. 13 can be compared with the frequency converter according to the prior art shown in FIG. 1. In the circuit of FIG. 1, both the non-phase-shifted and the phase-shifted local oscillator signal are continuously mixed with the input signal in their respective mixers 11 and 13 , while in the circuit of FIG. 13, the single mixer between the non-phase-shifted ones and the phase-shifted local oscillator signal alternates. In Fig. 1, the phase shifter 21 is always active on the output of the mixer 13 , while in Fig. 13 the output phase shifter 209 switches back and forth together with the switching of the local oscillator phase shifter. The summer function in Fig. 1 is performed by the summer 19 . In Fig. 13, this function is inherently performed by the bandpass filter 211 , which averages the two signals which are alternately supplied to it. The switching frequency should be significantly higher than the bandwidth of the bandpass filter 120 to ensure that the bandpass filter smoothly averages the alternating signals. The elimination of parallel signal paths, parallel mixers and a summer with parallel inputs eliminates any problem with asymmetry in these components and therefore decisively improves the mirror suppression capability of the circuit.

The bandpass filter 211 is typically included in the first IF amplifier stage, although the filter 211 can be provided as a separate component if desired.

Circuit element 135 must have the same gain in both of its positions. However, this requirement can be alleviated if the local oscillator is strong enough to drive mixer 123 to saturation. In this case, the mixer is largely independent of the local oscillator signal amplitude which is provided by the circuit element 135 to the mixer.

The output phase shifter 209 must have the same gain in both phase shifts. The exact amount of the gain is not critical, but the bandpass filter 211 cancels the unwanted mirror signal by averaging the alternating components, and perfect cancellation can only be achieved if the time-voltage product of the two components is symmetrical. An unequal gain between the two phase shifts provided by the phase shifter 209 can be compensated for by setting the operating cycle of the circuit signal a required amount from the 50% mark.

The duty cycle element 189 may be placed anywhere between the mixer 123 and the band pass filter 211 . The best placement depends on the implementation of phase shifter 209 . Alternatively, the duty cycle element 189 may be placed between the oscillator signal circuit element 135 and the oscillator input gate 137 of the mixer 123 . The important aspect of duty cycle element 189 is that it provides means for sampling the output of the mixer over a period of time that is independent of the ratio of the times for which the two quadrature components are applied to the oscillator input port.

During the time sharing approach that was in the previous lying invention is taught the mirror suppression problem significantly reduced that with frequency converters according to the state of the art, one exists Problem that is specific to the time division concept occurs and is worth mentioning. Although the conventional un  desired mirror signal is suppressed by cancellation, new unwanted mirror signals are generated. The Fre sequences of these new mirror signals are as follows give:

f _T (m) = f _U ± mf _C (23)

where f _T (m) is the m th image frequency, m is an odd integer, f _{U is} the frequency of the original unwanted mirror signal and f _{C is} the circuit frequency. These undesirable frequencies can be suppressed by selecting a sufficiently high switching frequency f _C.

In a conventional receiver with an intermediate frequency of 1 MHz, for example, the undesired mirror frequency ²f _{IF will be} less than the desired frequency. Thus, if the desired receiver range is from 902 to 928 MHz, the unwanted image frequencies will range from 900 to 926 MHz. In a receiver having a frequency converter according to the invention, a switching frequency f _C = 200 MHz time division mirror frequencies f _T (m) will be generated which are at least 200 MHz away from f _U. The resulting guard band between the range of desired frequencies and the closest unwanted image frequency will be wider than 170 MHz. This guard band is large enough that the time division mirror signals can be suppressed by an inexpensive input filter which is positioned in front of the mixer.

As already mentioned, a preferred embodiment of a frequency converter according to the principles of the invention uses a clocked inverter and not a switched phase shifter in series with the local oscillator. An example of such a frequency converter is shown in FIG. 14. A time division mixer 214 , similar to that of FIG. 6, receives an input at its input gate and provides an output at its output gate 103 to a phase shifter 216 , which is similar to the phase shifter 209 of FIG. 13. The phase shifter 216 is in turn connected to a bandpass filter 218 to provide a frequency-converted signal.

For a given input signal with a frequency f _D , the frequency f _{LC of} the oscillator 143 of FIG. 14 will not be the same for the same input frequency as the frequency f _{LO of} the oscillator 127 of FIG. 13. From equation (3) above (f _D = f _LO + f _IF ) the frequency f _{LO of} the oscillator 127 must be set to f _LO = f _D - f _IF . However, the frequency f _{LC of} the oscillator 143 must differ from this frequency f _LO by an amount which corresponds to half the switching frequency f _C. The frequency f _{LC of} the oscillator 143 is thus given as follows:

f _LC = f _D - f _IF ± ½f _C (24).

The operation of the circuit of Fig. 14 will be described below in more detail. As in (5) above, an input signal of the following form is assumed:

D (t) = Dsin (ω _D t + Φ _D ) (25)

where D is the amplitude of the desired input signal, ω _{D is} the angular frequency and Φ _{D is} the phase. The phase angle Φ _D is not taken into account. The mixer 141 combines the desired input signal D (t) with the local oscillator signal, which can be expressed as cos (ω _LC t). The resultant mixer output signal D 'has the following term:

½DSin (ω _D - ω _LC ) t (26)

and the same has another term with a different frequency, which will not survive the subsequent filtering and is therefore not taken into account, as previously explained with regard to the first mixer of FIG. 1. Thus D 'can be conveniently expressed as follows:

D ′ = ½Dsin (ω _D - ω _LC ) t (27).

By using ω _D = ω _LC + ω _IF and ω _LC = ω _LO - ω _C / 2 in (26), the following equation results for the signal that is supplied to the input port of the clocked inverter 147 :

D ′ = ½Dsin (ω _C / 2 + ω _IF ) t (28).

The effect of the clocked inverter and the effect of switching at the frequency f _C can be described as chopping its input signal D 'by four successive chopping pulses P _A , P _B , P _C and P _D. This can be shown with reference to Fig. 15, which shows in vertical alignment two cycles of the switching frequency f _C , a cycle of f _C / 2 and the four pulses P _A , P _B , P _C and P _D , each of which has a frequency f _C / 2 and an operating cycle of 25%. These four pulses have a DC component, but if the signal D '= ½Dsin (ω _C / 2 + ω _IF ) t is multiplied by these pulses, the DC component only results in a frequency of ω _C / 2 + ω _IF , which will not survive the later bandpass filtering. The DC components can thus be neglected. The AC spectra of the four pulses are given as follows:

P _A : (2 / (nπ)) sin (nπ / 4) cos (n (ω _C t / 2 - π / 4)) (29a)
P _B : (2 / (nπ)) sin (nπ / 4) cos (n (ω _C t / 2 - 3π / 4)) (29b)
P _C : (2 / (nπ)) sin (3nπ / 4) cos (n (ω _C t / 2 - π / 4)) (29c)
P _D : (2 / (nπ)) sin (3nπ / 4) cos (n (ω _C t / 2 - 3π / 4)) (29d)

where n is any positive integer and not zero may be.

The following should expediently apply: N _AB = (2 / (nπ)) sin (nπ / 4) and N _CD = (2 / (nπ)) sin (3nπ / 4). Then multiplying D ′ with each of the four pulses and using the trigonometric identity for sin x cos y results in the following:

D'P _A = D (N _AB / 4) (sin ((1 + n) ω _C t / 2 + ω _IF t -n π / 4) + sin ((1 - n) ω _C t / 2 + ω _IF t + nπ / 4)) (30a)
D'P _B = D (N _AB / 4) (sin ((1 + n) ω _C t / 2 + ω _IF t - 3nπ / 4) + sin ((1 - n) ω _C t / 2 + ω _IF t + 3nπ / 4)) (30b)
D'P _C = D (N _CD / 4) (sin ((1 + n) ω _C t / 2 + ω _IF t - nπ / 4) + sin ((1 - n) ω _C t / 2 + ω _IF t + nπ / 4)) (30c)
D'P _D = D (N _CD / 4) (sin ((1 + n) ω _C t / 2 + ω _IF t - 3nπ / 4) + sin ((1 - n) ω _C t / 2 + ω _IF t + 3nπ / 4)) (30d).

The components of these four products, which have a frequency ω _IF , which are the only components that will survive the bandpass filter centered around this frequency, exist only for n = 1, in which case: N _AB = N _CD = (2 / π) sin (π / 4). This results in:

D′P _A = D′P _C = D (N _AB / 4) sin (ω _IF t + π / 4) (31)

and

D'P _B = D'P _D = D (N _AB / 4) sin (ω _IF t + 3π / 4) (32).

The first two signals D'P _A and D'P _C occur in the first half of the cycle of the circuit signal f _C , whereby the se two signals pass through the clocked inverter without a phase shift. The other two signals D'P _B and D'P _D occur in the second half of the cycle of the circuit signal, which causes them to be phase-shifted by 90 °, which results in the following equation for the latter two expressions after being inverted by the clocked signal have arrived:

D′′P _B = D′′P _D = D (N _AB / 4) sin (ω _IF t + 3π / 4 - π / 2) = D (N _AB / 4) sin (ω _IF t - π / 4 ) (33).

All four signals are present in the output. Your sum is:

D′P _A + D′′P _B + D′P _C + D′′P _D = D (N _AB / 2) (sin (ω _IF t + π / 4) + sin (ω _IF t - π / 4 )) (34)

or

D′P _A + D′′P _B + D′P _C + D′′P _D = (D / π) sSin (ω _IF (35).

The desired input signal with the angular frequency ω _{D has} thus been converted into an intermediate frequency with an angular frequency ω _IF .

A similar calculation shows that the unwanted game Gel signal is canceled.

Just as the switched phase shifter in connection with the local oscillator 127 has introduced an undesirable new time division image frequency in the embodiment of FIG. 13, the clocked inverter also introduces new undesired time division image frequencies. The clocked inverter introduces the same mirror frequencies as the circuit of FIG. 13. In addition to these image frequencies, the clocked inverter introduces a set of image frequencies f _T (q), which are given as follows:

f _T (q) = f _D ± qf _C (36)

where q is an even integer and not zero. These new time division mirror frequencies can also be suppressed by choosing a switching frequency f _C that enables a sufficient guard band.

The frequency conversion circuits shown in FIGS. 13 and 14 use an analog phase shifter 209 . A preferred implementation of such a phase shifter fulfills at least two conditions. First, the two paths that produce the two phase shifts must share the same circuit as much as possible. This minimizes symmetry errors due to circuit component mismatches. Second, the implementation must not require a high gain for an amplifier that operates over a wide bandwidth, since one of the reasons for using a time division mixer is to avoid such high gain broadband amplifiers.

An implementation of a suitable analog phase shifter is shown in FIG. 16. The circuit is similar to that of FIG. 13. Similar components have the same reference numerals and are not discussed further below.

An amplifier 215 receives the time division mixer output from the output gate 103 of the time division mixer. The amplifier 215 provides complementary outputs + V and -V at the first and second amplifier outputs 217 and 219, respectively. The first output 217 is connected to a resistor 221 , which in turn is connected to the output gate 213 . The second output 219 is connected to two capacitors 223 and 225 , which in turn are connected to a first and a second terminal of a circuit element 227 . The circuit element 227 has a pole which is connected to the output gate 213 . Circuit element 227 is controlled by the circuit signal.

The values of resistor 221 and capacitors 223 and 225 are chosen to produce two signals with a relative phase shift of 90 °. The respective phase shifts can be, for example, 45 ° and 135 °. When selecting the values of these components, it should be noted that the capacitors are connected to the resistor only for a period of time p and (1-p), where p is the circuit duty cycle (ideally, p = 50%). An error in the operating cycle would result in a proportional error in the effective ratio of the two capacitors and therefore in an error in the relative phase shifts of the two signals. Of course, the duty cycle could be intentionally adjusted to compensate for any errors in the capacitor values.

A frequency converter using a second time division mixer to deliver the phase shift is shown in FIG . A first time division mixer circuit 228 generally receives an input signal at its input port 229 and provides an output signal at its output port 231 . The output port 231 is connected by a band pass filter 233 to an input port 235 of a second time sharing mixer circuit, generally designated 237 , which serves as a phase shifter. The phase shifter 237 provides an output to a bandpass filter 239 at its output gate 241 .

In the illustrated embodiment, both the time division mixer circuit 228 and the time division mixer circuit 229 are similar to the exemplary embodiment shown in FIG. 5A, except that a single circuit signal source 243 provides the circuit signal for both circuits. The circuit 228 includes a mixer 245 which receives the input signal which is present at the input port 229 and which delivers the output to the output port 231 . The mixer 245 has an oscillator input which is connected by a circuit element 247 alternately to a local oscillator 249 and to a phase shifter 251 which shifts the phase of the local oscillator by 90 °. Similarly, circuit 237 includes a mixer 253 which receives the input signal applied to input gate 235 and which provides the output to output gate 241 . The mixer 253 has an oscillator input which is connected by a circuit element 255 alternately to a local oscillator 257 and to a phase shifter 259 which shifts the phase of the local oscillator by 90 °. The circuit signal source drives the two circuit elements 247 and 255 .

In some embodiments, a separate circuit signal source may be used to drive circuit element 255 . This would be the case, for example, if the filter 233 were implemented by a pair of switched filters, such as e.g. By those shown in Fig. 18 and discussed below.

The second time division mixer circuit 237 will be sensitive to an unwanted image frequency at its input. Such an undesirable image frequency could result from an undesired signal at the input to the first mixer circuit 228 . The filter 233 will suppress any such undesirable image frequency. The filter 233 can be implemented, for example, by a low-pass filter, which is similar to the filter 227 shown in FIG. 19 and discussed below.

One or both of the time division mixer circuits 228 and 237 may be implemented by an alternative embodiment, such as e.g. B. one of the games shown in Figs. 6, 7 and 8 Ausführungsbei, be replaced.

As already mentioned, a high switching frequency of e.g. B. f _C = 200 MHz is desirable to ensure a sufficient distance between the time division mirror frequencies and the desired input frequency of the frequency converter. However, the useful information at the output of the phase shifter ( 209 in FIG. 13) is transmitted by a signal at an intermediate frequency f _IF and can therefore be implemented by relatively low-frequency circuits, such as. B. the bandpass filter 211 are processed.

In many applications, it would be desirable to replace phase shifter 209 and bandpass filter 211 in the circuit of FIG. 13 with more accurate digital signal processing hardware. Digital processing hardware that emits a signal that is transmitted at a relatively high frequency, e.g. B. 200 MHz, could be processed, would consume too much power. Therefore, in order to exploit the capabilities of digital signal processing without excessive power consumption, the switching frequency of the signal must be significantly reduced before the same is processed by the digital hardware. However, in order to keep the time division mirror frequencies away from the desired input frequency, this must be done without reducing the high circuit frequency used in the frequency converter circuit. This can be accomplished by filtering the two quadrature components of the time-sharing mixer output separately, and by replacing the output phase shifter 209 and band-pass filter 211 with a digital signal processing circuit that performs the functions of these components. A circuit that can be used for this purpose is shown in FIG .

Fig. 18 shows a frequency converter showing a time division mixer similar to that previously discussed. A time division mixer 261 , similar to the circuit in Fig. 5A, is used in the illustrated embodiment, but it is apparent that some other time division mixer, previously discussed and illustrated, is used instead that can. An IQ circuit element 263 , controlled by the circuit signal, receives the output signal from the output port of the time division mixer 261 . IQ circuit element 263 has two outputs, one driving a filter 265 and the other driving a filter 267 . A second IQ circuit element 269 , which is controlled by a circuit signal source 271 , connects the outputs of each filter 265 and 267 alternately to an analog / digital converter 273 . The output of the A / D converter 273 (A / D = analog / digital) is in turn supplied to a digital phase shifter and a summer 275 .

Filter 265 may be referred to as an "I" filter, while filter 267 may be referred to as a "Q" filter. These filters convert the alternating I and Q components at the output 103 of the time division mixer circuit 261 into continuous I and Q signal currents, respectively. Therefore, the frequency of the signal source 271 may be different from the frequency of the circuit signal supplied to the circuit signal output port 119 of the time division mixer 261 . The frequency of the signal source 271 is preferably chosen low enough to allow digital signal processing without excessive power consumption.

In order to maintain a high level of mirror rejection, filters 265 and 267 must pass the I and Q components of the intermediate frequency signal supplied to the output port 103 of time division mixer 261 with a well-adjusted phase shift and well-matched gain. This is made easier if filters 265 and 267 share as many components as possible. A circuit in which the two filters share most of their components is shown in FIG. 19.

The circuit of FIG. 19 corresponds in many respects to the circuit of FIG. 18, the same reference characters being assigned to similar components in both figures for the sake of convenience. A low pass filter circuit, generally designated 277 , replaces IQ circuit elements 263 and 269 and filters 265 and 267 of FIG. 18. Filter 277 receives the signal from output port 103 of time division mixer 261 . The filter 277 includes a plurality of cascaded RC filter stages and a sample-and-hold element 279 . The first such RC filter stage comprises a resistor 281 , which receives the signal and couples it to the input of an amplifier 283 . A circuit element 285 , which is driven by the circuit signal from the gate 119 of the mixer circuit, alternately connects a capacitor 287 and a capacitor 289 to the input of the amplifier 283 .

Similarly, the second filter stage includes a resistor 291 which receives the signal from the first filter stage and couples it to an input of an amplifier 293 . A circuit element 295 , which is driven by the circuit signal from the gate 119 of the mixer circuit, alternately connects a capacitor 297 and a capacitor 299 to the input of the amplifier 293 . The third filter stage comprises a resistor 301 , which receives the signal from the second filter stage and couples it to the input of an amplifier 303 . A circuit element 305 , which is driven by the circuit signal from the gate 119 of the mixer circuit, alternately connects a capacitor 307 and a capacitor 309 to the input of the amplifier 303 . The amplifiers are typically emitter or source followers that act as buffer amplifiers.

The output from the third filter stage is provided to the sample-and-hold element 279 and then to the A / D converter 273 . The sample-and-hold element 279 is controlled by the circuit signal source 271 .

The sample-and-hold element 279 has a recording time slot which is shorter than 1 / (2f _C ), but the same is triggered by a signal supplied by the signal source 271 , which has a frequency f _S which is chosen such that it is an odd fraction of 2f _C. As a result, the samples taken by sample-and-hold element 279 alternate between the quadrature samples taken by capacitors 287 , 297 and 307 and the in-phase samples which have been picked up by the capacitors 289 , 299 and 309 . If the frequency f _{S of} the circuit signal source 271 is selected such that f _s <f _O + f _IF , where f _{O is} the stop band edge of the low-pass filter 271 , any signal that comes from the low-pass filter is prevented from entering the IF signal is folded back. Since two samples form a single circuit cycle with reduced frequency, the switched low pass filter together with the sample-and-hold circuit has the effect of switching the circuit frequency that occurs at the output of the sample-and-hold element from f _C to reduce to a new frequency f _C ′ = f _S / 2. In a practical case where f _{C is} 200 MHz, f _C ′ could be less than 7 MHz.

The signal supplied by d 01112 00070 552 001000280000000200012000285910100100040 0002019538002 00004 00993ie the sample-and-hold circuit is converted into a digital form in the A / D converter 273 . Once the signal has been digitized, an accurate 90 ° phase shift between the two quadrature components can be readily achieved using conventional digital techniques, such as in the digital phase shifter and summer 275 .

From the foregoing it is obvious that time Distribution mixer of the invention a frequency converter creates that has skills that were previously in a mo nolithic receivers were not reachable. A frequency implementer that embodies the principles of the invention an unwanted mirror signal that is 60 dB more power than the desired signal. A ent radically improved I-Q modulator and a crucial one improved I-Q demodulator are also created.

Claims (13)

1. Time division mixer circuit which receives an input signal and provides a time division output signal, having the following features:
a mixer ( 105 , 123 ) having a main input gate ( 107 , 121 ), an oscillator input gate ( 109 , 137 ) and an output gate ( 111 , 125 );
a local oscillator ( 113 , 127 ) that provides an initial oscillator signal;
a circuit signal source ( 115 , 129 ) which supplies a circuit signal; and
an alternating signal means ( 117 , 131 ) responsive to the circuit signal to cause the time division output signal to alternate between an in-phase output signal and a quadrature-phase output signal, the in-phase output signal being the output signal is what the mixer would deliver if the input signal to the main input port and the initial oscillator signal were applied to the oscillator input port, the quadrature phase output signal being the output signal that the mixer would deliver if the input signal to the main input port would be applied and the initial oscillator signal would be phase shifted 90 ° and then applied to the oscillator input gate. 2. A time division mixer circuit according to claim 1, wherein the input signal is applied to the main input port ( 121 ) of the mixer ( 123 ), the time division output signal being supplied to the mixer output port ( 125 ), and the alternating signal device ( 131 ) has the following features having:
a phase shifter ( 133 ) which shifts the phase of the initial oscillator signal by 90 ° to provide a phase-shifted oscillator signal; and
a circuit element ( 135 ) responsive to the circuit signal to alternately couple the initial oscillator signal and the out-of-phase oscillator signal to the mixer oscillator gate ( 137 ). 3. Time division mixer circuit according to claim 1, in which the alternating signal device has a clocked inverter ( 147 ) which is arranged in series with a gate of the mixer ( 141 ). 4. Time sharing mixer circuit according to claim 3, wherein the input signal is applied to the main input port ( 139 ), the initial oscillator signal is applied to the oscillator input port ( 145 ) and the clocked inverter ( 147 ) is connected in series to the mixer output port ( 151 ) is to provide the time division output. The time division mixer circuit of claim 3, wherein the input signal is applied to the main input port ( 167 ) of the mixer ( 165 ), the initial oscillator signal is applied through the clocked inverter ( 159 ) to the oscillator input port ( 163 ), and that Time split output signal is provided to the mixer output port ( 169 ). 6. time sharing mixer circuit according to claim 3, wherein the input signal through the clocked inverter ( 173 ) is applied to the main input port ( 175 ) of the mixer ( 177 ), the initial oscillator signal is applied to the oscillator input port ( 181 ), and the time division output signal is provided to the mixer output gate ( 183 ). A time division mixer circuit according to any one of the preceding claims, further comprising a duty cycle equalizer ( 187 & 189 ) operative to operate the in-phase output signal duty cycle to the quadrature-phase output signal duty cycle align. 8. IQ modulator with the following features:
a time division mixer circuit according to any of the preceding claims; and
an IQ circuit element ( 199 ) responsive to the circuit signal to alternately couple a first and a second information signal to the input ( 101 ) of the time division mixer circuit, thereby providing an IQ output signal that modulates with both information signals is. 9. IQ demodulator with the following features:
a time division mixer circuit according to any of claims 1 to 7, which receives an IQ signal that is modulated with a first and with a second information signal;
a first filter ( 205 );
a second filter ( 207 ); and
an IQ circuit element ( 203 ) responsive to the circuit signal to alternately couple the time division output signal to the first and second filters and thereby demodulate the IQ signal to pass the first information signal through and through the first filter the second filter to deliver the second information signal. 10. Frequency converter for shifting the carrier frequency of an RF signal with the following features:
a time division mixer circuit according to any one of claims 1 to 7, which receives the RF signal as its input signal;
an output phase shifter ( 209 ) responsive to the circuit signal for alternately shifting the phase of the time division output signal by a first and a second phase shift, the second phase shift differing from the first phase shift by 90 °; and
a bandpass filter ( 211 ) which receives the phase-shifted time division output signal and provides the desired frequency-shifted signal. 11. Frequency converter for shifting the carrier frequency of an RF signal with the following features:
a time division mixer circuit according to any one of claims 1 to 7, which receives the RF signal as its input signal;
an in-phase filter ( 265 );
a quadrature filter ( 267 );
a first quadrature circuit element ( 263 ) which receives the time division output signal and supplies the output signal alternately to the in-phase filter and the quadrature filter under the control of the circuit signal;
an analog to digital converter ( 273 );
a second circuit signal source ( 271 ) providing a second circuit signal;
a second quadrature circuit element ( 269 ) controlled by the second circuit signal to alternately couple the in-phase filter and the quadrature filter to the analog-to-digital converter; and
a digital phase shifter ( 275 ) which is coupled to the analog / digital converter, which supplies the desired frequency-shifted signal. 12. Frequency converter for shifting the carrier frequency of an RF signal with the following features:
a time division mixer circuit according to any one of claims 1 to 7, which receives the RF signal as its input signal;
a plurality of cascaded low pass filter stages ( 277 ) that filter the time division output signal, each stage comprising a resistor ( 281 , 291 , 301 ), a first capacitor ( 287 , 297 , 307 ), a second capacitor ( 289 , 299 , 309 ), circuit means ( 285 , 295 , 305 ) responsive to the circuit signal to alternately connect the first capacitor and the second capacitor to the resistor in series, and has an output amplifier ( 283 , 293 , 303 );
a sample-and-hold circuit ( 279 ) which samples the filtered time division output signal;
an analog-to-digital converter ( 273 ) which converts the sampled values provided by the sample-and-hold circuit into a digital signal; and
a digital phase shifter ( 275 ) which alternately shifts the phase of the digital signal by a first and a second phase shift, the second phase shift differing from the first by 90 °, and whereby the digital phase shifter ( 275 ) shifts the desired frequency Signal delivers. 13. Frequency converter for shifting the carrier frequency of an RF signal with the following features:
a time division mixer circuit ( 228 ) according to any one of claims 1 to 7;
a filter ( 233 ) that filters the time division output signal from the time division mixer circuit;
a second mixer ( 253 ) having a main input port which receives the filtered signal from the filter, an oscillator input port and an output port;
a second local oscillator ( 257 ) providing a second initial oscillator signal; and
second alternating signal means ( 255 ) responsive to a circuit signal to cause an output signal provided at the second mixer output port to alternate between first and second output signals, the first output signal being the output signal which is the second Mixer would deliver if the second initial oscillator signal were applied to the oscillator input port of the second mixer, the quadrature phase output signal being the output signal that the second mixer would provide if the second initial oscillator signal were 90 ° out of phase and then would be placed on the oscillator input port of the second mixer.