DE19523731C1 - Power semiconductor setting command system for 4-quadrant regulator - Google Patents

Abstract

The system provides setting commands for both positive and negative network voltages as a cyclic sequence of switch conditions for the switching power semiconductors, represented by a pulse pattern provided by a microprocessor pulse pattern generator. The transition from one switch condition to the next switch condition when the regulation error for the current through the 4-quadrant regulator reaches the limits of the tolerance band, or when the error lies outside the tolerance band for a defined interval.

Description

The invention relates to a method according to the Preamble of claim 1. Such a method is through the contribution of Ch. Endrikat "DIGITAL CONTROL OF A FOUR-QUADRANT CONVERTER USING PREDICTIVE CURRENT CONTROL " Proceedings EPE ′91, Florence 1991, Vol. 2, pp. 48-51 known.

Traction drives for electric locomotives or Multiple units are based on asynchronous motors then one or more people working in parallel Mains converters for feeding a DC link and one or more Pulse inverters for supplying and controlling the Drive motors. The line converter for that usually single-stranded alternating voltage rail network work here each as a four-quadrant. The Four-quadrant controllers can be in two-step or in Three-stage technology (often also as a 2- or 3-level technology designated) to be executed, that is, to stand two potential levels on the DC voltage side (plus and minus) or three potential levels (plus, zero, minus) are available (see also the contribution by S. Salama and S. Lennon "OVERSHOOT AND LIMIT CYCLE FREE CURRENT CONTROL METHOD FOR  PWM INVERTERS "Proceedings EPE ′91, Florence 1991, Vol. 3, pp. 247-251).

The power converter with the associated control has the task of powering the drive units to ensure from the rail network. This is done by the Regulation of the intermediate circuit voltage (s) to a constant Value. The regulation uses the Mains converter as an actuator. The task of current regulation for such an actuator it is therefore one of the superimposed control predetermined setpoint for the current to be set as the actual value, i.e. the controller manipulated variables are the control commands for switching the Power semiconductor switch or the one formed by this Converter strings.

The regulation also has additional constraints to fulfill, among other things, the network perturbations, that is those generated due to the switching actuator, to keep line-side overcurrents low and one defined phase angle between the mains voltage and the Mains current (cos ϕ = 1 or grid-supporting phase angle) guarantee. For the regulation, this means one as exact as possible sinusoidal mains current in phase with the Impress the mains voltage with a minimal current ripple.

So far, the converters are mainly because of necessary switching power GTO (gate turn-off) thyristors used as a power semiconductor switch. GTO thyristors allow only one due to their switching losses Pulse frequency of some 100 Hz.

Although the four-quadrant set only a few, discrete Switching states can be assumed by one of these Actuator upstream pulse width modulation an apparently generates continuous behavior in terms of value. Through the suitable implementation of this pulse width modulation the power electronics requirements for more limited  and even switching frequency can be easily met.

Both the regulation and the pulse width modulation have been synchronized with each other so far, realized by means of a computer (microprocessor) (cf. S. Salama, S. Lennon op. Cit.). The sampling time of the scheme and the pulse width modulation depends among other things on the number of offset clocked parallel converters and the pulse pattern strategy used.

The disadvantage of using GTO thyristors Mains converter exists even with optimally executed Regulation in a relatively large current ripple and thus strong network perturbations due to the low Pulse rate. In addition, the scheme can be distorted Mains voltages or due to the relatively large Switching delay times of the GTO thyristors are not ideal Generate sinusoidal mains current.

It is through the essay by H. Kehrmann, W. Lienau, R. Nill "four-quadrant controller - a network-friendly Infeed for traction vehicles with three-phase drive "in: Elektro Bahnen, 45 (1974) Issue 6, pages 135 to 141 already a control procedure for a four-quadrant generator known, in which both one Clocking the power semiconductor switch as well as one of the polarity specification depending on the direction of the mains voltage he follows. A clocking of the Power semiconductor circuit through a two-point controller made within a tolerance band for the current, during a polarity switch with changed polarity the counter tension by an additional (compared to the Tolerance band larger dimensioned) hysteresis initiated becomes, which requires a large amount of comparators.

As an alternative to the GTO thyristors are now available simple and powerful, fast switching IGBT (Insulated Gate Bipolar Transistor) valves available.  

Because of the tendency to single-axle or single-wheel drives distributing it over the train reduces the Power requirement on the individual converter, whereby the possible use of compared to GTO inverters even less powerful IGBT converters for Full railways already exist today. Allow IGBT converter a more advantageous higher pulse frequency (1-3 kHz).

While maintaining the previous regulatory structure the higher pulse frequency requires an additional one Effort regarding the performance of the computers (Microprocessors): At least the clock of the Pulse pattern generator adapted to the higher pulse frequency will.

The invention has for its object a method of Specify the type mentioned at the beginning Reduction of effort to use one on one Microprocessor implemented pulse pattern generator entirely can be dispensed with.

This object is achieved according to the invention by the Characteristics characterized claim 1 solved.

This is advantageous instead of the previous one Inverter control via pulse pattern generators based on Microprocessors are realized, a direct control made by a current switching regulation. Such Switching control is characterized by robustness Parameter fluctuations, very high dynamics and high Noise suppression off. In addition, it is through a Rear derailleur (for example in EPLD technology) simple and cheap to realize. The requirements for the This reduces the control processor.

Advantageous further developments of the method according to Invention are characterized in the remaining claims.

The invention is intended in the following with reference to the drawing illustrated embodiments are explained. It demonstrate

Fig. 1 shows the basic structure of a one-phase four-quadrant actuator in two-stage technology, the GTO elements shown there can also be replaced by IGBT or other suitable components.

Fig. 2 pulse patterns and switching state graphs for the four-quadrant controller in FIG. 1

Fig. 3, two state graph for the case shown in Fig. 1 four-quadrant controller for the two polarities of a mains voltage,

Fig. 4 Steller a state graph for the switching control of the four quadrants shown in Fig. 1,

Fig. 5 shows the principle circuit diagram of a Vierquadran least tellers in three-step technique, wherein here also other power semiconductor devices are conceivable instead of the GTO,

FIGS. 6a-c pulse pattern and associated state graph for the in Fig. 5 shown four-quadrant controller,

Fig. 7, four basic cycles of the switching regulator of a four-quadrant controller in accordance with Fig. 5,

Fig. 8 is a state graph for the switching control of a four-quadrant controller in accordance with Fig. 5,

Fig. 9 shows the timing of current, voltages, and switching signals when changing between two cycles of a four-quadrant controller in accordance with Fig. 5,

Fig. 10, the creation of a limit cycle in a counter-zero voltage by a current reference step,

Fig. 11 is a state graph for the switching control of a four-quadrant actuator according to FIG. 5 with the consideration of minimum times and

FIG. 12 shows a state graph for the switching control of a four-quadrant actuator according to FIG. 5, taking into account minimum times and with DC voltage balancing.

In Fig. 1 is a schematic diagram of a single-strand two-stage four-quadrant controller shown as it can be used as power converters for traction drives.

The four-quadrant actuator consists of a first actuator branch 1 with a GTO thyristor T11 and a GTO thyristor T12 and the two thyristors T11 and T12 antiparallel connected freewheeling diodes D11 and D12. A second actuator branch 2 of the four-quadrant actuator has GTO thyristors T21 and T22 and these freewheeling diodes D21 and D22 connected in anti-parallel. Instead of the conventional GTO thyristors, IGBT valves with a higher possible switching frequency are being used more and more advantageously.

On the AC voltage side, each actuator branch 1 , 2 of the four-quadrant actuator is connected to a connection of a single-stranded AC voltage source N (for example a rail network). L denotes a smoothing inductance in the supply line on the AC voltage side or the leakage inductance of a transformer (not shown).

On the DC voltage side, the four-quadrant actuator has an intermediate circuit capacitor C between the two potentials + and -, which represent a potential difference corresponding to an intermediate circuit voltage u _d . A pulse inverter (not shown here) with a subsequent asynchronous motor is usually connected to the intermediate circuit.

The task of a current control for the current i by such a four-quadrant controller is to set a current setpoint specified by an overlaid control (not shown) as the current actual value. To do this, one uses a total of four possible different switching states of the actuator, which are defined by two potential setting commands S₁, S₂ of the two actuator branches. Each potential setting command can have the values "+" and "-". As a result, the branch potential is controlled either to the positive or to the negative intermediate circuit potential in accordance with the connection of the AC voltage connection via one of the thyristors T11 to T22 of each of branches 1 and 2 to the potential + or - of the intermediate circuit. For the task of current regulation, however, only the actuator voltage u _s , which results as the difference between the branch potentials, is relevant. The actuator voltage u _s depends on the control commands according to the following table

The actuator voltage can therefore assume three different values (-u _d , 0, + u _d ), the zero voltage being adjustable by means of two different switching states. In order to achieve the lowest possible current ripple and a low switching frequency, it makes sense to use only the two actuator voltages that come closest to the counter voltage u _n (mains voltage) among the three available actuator voltages. Specifically, this means that for positive counter voltages u _n only the actuator voltages 0 and + u _d , for negative counter voltages u _n only the actuator voltages 0 and -u _d should be used.

Fig. 2 shows two different realizable pulse patterns that meet this requirement: pulse patterns P1 and P3 for negative pulse pattern, and P2 and P4 for positive reverse voltage u _n. The pulse patterns shown in FIG. 2 and in the following figures are only sketched according to the principle. The pulse widths actually required are not shown here.

In the case of the pulse patterns P3 and P4, it should be noted that if the countervoltage is small in magnitude, one of the branches would have to switch very narrow pulses, which are set a barrier due to the minimum pulse width specified by the power electronics. It is therefore more favorable to implement the two switchovers of a short pulse of the actuator voltage not within one actuator branch 1 or 2 , but by distributing it over the two actuator branches 1 and 2 . Since the two actuator branches 1 , 2 can be designed independently of one another, there are no time restrictions with this procedure. This method is used for the pulse patterns P1 and P2, so that voltages close to the zero voltage can be realized without restriction, which is why these variants are preferred. The problem of minimum pulse widths also occurs near the full modulation - but equally in all variants.

These pulse patterns can be generated quite simply with the aid of pulse width modulation, which, however, is not intended to be used in the desired switching control. Nevertheless, the specifiable pulse pattern to be implemented can serve as the basis for the design of the switching control:
The first conceptual step consists in breaking down the desired pulse pattern into a cyclic sequence of the switching states involved, as is already shown in FIG. 2. In the state graph over the pulse patterns P1 to P4, the switching state of the four-quadrant actuator is indicated by the two control commands S 1, S 2 at the top right and the resulting actuator voltage u _s at the bottom (see also the table above). It is important to understand switching states that occur several times within a cycle as different states and to list them accordingly several times, such as the state (S₁, S₂) = (- +) in the pulse pattern P1. The actuator voltage alternates in the pulse pattern P1 between 0 and -u _d .

This transition between the states can be controlled directly by the current control error. For this purpose, two logic signals from the negative current control error Δi, namely the difference between the actual value i of the current and the current setpoint i _w (Δi = 1 - i _w ) and a hysteresis range Δi₁ of a first tolerance band for the current control error are defined:

R +: = i - i _w <+ Δi₁,
R -: = i - i _w <- Δi₁.

These signals are used first to set up two separate state graphs for positive and negative countervoltage, which generate the desired sequence of the switching states of the pulse patterns P1 and P2 in FIG. 2. This results in a state graph with separate cycles for the two polarities of the counter voltage u _n <0 and u _n <0, as shown in FIG. 3.

If the opposite voltage changes its sign, a transition must take place between the state graphs of FIG. 3.

In principle, the sign of the mains voltage (reverse voltage u _n ) could be used for switching between the cycles of the switching states. For this purpose, the voltage measurement of the switching control would have to be made available. However, this procedure would not take voltage drops in leakage inductances and resistors into account. However, it is possible to generate an appropriate switchover signal solely from the current control error. Three different strategies can be used:

A first possibility is given by the fact that each of the two control error signals R +, R- a changeover (one Change of state). Usually shortly after Switching to a new actuator voltage Control error signal go out again because of the current again enters the first tolerance band Δi₁. Admitted nevertheless Control error signal still on, this is a sign that the selected actuator voltage is insufficient or the Counter voltage must have changed the sign. In in this case, the system switches to the other cycle. It two further logical signals are defined:

RT +: = R + is pending longer than a time T,
RT-: = R- is present longer than the time T.

Since R + and R- can never be present at the same time, it is advisable to first generate a common time signal RT:
RT: = R + ∨ R- is present longer than the time T-. The RT + and RT- signals can then be formed by linking the RT signals with the R + and R- signals.

However, the correct measurement of time T is problematic. It must not be too short, not to go through Switching delays caused brief overshoots of the Tolerance range to trigger a switchover; it must not be too long, otherwise the current can move too far from the tolerance range. The vote the time T depends on the used Switching elements. Here are time delays Pulse formation, the pulse amplifier and the actual Semiconductor valve with its wiring too  consider. This time must at least be waited for the impact of the last switch on the To be able to assess control errors. When using GTO Thyristors are about 100 for T. . . 200 µs at IGB transistors approx. 2. . . 10 µs to choose.

The advantage of this procedure is that no additional Comparators next to those for the actual tolerance band are needed.

A second possibility of determining the signals RT + and RT- is the following: If the polarity of the counter voltage u _{n changes} , the actuator voltages selected in the previous cycle are no longer sufficient to keep the current control error Δi in the first tolerance band with the width Δi₁. This effect can be monitored by specifying a second, larger tolerance band Δi₂ <Δi₁ and used to generate the switching signals in the other cycle.

RT: = Δi <+ Δi₂ or Δi <- Δi₂

This signal can then be used for the actually required ones Signals through

RT +: = RT ∧ R + and
RT-: = RT ∧ R-

be determined. Through this monitoring, the electricity be kept safely within the limit Δi₂. However, the current must be the smaller for each switch leave first tolerance band Δi₁.

The third possibility for determining the changeover signals from one cycle to another in the event of a polarity change in the counter voltage u _n from the course of the current control error can be seen from FIG. 9. There you can see that the zero voltage crossing of the counter voltage u _n due to the "current garland" that occurs can also be determined by twice thrusting the control error Δi to the same limit of the (first) tolerance range shown in broken lines. This second triggering can therefore be used to generate the switchover signal RT. In this method, unlike the two methods described above, the (first) tolerance range is not left at all when switching over. In reality, however, a time limit T _w must be waited for after the first triggering in order to detect the second triggering, in order to distinguish this from the noise of the control error without a doubt.

The last described procedure seems to be the other one consider both at first, but there are cases constructible where this strategy fails. It It is therefore advisable to use the second and third options to determine the changeover signal RT, possibly also all to combine three methods.

The complete state graph with the switchover between the two cycles shown individually in FIG. 3 is shown in FIG. 4. Both in FIG. 3 and in FIG. 4, an arbitrary numbering of the individual states has been carried out in the individual state graphs of the cycles in the upper left field.

Although the state graph according to FIG. 4 was set up by considering the counter-voltage, voltage measurement variables do not occur. With the specified switching control, a uniform load of the individual valves and the cheapest choice of actuator voltage is ensured.

The switching frequency can be selected by choosing the width of the influence first tolerance band Δi₁. One is conceivable automatic adaptation of this hysteresis width to Setting a desired switching frequency.

The switching control can be implemented very easily with a digital circuit (possibly in PAL or EPLD technology).  

FIG. 5 shows a four-quadrant actuator fed from an AC voltage source N using a three-stage technique. The individual thyristors and free-wheeling diodes of the two branches 1 and 2 are not described in more detail here. On the DC voltage side, two DC voltages u _d1 , u _d2 are present on two (intermediate circuit) capacitors C1 and C2. Here, too, the GTO thyristors can advantageously be replaced by IGBT valves.

Compared to a four-quadrant actuator in two-stage technology, with an actuator in three-stage technology according to FIG. 5, more switching states can be mastered: each branch 1 , 2 can assume three switching states (-, 0, +); there are 9 switching states for the actuator as a whole. The following table shows the dependency of the actuator voltage u _s on the actuating commands _S 1 and _S 2

The previously described design technique of the current switching regulator for the two-stage four-quadrant actuator can be applied here accordingly. First of all, the desired pulse pattern that the switching control should generate must be designed. Again, the lowest possible current ripple in order to achieve that of the available voltages Steller _s u in each case only the two are to be used, the _n are closest to the counter voltage u. Under the simplifying assumption that both _{DC link} voltages are equal (u _d1 = u _d2 = u _d / 2), the four-quadrant controller can switch five different voltages (-u _d , u _d / 2, 0, u _d / 2, u _d ) . Accordingly, pulse patterns are to be defined for four areas B1 to B4 of the counter voltage and _n . Various possible pulse patterns are shown in FIGS . 6a, 6b, 6c. The pulse patterns are each designed so that all valves of the four-quadrant actuator and the two intermediate circuits are loaded evenly. The different pulse patterns can be assigned to the areas as follows:

Range B1: (-u _d , -u _d / 2): pulse pattern P15
Range B2: (-u _d / 2, 0): pulse pattern P11 or P13
Range B3: (0, u _d / 2): pulse pattern P12 or P14
Area B4: (u _d / 2, u _d ): pulse pattern P16

Two different pulse patterns can be used for areas B2 and B3. Both variants have problems with minimum pulse widths: The pulse patterns P11 and P12 are difficult to implement voltages just above u _d / 2 or just below u _d / 2, since an actuator branch must switch very short pulses here. The pulse patterns P13 and P14 can implement these voltages without problems, but in turn have the same problem with voltages around 0. It is therefore desirable to master both variants equally. First, however, the pulse patterns P11 and P12 should be selected; the pulse patterns P13 and P14 will be incorporated later.

The cycles for the four areas B1 to B4, which are shown in FIG. 7, are thus fixed. Here, too, it is important to consider controller states that occur several times within a cycle or in different cycles as separate states.

The change between the cycles can be triggered by the signals RT + and RT-, similar to the two-stage four-quadrant controller. When changing the cycle, the status in the new cycle is to be jumped to, which can be reached with minimal switching of the actuator. In addition, the problem of the minimum pulse times during the cycle changes can be taken into account, if possible that the actuator branch that switched last in the old cycle should not switch after the cycle change. Fig. 8 shows the state graph with the thus constructed transitions between cycles of switching states. The minimum pulse times cannot be taken into account only for the two transitions from state 12 (+0) with the RT + signal and from state 16 (-0) with the RT- signal.

For the transitions, instead of the states selected in FIG. 8, the following could also be jumped to in the respective new cycle. This could save a switchover, since after a transition triggered by the RT + condition, no change is made to the actuator voltage and thus the next transition takes place immediately due to the still existing R + condition
(For example 12 → 4 instead of 12 → 3 → 4 as in Fig. 8).

With regard to the implementation effort, however selected variant as cheaper.

In contrast to the switching regulator for the two-stage four-quadrant controller, it is possible with the three-stage four-quadrant controller that the signals RT + and RT- not only trigger the transition to the next neighboring cycle, but immediately switch to other cycles. For example, switching from state 2 with R- to state 3 takes place. If the signal R- is present for a sufficiently long time, the signal RT- is set and there is immediately a chain of switches, namely state 3 → state 12 → state 5 → state 17 → state 18 → state 23 → state 24. This is avoided by first resetting the RT signal after a switch to another cycle and restarting the timer. If a control error signal is still present after the time T or T _w has elapsed again, the signal RT is set again and changed to the next cycle. In Fig. 9 a switch from one cycle to another - as already briefly mentioned for the two-stage four-quadrant controller - is shown on the basis of the time profile of the current control error Δi and the voltages u _s and u _n and the signals R +, R-, RT.

This strategy for switching between the cycles of the individual switching states generally works reliably. However, if the external counter voltage u _n = 0, limit cycles can be excited by a jump in the current setpoint, as shown in FIG. 10: By a jump in the setpoint voltage i _w, the current i leaves the (first) tolerance band shown in broken lines. This immediately reduces the actuator voltage by one step. However, if the current has not reached the tolerance band again before the time T has elapsed, the voltage is reduced again, triggered by the RT signal. At some point the tolerance band is reached again, but now the current - driven by the smallest possible actuator voltage - reaches the upper limit of the tolerance band. Until the current returns to the tolerance band, the voltage was increased several times by the RT pulses up to the maximum value. The process is then repeated at the lower limit of the tolerance band.

The limit cycle described can be prevented by taking into account the sign of the slope of the current control error Δi in addition to the control error signals R + and R-:
If there is still a control error (signal R +), but the current control error already drops, the signal RT must be prevented in order to prevent another cycle change and thus the occurrence of the limit cycle.

Alternatively, the filtering of the current control error is also possible conceivable via a retaining link.

Such a limit cycle can only be very set small counter voltages. When operating the Four-quadrant controller on sinusoidal mains voltage can only a current setpoint change in the voltage zero crossing trigger a limit cycle, but with increasing Voltage quickly disappears.

As mentioned above, with the selected pulse patterns P11 and P12 there is the problem of the minimum pulse widths, which could be avoided by supplementing the pulse patterns P13 and P14. The pulse patterns P13 and P14 but may be generated P11 and P12 by variation of the pulse pattern by the respective cycles in the states of 7, 11, 15 are skipped, 19 (see. Fig. 6b and Fig. 7). The skipping of these states can be controlled by a signal MT, which indicates whether the respective state has persisted longer than the minimum pulse time of the power semiconductor switch of the four-quadrant actuator without the presence of a control error ( FIG. 11). If this is the case for states 6, 10, 14, 18, the following states can be skipped in the respective cycle. However, if a control error occurs in states 6, 10, 14, 18 before this period, the original cycle of the pulse patterns P11 and P12 is run through.

The DC link voltage is regulated in a two-stage four-quadrant controller in a control loop that is superimposed on the current control. With the three-stage, four-quadrant controller, two intermediate circuit voltages must be regulated. However, the current control is also only a one-size control for the three-stage four-quadrant controller, i.e. the overlaid control is only provided with one manipulated variable - the current setpoint. With only one manipulated variable, a higher-level control cannot control two controlled variables. The superimposed voltage control can regulate the total intermediate circuit voltage (u _d = u _d1 + u _d2 ) as with the two-stage four-quadrant controller. Deviations between the two intermediate _{circuit voltages} u _d1 , u _d2 , on the other hand, must be corrected in the lower-level control loop.

This task can be solved relatively easily by expanding the state graph. The selected cycles of the switching states can be modified such that instead of an alternating load on the intermediate circuits, an intermediate circuit is loaded or relieved several times in order to compensate for voltage asymmetries. In Fig. 12 this is taken into account by the conditions according to the signals U + and U- initiated transitions.

For example, these conditions can be as follows To be defined:

Claims (13)

1. A method for creating control commands for the power semiconductor switch of a four-quadrant actuator acted upon with a single-phase mains voltage, characterized in that the control commands (S₁, S₂) for a positive and for a negative mains voltage (u _n ) as a cyclical sequence of switching states of the power semiconductor scarf ter (T11, T12, T21, T22) according to a desired pulse pattern that the transition from one switching state to the cyclically neighboring switching state is made when the control error of the current flowing through the four-quadrant current (i) one of the two limit values one in its A wide, predeterminable (first) tolerance band for the current control error is reached and that the transition between the cyclical sequences of switching states when the mains voltage (u _n ) changes sign is controlled by a signal (RT +, RT-) derived from the time course of the current control error. 2. The method according to claim 1, characterized in that a switchover between the cyclical sequences of switching states is carried out when the mains voltage (u _n ) changes sign when the current control error reaches the limits of a second tolerance band which is wider than the first tolerance band for the current control error. 3. The method according to claim 1, characterized in that a switchover between the cyclic sequences of switching states is carried out when the mains voltage (u _n ) changes sign when the current control error remains outside the (first) tolerance band for the current control error for a predetermined time. 4. The method according to claim 1, characterized in that a switchover between the cyclical sequences of switching states is carried out with a change of sign of the mains voltage (u _n ) when the current control error after a predetermined time for the second time the same limit value of the (first) tolerance band reached for the current control error. 5. The method according to claim 1, marked by a combination of those in claims 2 to 4 labeled procedures. 6. The method according to any one of claims 1 to 5, characterized in that in a three-stage four-quadrant controller between the several possible to achieve a certain desired pulse pattern, cyclical sequences of switching states of the power semiconductor switch is selected such that a new switching state always with minimal possible switching of the Power semiconductor switch is reached ( Fig. 5). 7. The method according to any one of claims 1 to 6, characterized in that in a three-stage four-quadrant for switching between the cyclical sequences of switching states that actuator branch ( 1, 2 ) is not switched as the next, which was switched last in the previous cycle is ( Fig. 5). 8. The method according to any one of claims 1 to 7, characterized in that in a three-stage four-quadrant controller, the transition between individual cyclic sequences is always made only after a predeterminable period of time (T _w ) that begins with each transition. 9. The method according to any one of claims 1 to 8, characterized, that with a three-stage four-quadrant controller for a transition from a switching state to cyclical neighboring switching state in addition to reaching a of the two limit values of the (first) tolerance band due to the current control error also the sign the slope of the current control error is taken into account becomes. 10. The method according to any one of claims 1 to 8, characterized, that in a three-stage four-quadrant actuator Current control errors filtered via a lead element becomes. 11. The method according to any one of claims 1 to 10, characterized, that with a three-stage four-quadrant actuator individual switching states within a cycle are skipped if the current control error causes a of the two limit values of the (first) tolerance band not reached during a period that longer is than that for the power semiconductor switch necessary minimum pulse time. 12. The method according to any one of claims 1 to 11, characterized, that with a three-stage four-quadrant controller  cyclical consequences of the switching states unevenly the DC circuits on the three-stage Four quadrant controllers are distributed. 13. The method according to any one of claims 1 to 12, characterized by an automatic adaptation of the Width of the (first) tolerance band.