DE1269177B - Electronic counter circuit with magnetic cores and transistors - Google Patents

Description

Electronic counting circuit with magnetic cores and transistors Die The invention relates to an electronic counting circuit, particularly for use in electronic computing or control systems with magnetic cores with approximately rectangular hysteresis curve and transistors work.

Such counting circuits must be adapted to the conditions in such Systems used to be optimally adapted. This results in the following Conditions: 1. The signals to be counted are pulses generated by switching of a magnetic core and are able to turn on a transistor in a known way from the idle state, in which only a small residual collector current flows to switch to the working state in which a large collector current flows.

2. The output signals of the counting unit must have the same properties have like the input signals and are only allowed to use a certain, after have precisely limited time lag above.

There are already counting circuits known which these conditions meet, but they require a relatively high cost of components. An electronic counting circuit working as a bistable multivibrator is known, in which the bistable element consists of two magnetic cores and a transistor and two Resistance exists. However, this known arrangement requires a guarantee a reliable function exactly the same, i.e. in pairs selected magnetic cores, because otherwise the compensation of the output signal at the first input pulse will not can be achieved with certainty.

It is therefore an object of the invention to provide a counting circuit for electronic To create computing or control systems, in which to the tolerances of the used therein Switching elements are made only low requirements, so that the selection of magnetic cores and transistors used is not critical. Furthermore, the possibility be given to put together any counters for such systems from this circuit.

In an electronic counting circuit in which two transistors and two magnetic cores with an approximately rectangular hysteresis curve are connected in such a way that that when the first transistor is turned on by an input pulse, its collector current one winding of the first core in the "L" direction and one winding of the second core flows through in the "0" direction, whereby the first core is set in the "L" state and the second core remains in the "0" state and in which the first core is replaced by a is read into the »0« state via a further winding supplied clock pulse, wherein an output signal is generated at a third winding which is used for writing Turning on the second transistor serving for the second core will accomplish this task solved that according to the invention, the collector current generated by an input pulse of the first transistor reads the second core if it was previously in the "L" state located, with the pulse appearing on its output winding another transistor controls whose collector current flows through another winding of the first core, so that the setting of the first kernel in the "L" state is prevented.

It is advantageous if the collector current of the further transistor also flows through a further winding of the second core, so that in addition the reading process of the second core is accelerated.

Be useful for writing to the first core and reading of the second core two separate transistors are provided, which are of different, simultaneous incoming input signals can be controlled.

The output signal of the first core can also be used for presetting if necessary further counting units connected in a chain are used. In this case it is advantageous to to provide a further transistor for presetting the counting unit, its Collector current is passed through the same winding of the second core as the one for Describing the second core required power.

In the counting circuit according to the invention, the output signal is the The counter is delayed by a very short time compared to the input signal opposite to the switching time of the cores used is negligible. It also emerges the advantage that the switching cores used compared to the known ones Counting circuits with magnetic cores only have low requirements in terms of tolerances of their data and the squareness of their hysteresis loop. The tolerances of the transistors used can also be relatively large, since the required switching times are achieved by suitable dimensioning of the number of turns of the cores can be largely influenced.

Another advantage of the counting circuit according to the invention is that that from the counting units according to the invention by chain connection and feedback Counters with any high counting volume can be built, their properties are only slightly worse than those of the individual counting unit.

Further details of the counting circuit according to the invention are given of the figures, of which F i g..1 a counting circuit designed according to the invention and F i g. 2 a decimal counter made up of several such counting units shows.

In the circuit according to FIG. 1 the pulses to be counted become one Input terminal 1 supplied. This turns on a transistor 2, and it comes a current flow from the ground point via the transistor 2, a resistor 3, winding 4 of a magnetic core 5, winding 6 of a second magnetic core 7 after the negative Pole 8 of a voltage source comes about. Cores 5 and 7 were both previously in the "0" state. The first input pulse sets core 5 to the »L« state, while core 7 remains in the "0" state.

After the input pulse, a clock pulse, which is fed to a winding 9 of the core 5, reads it to "0". As a result, an output pulse appears on a winding 10 , which controls a second transistor 11 and causes a current to flow through a resistor 12 and a winding 13 of the core 7 to the negative pole 8 of the voltage source, so that the core 7 is set to the "L" state will. Core 5, on the other hand, is now in the "0" state. Another impulse at input 1 brings about a current flow via transistor 2, resistor 3, winding 4 on core 5, winding 6 on core 7 to the negative pole 8 of the voltage source, which now causes the core 7, which is in the "L" state, to follow - "0" is read, so that - an output signal occurs on a winding 14. This can be taken from a terminal 15 and appears with every second input pulse. At the same time, the output signal controls a further transistor 16 conductive, so that a current flows through a resistor 17 and a winding 18 of the core 5 and a winding 6 of the core 7 in the direction that the setting of the core 5 is caused by the current flowing in the winding is prevented. After the second input pulse, both cores are again in the "0" state. The current flowing through the winding 18 is simultaneously conducted through the winding 6 of the core 7 in order to increase the reading current for this core and to ensure reliable reading. This measure is not absolutely necessary for the functioning of the counter, ie the current can also be conducted via the transistor 16, the resistor 17 and the winding 18 of the core 5 directly to the negative pole 8 of the voltage source.

In some cases it is useful to describe the core 5 via winding 4 and reading the core 7 via winding 6 with two separate transistors 2 and 2a perform the two different input signals arriving at the same time 1 and la can be controlled. In this case the connection 22-23 is broken, Point 22 placed on the operating voltage 8 and the additional transistor 2a over an additional resistor 3 a placed at point 23.

The circuit also contains an output terminal 19 through which the signal read from core 5 by means of a clock pulse can be picked up, and an input terminal 20 via which a transistor 21 can be turned on. This is via the transistor 21, resistor 12 and winding 13 on core 7 a Pre-setting of the counting unit possible. B. for the construction of decadic counters is required.

F i g. 2 shows, as an exemplary embodiment, one constructed from according to the invention Decimal counter composed of counting units. This consists of four counting units Zl, Z2, Z3 and Z4, each of which corresponds to the circuit according to FIG. 1 corresponds.

A pulse appearing at terminal 15 after the second input pulse at terminal 1 is used to control input 101 of the counting unit Z2, so that after a total of four input pulses at terminal 1 an output pulse is generated at terminal 115, etc. After the eighth input pulse at terminal 1, the core becomes core 305 of the counting unit Z 4 is set. Its output signal on winding 310 now sets core 307 of counting unit Z 4 as well as cores 107 and 207 of counting units Z2 and Z3 via feedback lines 30 and 31. As a result, after the eighth input pulse, cores 7 of counting units Z2, Z3 and are located Z4 in the "L" state, which corresponds to the dual number 14 (OLLL). The ninth input pulse sets the core 7 of the counter unit Z1 to "L", so that with the tenth pulse all units are read and an output signal appears at terminal 315. Of course, it is possible to achieve any reduction ratio by arranging the return lines differently. With four counting units, z. B. a maximum ratio of 1: 16, with three units a ratio of 1: 8 can be achieved.

Claims (5)

Claims: 1. Electronic counting circuit in which two transistors and two magnetic cores with an approximately rectangular hysteresis curve are connected in such a way that that when the first transistor is turned on by an input pulse, its collector current one winding of the first core in the "L" direction and one winding of the second core flows through in the "0" direction, whereby the first core is set in the "L" state and the second core remains in the "0" state, and in which the first core is replaced by a is read into the »0« state via a further winding supplied clock pulse, wherein an output signal is generated at a third winding which is used for writing of the second core serving second transistor turns on, d a d u r c h g e k e n n -z e i c h n e t that the generated by an input pulse Collector current of the first transistor (2) reads the second core (7) when this was previously in the "L" state, with the one occurring on its output winding (14) Pulse controls another transistor (16) whose collector current is another Winding (18) of the first core (5) flows through, so that the setting of the first core (5) in the "L" state is prevented. 2. Electronic counting circuit according to claim 1, characterized in that the collector current of the further transistor (16) also another winding (6) of the second core (7) flows through, so that in addition the reading process of the second core (7) is accelerated. 3. Electronic counting circuit according to claim 1 or 2, characterized in that for the writing of the first Core (5) and reading the second core (7) two separate transistors (2; 2a) are provided by different, simultaneously arriving input signals can be controlled. 4. Electronic counting circuit according to spoke 1, characterized in that that the output signal of the first core (5) for presetting further, in chain switched counting units is used. 5. Electronic counting circuit according to claim 1 and 4, characterized in that a further one for presetting the counting unit Transistor (21) is provided, the collector current of which via the same winding (13) of the second core (7) is conducted like that required for writing the second core Current. Documents considered: German Auslegeschrift No. 1096 412.