DE10361079A1 - Timing member for evaluating signal condition for monitoring and evaluating position switches for lasers, e.g. in robot treatment cells for car body treating - Google Patents

Abstract

Time member (10) evaluates signal state, e.g. safety position and working position of operating laser source etc. Logic unit (L1,2) evaluates signal state and energizes release path (20) via output plane (18) when first signal state appears. Logic unit energizes timer (T1,2) which, at change into second state, can be directed into second signal state, i.e. in state, taking over energizing of release path for preset time period. Clock generator (TG1,2) is controlled by logic unit, while its connection and function is specified. Independent claims are included for timing member testing method.

Description

The Invention relates to a timing element according to the preambles of claims 1 or 3 and a method for testing the timer according to General terms of the claims 9 or 10.

On Timer of the type described above is used for monitoring, for example and evaluation of position switches used, for example mark the position of a deflecting mirror for a laser beam.

According to the prior art, there are two types of laser beams, which are so-called CO ₂ lasers or a YAG laser. The lasers are used, for example, in robot processing cells for car body processing in the automotive industry.

With the CO ₂ laser, the energy for the laser beam is obtained from a gas mixture. If the laser beam does not perform any action, ie machining a workpiece, it is in a zero position, ie in a safe position. In the zero position, the laser is guided through a copper plate, which serves as a deflecting mirror, into a laser trap. The zero position or safe position of the deflection mirror is monitored with an initiator and at least one sensor designed as a positive opening position switch. If the deflecting mirror, which is driven by an electromagnet, for example, leaves the zero position, damping of the initiator is canceled and an opener of the position switch is opened. In addition, the position of the deflecting mirror is monitored by another initiator. The laser beam is released.

With the YAG laser, the energy for the laser beam is obtained from various crystals. The zero position of the deflection mirror is monitored in the YAG laser by a total of preferably four sensors designed as Hall sensors with an opening function. In contrast to the Co ₂ laser, the deflection mirror, which in this case is designed as a coated glass pane, is folded into the laser beam with a stepper motor. Two additional Hall sensors are installed to monitor the end position.

When machining workpieces, it can happen that the deflection mirrors fold back and forth within 250 ms for the CO ₂ laser and within 100 ms for the YAG laser. However, the short-term releases of the energy supply to the laser source mean that the switching elements controlling the energy supply, such as relays or contactors, are briefly switched on and off in succession, which leads to a large amount of contact wear.

If Timers of the aforementioned type constructed using discrete technology with a two-channel structure, each with a timer faulty timers a drift between the signals of the two channels occur which can lead to incorrect decisions.

From that starting from the present invention, the problem is based, a timer and a method for testing the timer disposal to provide, with which the functional reliability of the timer is increased.

The According to the invention the problem is solved by a Timing element with the characterizing features of claim 1 solved. The The timing element is characterized in that a clock for testing the divider stages of the timer is provided. The clock works with two frequencies, whereby a lower frequency is required, to expire a long time when the second signal state is present allow. The high frequency is used to test the timer and will switched on when the first signal state is present. The condition, The logic unit determines whether the high or low frequency is required controlled. The frequency of the clock generator applied to the timer determines the time period at which the output of the timer is switched on is. All divider stages of the timers are tested in each sequence.

Next the timer described in the single-channel embodiment described above can also be designed with two channels, each channel having a timer, a clock and a pulse comparator to compare the has pulses present at the output of the timer. Works one of the divider stages is not, then this is determined by pulse comparators and prevents the sequence from restarting.

According to one preferred embodiment provided that the output of the logic unit via a pulse shaper the start input of the timer. The pulse shaper expects a falling edge at its input and gives at the output a dynamic impulse. By dynamizing the circuit part errors are detected when static signals are present.

Of It is also provided that the output of the logic unit via a amplifier is connected to a switch-on input of the output level. The amplifier was inserted that are the output stages of the IC's of the logic units or the timer does not have enough current for the output level disposal can put.

It is also provided that the logic unit a memory unit for storing the errors occurring during the test of the timer and the comparison of the pulses. If an error occurs within a sequence, it is stored in the storage unit. If an error is stored in the error memory at the beginning of a new sequence, no sequence restart is triggered. The signal of the error memory must have changed the status once within a cycle, otherwise the sequence is interrupted or no sequence restart is triggered.

On The procedure for testing a timer is characterized by the characteristic Features of the claims 9 or 10 off.

The The peculiarity of the test procedure is that in each sequence Both timers can be tested in their full range of functions since go through all divider stages due to the high frequency of the clock become. Only switching off the timers triggers a sequence restart. If one of the timers remains on, no restart is triggered, whereby the other channel drops off. If an error or a drift of the timer stages is detected, this leads to switch off the starting level.

On Another advantage of the method is that the dynamization Most circuit parts will detect an error if static Signals are present.

Further Details, advantages and features of the invention do not arise only from the claims the characteristics to be extracted from these - and / or in combination - but also from the following description of one of the drawings preferred embodiment.

The only FIG. Shows a functional block diagram of a two-channel timer 10 , which is provided for evaluating signal states present at sensors. Each channel comprises a logic and error memory unit L1, L2 which is connected on the input side to one of the sensors pos. 1, pos. 2. There is also a coupling 12 provided between the logic and memory units L1, L2.

The logic error storage unit L1, L2 is on the output side with an output level 18 connected, which is a release path 20 controlled to release the energy supply of an item of equipment. The release path 20 consists of two make contacts connected in series.

Another output of the logic and error storage unit L1, L2 is on the one hand directly to the output level via an amplifier V1, V2 18 and on the other hand connected to the input of a pulse shaper I1, I2. Furthermore, the logic and error memory unit L1, L2 is directly connected on the output side to the pulse shaper I1, I2, which in turn controls a timer T1, T2 on the output side.

On further output of the logic and error storage unit L1, L2 is connected to a clock generator TG1, TG2, the output side with an input of the timer T1, T2 is connected.

On the output side, the timer T1, T2 is on the one hand with the output level via an amplifier V3, V4 18 to switch the release 20 connected and on the other hand to the input of a pulse comparator IV1, IV2 in order to be able to compare the output signals in the amplifiers V3, V4 of the two channels. It is provided that a coupling 22 is provided between the pulse comparators IV1, IV2 of the two channels. There is also feedback 24 . 26 provided by the pulse comparator IV1, IV2 to the logic and memory unit L1, L2.

The timer 10 In the exemplary embodiment described, the purpose is to switch off an item of equipment which, for example, emits a dangerous energy beam, such as a laser beam, if the latter has not returned to its position like a laser trap within an adjustable time T.

If the laser beam is in its safe position, ie laser trap, the sensors Pos1, Pos2 are closed. If no error from previous processing is stored in the logic and error memory unit L1, L2, the logic unit L1, L2 generates a start pulse with which the amplifier stages V1, V2 are controlled. These in turn control the starting level 18 and the release path 20 will be closed.

As soon as the processing machine driving the laser source, such as a robot, receives a command to process the workpiece, the laser beam is moved out of the safe position so that the position switches Pos1, Pos2 are opened. The changed signals are detected by the logic and error memory unit L1, L2 and the amplifiers V1, V2 are switched off, which triggers the pulse shapers I1, I2, which in turn control the timers T1, T2. The timers T1, T2 then switch on the amplifiers V3, V4, which likewise are the output level, for a predetermined time T in the range from 0.1 s T T 100 100 s 18 and thus the release path 20 unlock. As the amplifiers V1, V2 are switched off at the same time as the amplifiers V3 and V4 are switched on, the output level remains 18 controlled and the release path 20 closed.

During this Operating phase is the timer T1, T2 via the clock generator TG1, TG2 driven with a low frequency so that the time T expires.

As a rule, the laser beam returns to its safe position before the time T set in timers T1, T2 has elapsed, so that position switches Pos1, Pos2 are closed again before the set time has elapsed. Processing times can range from approx. 250 ms for CO ₂ lasers and approx. 100 ms for YAG lasers. This is recognized by the logic and error storage unit L1, L2 and passed on to the clock generator TG1, TG2, which control the timer T1, T2 with a high frequency in this operating phase. The high frequency is used to test the timers T1, T2. In this way, a complete cycle is run through each time the laser is actuated from the safe position and thus the timers T1, T2 are tested. When the time T set in the timers has elapsed, the amplifiers V3 and V4 are switched off. The falling edge present at the timer T1, T2 is fed to a pulse comparator IV1, IV2 via the amplifier V3, V4.

A pulse comparator IV1, IV2 generates a dynamic pulse from the falling edge of the timer T1, T2. This pulse is compared with the pulse of the other channel. If these impulses overlap, a sequence restart is triggered, with the release 20 remains closed. These impulses do not overlap because e.g. B. one of the timers is outside a tolerance, for example in the range of 1 to 10%, preferably 2 to 5%, then a sequence restart is prevented and the release path 20 open.

The method described ensures that the time stages of the timing element 10 For example, each time the mirror is folded back, ie when the position switches Pos1, Pos2 are operated within the set time, which can be, for example, in the range from 0.1 to 100 seconds. The release path 20 and thus the release relays will therefore not perform any switching operation in undisturbed operation, so that the switching contacts are protected.

After the time T preset in the timers T1, T2 has elapsed, the amplifiers V3, V4 are switched off. If at this point the position switches Pos1, Pos2 are only closed again after the set time has elapsed, the start condition "closed position switches" is not fulfilled, so that no sequence restart is triggered. This switches off the output level and the release 20 open.

To the logic and error storage unit L1, L2 it should be noted that contains these functions in order to be able to realize a sequence. If an error occurs within this sequence, it will be resolved in one Fault memory FS saved. Is at the beginning of a new sequence an error is stored in the error memory FS, no sequence start triggered. The error memory signal must occur once within a cycle changed the state, otherwise the sequence would be interrupted no sequence restart is triggered. This function block L1, L2 is therefore self-monitoring.

The Pulse shapers I1, I2 expect a falling edge at their input and give a dynamic impulse at their output. This means, that a differentiator is connected downstream on the output side.

The Clock generators TG1, TG2 work with two frequencies, one being low Frequency is needed around when open Let position buttons Pos1, Pos2 run for a long time. A high frequency is used to test the timers T1, T2 and is at closed position buttons Pos1, Pos2 switched on. The condition, decides whether the high or low frequency is required Logic and error memory unit L1, L2.

The Timers T1, T2 receive their start condition from the pulse shapers I1, I2, the applied frequency of the clock generators TG1, TG2 determines the period in which the output of the timer is switched on is. In each sequence, all divider stages of the timers T1, T2 tested. If one of the divider stages does not work, it will determined by the pulse comparator IV1, IV2 and a restart of Sequence prevented.

In the timing element according to the invention 10 it is a retriggerable circuit with an integrated test procedure for the timers T1, T2. ie, in each sequence both timers T1 and T2 are tested in their full range of functions, since all divider stages are run through. Only when the timers T1, T2 are switched off does a sequence restart start. If one of the timers T1, T2 remains switched on, then no restart is triggered and the other channel drops out. If an error or drift is detected, ie a time difference between the timer stages, this leads to the output level being switched off 18 , Due to the dynamization of most circuit parts such as the pulse shaper I1, I2, the pulse comparator IV1, IV2 and the logic and error memory unit L1, L2, errors are detected when static signals are present.

Claims (16)

Timer ( 10 ) for evaluating a signal state, wherein a first signal state is assigned to a first operating state such as a safe position and a second signal state is assigned to a second operating state such as the working position of an item of equipment such as a laser source, characterized by: - a logic unit (L1, L2) for evaluating the signal state and for actuation a release path ( 20 ) via an exit level ( 18 ) when the first signal state is present, - a timer (T1, T2) which can be controlled by the logic unit (L1, L2) and which can be controlled when changing from the first to the second signal state to an ON state, and the activation of the release path ( 20 ) for a predetermined period of time T, - a clock generator (TG1, TG2), which can be controlled by the logic unit (L1, L2) and is connected to a clock input of the timer (T1, T2), the timer after a change from the the first to the second signal state with a low frequency and after a change from the second to the first signal state until the timer (T1, T2) drops out with a high frequency for testing the timer. Timing element according to claim 1, characterized in that the timing element ( 10 ) has a first and a second channel for the redundant evaluation of the signal state, each channel comprising the logic unit, the timer and the clock generator and that a comparator (IV1, IV2) is provided for comparing output signals of the timers (T1, T2) of both channels , wherein an output signal of the timer is present at an input of the comparator (IV1, IV2) and an output of the comparison is connected to an input of the logic unit (L1, L2) in order to report an error in the comparison of the pulses, and wherein the comparators are coupled is. Timer ( 10 ) for evaluating a signal state, a first signal state being assigned to a first operating state such as a safe position and a second signal state being assigned to a second operating state such as the working position of an item of equipment such as a laser source, with a first and a second channel for redundant evaluation of the signal state and a common output level ( 18 ) to control an enable path ( 20 } for the equipment, characterized in that each channel comprises: - a logic unit (L1, L2) for evaluating the signal state and for controlling the release path ( 20 ) over the starting level ( 18 ) when the first signal state is present, the logic units (L1, L2) of both channels being coupled to one another, - a timer (T1, T2) which can be controlled by the logic unit (L1, L2) and when changing from the first to the second Signal state can be controlled into an ON state and the activation of the release path ( 20 ) for a predetermined period of time T, - a clock generator (TG1, TG2), which can be controlled by the logic unit (L1, L2) and is connected to a clock input of the timer (T1, T2), the timer after a change from the first to the second signal state with a low frequency and after a change from the second to the first signal state until the timers (T1, T2) drop out with a high frequency for testing the timers, - a comparator (IV1, IV2) for comparing Output signals of the timers (T1, T2) of both channels, an output signal of the timer being present at an input of the comparator (IV1, IV2) and an output of the comparison being connected to an input of the logic unit (L1, L2) in order to avoid a comparison error to communicate the impulses and a coupling of the comparators is provided. Timing element according to at least one of the preceding Expectations, characterized in that the first output of the logic unit (L1, L2) about a pulse shaper (I1, I2) with the start input of the timer (T1, T2) is connected. Timing element according to at least one of the preceding Expectations, characterized in that the output of the logic unit (L1, L2) via an amplifier (V1, V2) is connected to a switch-on input of the output level. Timing element according to at least one of the preceding Expectations, characterized in that the output of the timer (T1, T2) via a amplifier (V3, V4) is connected to the switch-on input of the output level. Timing element according to at least one of the preceding Expectations, characterized in that the logic unit (L1, L2) is a storage unit to save the while testing the timer and comparing the pulses occurring Has errors. Timing element according to at least one of the preceding Expectations, characterized in that the pulse shapers (I1, I2) have a dynamic Have output, the pulse shaper a falling edge at the input of the pulse shaper into a dynamic pulse at the output of the pulse shaper is deformable. Procedure for testing a timing element ( 10 ) for the evaluation of signal states, a first The signal state is assigned to a first operating state, such as a safe position, and a second signal state is assigned to a second operating state, such as the working state of an item of equipment, comprising the method steps: - generating a switch-on pulse for an enabling path ( 20 ) for supplying power to the equipment when the first signal state is present, - activating a timer (T1, T2) when changing from the first signal state to the second signal state, the activation of the release path ( 20 ) is taken over by the timer (T1, T2) for a predetermined period of time T, the timers (T1, T2) being tested during each sequence, by applying a low frequency when the second signal state is present and after a change in the signal state until If the timers (T1, T2) drop out at a high frequency, the timers (T1, T2) can be tested. Procedure for testing a timing element ( 10 ) for evaluating signal states, a first signal state being associated with a first operating state such as a safe position and a second signal state being associated with a second operating state such as the working state of an item of equipment, comprising the method steps: - generating a switch-on pulse for an enabling path ( 20 ) for supplying power to the equipment when the first signal state is present, - triggering a timer (T1, T2) in each channel when changing from the first signal state to the second signal state, the activation of the release path ( 20 ) is taken over by the timer (T1, T2) for a predetermined period of time T, the timers (T1, T2) being tested during each sequence, by applying a low frequency when the second signal state is present and after a change in the signal state until If the timers (T1, T2) fall off at a high frequency to test the timers (T1, T2), the timers (T1, T2) are switched off after the time period T has elapsed and the outputs at the timers (T1, T2 ) edges present on both channels, - restart of a sequence, ie release remains switched on if the pulses overlap within a specified tolerance or switch off the release path if the pulses do not overlap. A method according to claim 9 or 10, characterized in that that the timer (T1, T2) over a pulse shaper (I1, I2) is controlled at its output a dynamic impulse is present. A method according to claim 9 to 11, characterized in that when testing the timer (T1, T2) due to the high frequency all required divider stages of the Timers are run through. A method according to claim 9 to 12, characterized in that while testing the timers (T1, T2) and / or comparing the output pulses the timer (T1, T2) errors occurring, such as non-matching ones Impulses or drifts between the channels recognized and saved a sequence restart if there is an error is prevented. A method according to claim 9 to 13, characterized in that a sequence restart is only triggered if the signal of the Error memory changes its state once within a sequence. A method according to claim 9 to 14, characterized in that in each sequence both timers (T1, T2) in their full range of functions be tested, whereby the timers (T1, T2) only switch off Sequence restart triggers and the other channel drops, if one of the timers (T1, T2) always stays on. A method according to claim 9 to 15, characterized in that errors due to the application of static signals through dynamization of the output signals are recognized.