DE10359889A1 - Bridge field effect transistor memory cell has charge storage layer designed for selective charge carrier introduction or removal by application of given electrical potential - Google Patents

Abstract

A The fin field effect transistor memory cell includes first and second source / drain regions and a channel region therebetween, which source / drain and channel regions are formed in a semiconductor land. The memory cell contains a charge storage layer at least partially the semiconductor land is arranged, and a carbon material having gate region on at least a part of the charge storage layer, which is set up so that by means of applying specifiable electrical Potentials to the ridge field effect transistor memory cell in the Charge storage layer, electrical charge carriers selectively introducible or removable from it.

Description

The The invention relates to a land field effect transistor memory cell, a Land field effect transistor memory cell arrangement and a method for manufacturing a land field effect transistor memory cell.

in view of There is a need for rapid development in computer technology in high-density, low-power and nonvolatile memory, in particular for mobile Applications in the field of data storage.

Out In the prior art, a floating gate memory is known in the one above a gate insulating layer in a substrate integrated field effect transistor, an electrically conductive floating gate region is arranged, in which by means of Fowler Nordheim tunnels electrical charge carrier can be permanently introduced. by virtue of of the field effect is the value of the threshold voltage of one Transistor depends on it whether or not charge carriers are stored in the floating gate. Thus, in the presence or absence of electrical Charge carrier in the floating gate layer a memory information codable.

Indeed is for introducing electrical charge carriers in a floating gate one high voltage of typically 15V to 20V required. This can cause damage sensitive integrated components lead and is also energy-saving (e.g., low-power applications) or mobile applications (e.g., cellular phones, Personal Digital Assistant, PDA) unattractive.

at an NROM memory ("nitrided read only memory ") For example, a silicon nitride trapping layer is used as the gate insulating layer a field effect transistor used by means of Channel Hot Electron Injection (tunnels hotter Electrons) charge carriers permanently in the silicon nitride layer as a charge storage layer can be introduced. Typical programming voltages in this case are around 9V, and Write times of 150ns are achieved on a single cell.

Out [1] is an NROM memory cell is known in which in a transistor two bits of memory information can be stored.

A However, such NROM memory cell has the disadvantage of a high Power consumption on. Further, the scalability of NROM memory cells due to short channel effects, such as the "punch through" effect, especially for a channel length of typically below 200nm, bad. Furthermore is at a small width of transistors of NROM memory cells of the Reading current very small. Again, this is a continued scaling opposite.

There is a need for high-density data memories with storage densities of preferably at least 1 Gbit / cm ² . Memory cell arrangements known from the prior art are a NAND arrangement having planar floating gate memory cells or so-called "virtual ground arrays" with NROM memory cells for storing two bits of information per memory cell. Storage capacities of approximately 1 Gbit can be achieved with these memory cell arrangements. However, due to the poor scalability of these memory cell arrays, a continued increase in storage density is technologically difficult.

Of the The invention is based on the problem of providing a memory cell, which is still scalable to small dimensions.

The Problem is solved by a land field effect transistor memory cell, by a land field effect transistor memory cell arrangement and a method of fabricating a ridge field effect transistor memory cell solved with the features according to the independent claims.

The The ridge field effect transistor memory cell according to the invention contains a first and a second source / drain region and an intermediate one arranged channel region, which source / drain and channel regions are formed in a semiconductor land. Further, a charge storage layer provided at least partially disposed on the semiconductor land is. The land field effect transistor memory cell includes a Carbon material having gate area on at least one Part of the charge storage layer, wherein the charge storage layer set up such that by means of applying specifiable electrical Potentials to the ridge field effect transistor memory cell in the charge storage layer, electrical charge carriers selectively can be inserted or removed therefrom.

The The ridge field effect transistor memory cell arrangement according to the invention contains a plurality of land field effect transistor memory cells with the features described above.

In the method according to the invention for producing a ridge field effect transistor memory cell, a first and a second source / drain region and a channel region arranged therebetween are formed in a semiconductor ridge. Fer A charge storage layer is formed at least partially on the semiconductor land. A carbon material-having gate region is formed on at least a part of the charge storage layer. The charge storage layer is set up in such a way that, by applying predeterminable electrical potentials to the ridge field effect transistor memory cell, electrical charge carriers can be selectively introduced or removed from the charge storage layer into the charge storage layer.

A The basic idea of the invention can be seen in the fact that the gate region a land field effect transistor memory cell (or the word line area a land field effect transistor memory cell array) is formed of a carbonaceous material. With others In other words, carbonaceous material becomes between adjacent semiconductor lands or semiconductor fins introduced. The invention is the realization based on that when providing the gate region of a carbonaceous Material even with fins or webs, which has a very small dimension or have a very small distance from each other, spaces between neighboring fins safely and avoiding the electrical Controllability of the memory cell affecting air holes with material the gate area positively fill out.

at Fin-FET memory cells are at very high storage densities, for example with a distance of neighboring fins of 20nm and less, difficult Word line areas between the fins or bars without air gaps and with good electrical conductivity manufacture.

at Use of conventional metallic materials or doped poly-silicon for gate regions or word line areas In a land field effect transistor memory cell arrangement, such may occur Metal electrodes in the narrow spaces between adjacent ones Semiconductor fins not deposited in sufficiently good quality and sufficient conformity become. In accordance with the invention, fin field effect transistor memory cells are formed with gate regions or word line regions, which have carbon or consist of carbon is a Material for created the word line areas, even in the narrowest columns or cavities with dimensions of 10nm and less with homogeneous interface coverage can penetrate and even at low thicknesses a good electrical conductivity having. The inventively achieved Homogeneous coverage of the provided with the charge storage layer semiconductor ridges with the carbonaceous gate region causes when applied an electric voltage to the gate region by means of the field effect the electrical properties of the memory cell exactly controllable or are adjustable. This is also at high storage densities a perfect functioning the memory cell allows.

Consequently is a new invention possibility created, at short intervals of, for example, below 30nm between adjacent fins a low impedance, high quality and miniaturized electrical control cable for one To create transistor memory cell. Using carbon material for the Gate areas or word line areas can Even very narrow joints can be wetted with material. The carbon material also has good electrical conductivity even at low thicknesses on.

Therefore, with the land field effect transistor memory cell of the present invention, in a "virtual ground array" architecture, a high storage density of, for example, 8Gbit / cm ² and more is combined with a high readout rate.

experiments have shown that the carbon layer of the land field effect transistor memory cell according to the invention has good adhesion properties, in particular on a silicon oxide layer, so that an undesirable supersede such layers is avoided from each other. The carbon layer For example, using an oxygen plasma or Nitrogen plasma etching with high quality and reasonable effort. Further, the deposition is silicon nitride material (e.g., as a capping or passivation layer) on the carbon-containing layer technologically possible without problems.

at the ridge-effect transistor memory cell according to the invention is a high readout rate with high aspect ratios of the semiconductor fins allows. These read rates are better than conventional NAND memories. Under an aspect ratio will the ratio of height to width of the area between adjacent fins of a memory cell arrangement understood. Such a distance may be on the order of 10nm, the Height of one For example, the fin can be 50nm.

preferred Further developments of the invention will become apparent from the dependent claims.

The charge storage layer of the ridge field effect transistor memory cell can be embodied as an electrically insulating charge storage layer. Memory cells with an electrically insulating charge storage layer allow lower programming voltages than those with a floating gate. An electronically insulating charge storage layer can also be referred to as a trapping layer the, as clearly electrical charge carriers are trapped in the electrically insulating layer.

The Charge storage layer may according to the invention, for example, a silicon oxide-silicon nitride-silicon oxide layer sequence, Alumina, yttria, lanthana, hafnia, amorphous silicon, Tantalum oxide, titanium oxide, zirconium oxide, and / or an aluminate or consist of.

Of the Gate region of the ridge field effect transistor memory cell according to the invention or a word line area The land field effect transistor memory cell array may be made of carbon material consist.

Doping material may be incorporated into the carbon material to increase the electrical conductivity of the gate region. Boron, aluminum, indium, phosphorus or arsenic can be used as doping material, for example. Such dopant material may for example be introduced or injected into the gate region during the production of the carbonaceous gate region, for example by supplying an additional dopant-comprising precursor into the process chamber during a chemical vapor deposition (CVD) deposition process. Such an additional precursor for providing boron doping material is, for example, diborane (B ₂ H ₆ ).

Of the Semiconductor bridge can be made of a bulk silicon substrate or of a Silicon on insulator substrate may be formed. In other words can the memory cell according to the invention in bulk silicon technology or in SOI technology.

in the Further, the land field effect transistor memory cell arrangement according to the invention, the ridge field effect transistor memory cells according to the invention has, closer described. Embodiments of the ridge field effect transistor memory cell apply also for the land field effect transistor memory cell array and vice versa.

The Land field effect transistor memory cells of the land field effect transistor memory cell arrangement can essentially matrix-shaped be arranged.

Along a first direction arranged land field effect transistor memory cells can have common word line regions connected to the gate regions coupled to the associated land field effect transistor memory cells are made of the same material as the gate regions. Thus, vividly the gate areas and the word line regions of a row or column of land field effect transistor memory cells the memory cell array of a one-piece and one-carbon structure consist.

The The land field effect transistor memory cell arrangement can be used as a NAND memory cell arrangement be furnished. In this case, the Finns can essentially be arranged orthogonal to the word line areas extending. The word line areas can used as a mask for forming the source / drain regions of the ridge field effect transistor memory cells become. It is possible in NAND architecture, a semiconductor fin descriptive as part of the Bitleitung mitververwenden. Preferably are, however, at a distance of a predetermined number (typically eight or sixteen) of memory cells of a semiconductor fin vias formed by means of which a coupling of the source / drain regions with metallic Bit lines of a wiring level is realized.

The The ridge field effect transistor memory cell arrangement according to the invention can be set up in such a way that predefinable by means of applying electrical potentials to at least one gate region and at least a portion of the source / drain regions charge carriers into the charge storage layer a selected one Fin field effect transistor memory cell using Fowler-Nordheim tunnels are selectively introduced or removable therefrom.

alternative to the NAND memory cell arrangement, the ridge field effect transistor memory cell arrangement according to the invention can at least one first bitline region and at least one second bitline region wherein the first source / drain region of a respective ridge field effect transistor memory cell with an associated first bitline area and the second one Source / drain region a respective ridge field effect transistor memory cell having an associated one second bitline area is coupled. For example, you can such bit line areas in a wiring level above the gate areas or the word line areas may be provided, wherein a memory cell in a crossing region of a word and a bit line driven by an associated word line and is read out or programmed by means of allocated bit lines.

The first and second bit line regions may be arranged to extend substantially in a second direction, which second direction is arranged obliquely to the first direction. Preferably, the semiconductor fin is arranged substantially orthogonal to the word line or the gate regions coupled to one another. In this case, it is necessary to have the bit line areas in, for example, above the word line plane arranged obliquely to the word lines, for example, at a 45 ° angle. The first and second bit line regions may be straight or have a zigzag or sawtooth structure. If a bit line region is provided as a zigzag or sawtooth structure that extends obliquely to the word line regions substantially along the second extension direction, it is possible to have bit line regions having essentially the same length and thus substantially equal resistance form, with which source / drain regions of land field effect transistor memory cells can be controlled.

The Semiconductor fins of the land field effect transistor memory cells and the word line areas can be arranged to extend along a third direction, and first and second bit line areas may be along a fourth Direction be arranged extending, which third direction perpendicular is arranged to the fourth direction.

The The land field effect transistor memory cell arrangement can be set up in this way be that by applying predeterminable electrical potentials at least one word line area and at least a portion of the bit line areas charge carriers in the Charge storage layer in a selected land field effect transistor memory cell by means of tunneling hotter charge carrier are selectively introduced or removable therefrom. By tunneling hot Electrons or tunnels hotter Holes can with short writing times electrical charge carriers in the charge storage layer permanently introduced, wherein in these introduced electrical carriers the memory information is encoded.

The The described bridge field effect transistor memory cell arrangement can be used for Storing two bits of information in a land field effect transistor memory cell by introducing charge carriers into the charge storage layer in a boundary region between the first source / drain region and the channel region and in a boundary region between the second source / drain region and the channel area be configured of the respective ridge field effect transistor memory cell. Consequently the memory cell array of the invention is operable as a dual bit memory cell, so that a high-density semiconductor memory is provided.

The first and second bit line areas may be called virtual ground wirings accomplished be.

The Semiconductor ridges of adjacent ridge field effect transistors can be used in a distance of 10nm to 100nm, preferably at most 30nm, more preferably at the most 20nm or at most 10nm from each other. It is also at very small intervals between adjacent semiconductor fins possible, a gate region of sufficient conformity and quality from a carbonaceous one To create material.

Further may at least partially cover the word line areas be provided electrically insulating cover layer. A silicon nitride capping layer has particularly good material properties in combination with a carbon-containing word line region, in particular, a peeling off a safely avoided such cover layer.

The Topcoat may be in cavities between semiconductor lands covered with the word line region extend. Thus, the cover layer as a spacer or Decoupling element be used between adjacent fins, causing an undesirable crosstalk between adjacent memory cells is avoided. By means of the areas the cover layer between adjacent semiconductor fins is a mechanical decoupling realized adjacent memory cells.

in the Further, the method of the invention for fabricating a ridge field effect transistor memory cell. Embodiments of the ridge field effect transistor memory cell or the land field effect transistor memory cell arrangement also apply to the method for manufacturing a ridge field effect transistor memory cell and vice versa.

The carbon material of the gate region may be formed using a chemical vapor deposition (CVD) method. For example, methane (CH ₄ ), acetylene (C ₂ H ₂ ) or ethene (C ₂ H ₄ ) can be used to form the carbon material.

When Carbon source for forming the carbon material is suitable Particularly good methane gas as a precursor in a CVD process, since this little molecule especially good in the narrow spaces between adjacent semiconductor fins can penetrate. Using methane gas as precursor to To form the carbonaceous gate region, air holes are particularly safely avoided.

During the formation of the carbon material, a dopant-containing material may be supplied, which doping material such is directed that it increases the electrical conductivity of the gate region. For example, diborane may be added as a boron source for doping the carbonaceous material of the gate region, thereby achieving very homogeneous boron doping in the carbon material.

To In forming the carbon material, this may be an annealing process step be subjected. For example, the carbon material formed approximately two minutes in argon atmosphere and a temperature of typically 1000 to 1100 ° C, preferably 1050 ° C, treated become. By means of such an annealing process step, the ohmic resistance of the carbon layer typically by one Factor two and more are reduced. By means of the annealing process step Therefore, the material property of the gate region can be additionally improved.

For example, the following parameters may be used for a method of manufacturing the carbonaceous layer in a CVD process. As the gas for preconditioning, for example, hydrogen gas having a pressure between 10 ^-4 bar and 10 ^-2 bar, preferably 10 ^-3 bar can be used. Further, methane may be supplied as a carbon source to form the carbonaceous layer at a pressure between 0.2 bar and 0.7 bar, preferably 0.6 bar. The operating temperature during the manufacturing process is typically between 950 ° C and 1000 ° C. The thickness of the carbon layer is adjustable by predetermining the processing time.

For producing the ridge field effect transistor memory cell according to the invention, energy can be supplied by means of an electromagnetic radiation source. As an alternative to the conventional heating of a CVD apparatus, the process chamber can thus be heated to 800 ° C. with a clearly photonic heater, that is to say an electromagnetic radiation source as energy source. At a pressure between 10 ^-3 bar and 10 ^-2 bar, preferably 3.3 10 ^-3 bar, hydrogen and between 10 ^-3 bar and 10 ^-1 bar, preferably 10 ^-2 bar methane, then the carbon layer is produced.

The Carbon material can be deposited and used a plasma etching process for forming the gate region be structured. Preferably, for the plasma etching method used a hydrogen plasma or oxygen plasma etching process.

embodiments The invention is illustrated in the figures and will be discussed below explained in more detail. It demonstrate:

1 a cross-sectional view of a ridge field effect transistor memory cell arrangement according to a first embodiment of the invention,

2 in the 1 shown land field effect transistor memory cell arrangement in an operating state in which in the charge storage layer electrical charge carriers are introduced,

3A to 3D Layer sequences at different times during a method for producing the ridge field effect transistor memory cell arrangement 1 .

4 FIG. 4 is a layout plan view of a land field effect transistor memory cell array according to the first embodiment of the invention; FIG.

5 FIG. 4 is a layout plan view of a land field effect transistor memory cell array according to a second embodiment of the invention; FIG.

6 a land field effect transistor memory cell arrangement according to a third embodiment of the invention, with sawtooth bit lines,

7 FIG. 2 is a cross-sectional view of a land field effect transistor memory cell array according to a fourth embodiment of the invention; FIG.

8th a layout plan view of a land field effect transistor memory cell array according to the fourth embodiment of the invention.

Same or similar Components in different figures are given the same reference numerals Mistake.

The Representations in the figures are schematic and not to scale.

Furthermore, the functionality of in 1 shown land field effect transistor memory cell arrangement 100 described according to a first embodiment of the invention.

In 1 are a first land field effect transistor memory cell 110 and a second land field effect transistor memory cell 111 shown.

The land field effect transistor memory cell len arrangement 100 is on a silicon substrate 101 educated. On the silicon substrate 101 is a buried silicon oxide layer 102 is formed. In other words, the land field effect transistor memory cell array 100 formed from an SOI substrate, which is the silicon substrate 101 , the buried silicon oxide layer 102 and one on the buried silicon oxide layer 102 arranged silicon layer, from the in 1 due to the processing for fabricating the memory cell array 100 only the areas 105 available.

Each of the land field effect transistor memory cells 110 . 111 has a first and second source / drain region, which in 1 are not recognizable. In the cross-sectional view of 1 is a channel area 105 shown. The first and second source / drain regions are illustratively in line with the paper plane of FIG 1 vertical direction above the paper level or below the paper plane as n-doped regions of the silicon layer of the SOI substrate provided.

Each channel area 105 together with the two associated source / drain regions, forms a silicon fin or a silicon fin which is perpendicular to the paper plane of FIG 1 is arranged running. On each silicon land is an ONO charge storage layer sequence 106 educated. The ONO charge storage layer sequence 106 consists of two silicon oxide layers and a silicon nitride layer arranged between them as a trapping layer for introducing electrical charge carriers.

On the charge barrier 106 is a carbon wordline 107 applied. Illustratively, those sections form the carbon word line 107 pointing to a respective channel area 105 arranged region of the charge storage layer 106 cover the gate region of the associated land field effect transistor memory cell 110 respectively. 111 , The distance between adjacent silicon fins is in the range of 30nm or less, as in FIG 2 shown. Despite this very small distance between adjacent semiconductor fins, the carbon layer can 107 very compliant and avoiding air holes on the charge storage layer 106 be deposited.

The carbon wordline 107 is with a silicon nitride capping layer 108 coated, which extends into areas between the Finns. Silicon nitride has very good adhesion properties to carbon and, due to the post-like spacers in the carbon material-covered trenches between adjacent fins, causes mechanical decoupling between adjacent land field effect transistor memory cells 110 . 111 , At very close spaces between the fins, the silicon nitride material does not penetrate into the trench, as the carbon material completely fills the trenches.

In 2 is the land field effect transistor memory cell arrangement 100 shown in an operating state in which electrical charge carriers 200 , electrons, into the silicon oxide trapping layer of the ONO charge storage layer sequence 106 are introduced. In these introduced electrons is the in the memory cells 110 . 111 stored information encoded.

In one embodiment of the ridge field effect transistor memory cell arrangement in NAND architecture, the electrical charge carriers 200 into the ONO charge storage layer sequence 106 introduced by means of Fowler-Nordheim tunnels. In one embodiment of the fin field effect transistor memory cell arrangement 100 As a dual-bit memory cell arrangement, the electrical charge carriers 200 into the ONO charge storage layer sequence 106 introduced by tunneling hot carrier.

The electric charge carriers 200 in the ONO charge storage layer sequence 106 Effectively have the effect of a gate voltage as applied to a carbon word line 107 can be created. Because the electrical charge carriers 200 affect similar to one at the gate area 107 applied electrical voltage the electrical conductivity of the channel area 105 , Thus, at a fixed voltage between the two source / drain regions of a respective ridge field effect transistor memory cell 110 . 111 the value of the electric current flow between the two source / drain regions depending on whether in the ONO charge storage layer sequence 106 Charge carriers are introduced or not. Thus, in the electric charge carriers 200 the storage information of the respective land field effect transistor memory cell 110 . 111 coded.

In the following, reference is made to 3A to 3D a method of making the in 1 shown land field effect transistor memory cell arrangement 100 described.

The field effect transistor memory cell arrangement 100 is starting from an SOI substrate 302 ("Silicon-on-Insulator") formed, which consists of silicon substrate 101 The buried silicon oxide layer is buried thereon 102 and a silicon layer disposed thereon 301 consists. Alternative to an SOI wafer 302 as a starting material, a bulk wafer with a suitable well doping can also be used.

To the in 3B Layer sequence shown 310 The silicon layer is obtained by using a lithography and an etching method 301 the sequence of layers 300 structured so that at a distance of less than 30nm apart from each other first and second silicon fins 311 . 312 be formed. For this purpose, first a photoresist layer (not shown) on the silicon layer 301 applied and patterned using an etching process. After etching the areas between adjacent fins 311 . 312 the photoresist layer is removed ("stripped") from the surface of the layer sequence.

To the in 3C Layer sequence shown 320 becomes an ONO charge storage layer sequence 106 on the silicon fins 311 . 312 applied. For this purpose, a first silicon oxide sub-layer is first deposited, a silicon nitride sub-layer is deposited on the first silicon oxide sub-layer, and a second silicon oxide sub-layer is deposited on the silicon nitride sub-layer. The two silicon oxide sublayers and the interposed silicon nitride sublayer together form the ONO charge storage layer sequence 106 , On the ONO charge storage layer sequence 106 becomes a carbon layer using a CVD ("chemical vapor deposition") method 321 for forming gate and wordline regions, respectively.

To the in 3D Layer sequence shown 330 is obtained by using a lithography and a plasma etching (oxygen plasma etching), the carbon layer 321 structured such that thereby the carbon word line 107 is formed. In a further method step, the carbon word lines 107 as an implantation mask when introducing doping material of the n-type conductivity in such areas of the silicon fins 311 . 312 which form first and second source / drain regions of the fin field effect transistor memory cells.

Subsequently, the thus obtained layer sequence with a silicon nitride cover layer 108 covered. Alternatively, a TEOS layer sequence ("tetraethylorthosilicate") can be formed as a cover layer.

Order from the in 3D shown layer sequence 330 to the land field effect transistor memory cell array 100 is reached in processing levels above the top layer 108 the back-end area is processed, in particular metallization levels formed (not shown). The manner of forming the back-end region depends on the configuration of the ridge field effect transistor memory cell arrangement as a NAND memory cell arrangement or as a dual-bit memory cell arrangement.

In the following, reference is made to 4 a layout plan view of a ridge field effect transistor memory cell array 400 described according to a second embodiment of the invention. The land field effect transistor memory cell arrangement 400 is executed in NAND architecture (non-AND architecture). In the 1 shown cross-sectional view is along the in 4 recorded line AA 'recorded.

As in 4 shown, the semiconductor fins run 311 . 312 perpendicular to the carbon word lines 107 , In every crossing area of a silicon fin 311 . 312 with a carbon word line 107 a ridge field effect transistor memory cell is arranged. As in 4 1, the extension of a fin field effect transistor memory cell is shown in FIG 4 horizontal or vertical direction respectively 2F, where F represents the minimum achievable in a technology generation structure dimension. Thus, the land field effect transistor memory cells of the invention are formed as 4F ² area memory cells. The areas of silicon fins 311 . 312 covered by a wordline covering 107 are free, are formed as n-doped regions. In particular, a first source / drain region 401 and a second source / drain region 402 the in 1 shown first land field effect transistor memory cell 110 shown.

The web course direction 403 is orthogonal to the word-line direction 109 ,

In 4 not shown are the select transistors and the plane of the global bitlines which typically contact the respective source / drain regions at a distance of eight to sixteen memory cells using vias. External control, programming or reading voltages can be applied to such low-resistance bit lines. In each field effect transistor memory cell of the memory cell array 400 is an information of one bit storable.

In the following, reference is made to 5 a land field effect transistor memory cell arrangement 500 described according to a third embodiment of the invention. 5 shows a layout plan view of the memory cell array 500 , In the 1 shown cross-sectional view is along the in 5 recorded line BB 'recorded. In other words, the cross-sectional view is off 1 at the in 4 and 5 The memory cell arrangements shown in FIG. 2 are identical, whereas the interconnection architecture is identical in the memory cell arrangements 400 and 500 is different, how out 4 and 5 evident.

The memory cell arrangement 500 is designed as a dual-bit memory cell arrangement in which in each memory cell information of two bits can be stored. Due to the design of the memory cell array 500 As a dual bit memory cell arrangement, it is necessary to use the source / drain regions of the fin field effect transistor memory cells of the memory cell arrangement 500 to contact with bitlines over which electrical control and read-out signals can be applied according to a "virtual ground array" architecture. For this purpose, one above the paper level of 5 arranged plurality of bit lines formed with respective source / drain regions of the ridge field effect transistor memory cell array 500 be coupled.

To form such bit lines, starting from 3D the silicon nitride cap layer 108 a lithography and an etching process, whereby bitline contacts are etched as through holes and filled with titanium nitride and tungsten material. In a metallization level arranged above the bit lines are formed by first depositing a whole-area metallization layer and structuring it using an additional lithography and an additional etching process. Subsequently, the back-end contacting can take place.

As in 5 shown schematically are in each of the ridge field effect transistor memory cells 110 . 111 the land field effect transistor memory cell arrangement 500 each two bits of information storable by in a first charge storage area 501 and a second charge storage area 502 a respective memory cell independent of each other, electrical charge carriers can be introduced or not. The first charge storage area 501 is in a boundary between a first source / drain region 401 a memory cell 110 and the channel area 105 the memory cell arranged. The second charge storage area 502 is in a boundary between the channel area 105 and the second source / drain region 402 arranged. By tunneling hot electrons or holes into each of the charge storage areas 501 . 502 be introduced independently of each other electrical charge carriers. Since the value of a current flow between the source / drain regions of a respective memory cell depends on whether or not electrical charge carriers are introduced in the first charge storage layer and / or the second charge storage layer, two bits of information can be stored per memory cell.

In the following, reference is made to 6 a land field effect transistor memory cell arrangement 600 described according to a third embodiment of the invention.

The memory cell arrangement 600 is like the memory cell arrangement 500 implemented as a dual-bit memory cell array. In contrast to 5 is in the layout top view of 6 show how the bit lines for driving the source / drain regions of the ridge field effect transistor memory cells are arranged.

It should first be noted that in the memory cell arrangement according to the invention the direction of progression between word lines 109 and semiconductor lands or fins 403 orthogonal to each other. On the other hand, in order to drive a respective memory cell in dual bit mode, it is necessary that the source / drain regions of the memory cell can be driven by means of bit lines. Because there are crossing areas between the word lines 107 and the bitlines 601 respectively. 602 are required, according to the embodiment of 6 the bitlines 601 . 602 arranged obliquely to the word lines. This may differ (from the in 6 shown) can be realized in that the bit lines are formed in plan view, for example, at a 45 ° angle to the word lines. According to the in 6 the embodiment shown are the bit lines 601 . 602 however, formed in a sawtooth or zigzag shape, wherein in each crossing region of the bit lines 601 . 602 with a source / drain region 401 . 402 . 404 Vias from the bitlines 601 . 602 to the respective source / drain regions 404 perpendicular to the paper plane of 6 running down, whereby an electrical coupling is realized. The sawtooth-like structure of the bit lines has the advantage that all the sawtooth bit lines of a memory cell arrangement having a plurality of memory cells are of essentially the same length, so that the ohmic resistances of the bit lines 601 . 602 are approximately the same for all bit lines.

The bitlines 601 . 602 are formed in a single metal level (bit line level). The minimum structure width of the semiconductor memory depends on the extension of the bit lines. The dimension of a memory cell in accordance with 6 horizontal direction corresponds to 2F√ 2 , The bitlines 601 . 602 are at an angle of 45 ° to the word lines 107 educated. The width of the wordline 107 and the width of the semiconductor fins 311 . 312 is F√ 2 , Thus, the space requirement of a single memory cell according to the embodiment of 6 equal to 8F ² . The method for producing the in 6 shown memory cell array in "virtual ground array" architecture is not very expensive due to the only one required bit line level.

In the following, reference is made to 7 a land field effect transistor memory cell arrangement 700 described according to a fourth embodiment of the invention.

The land field effect transistor memory cell arrangement 700 is executed in dual-bit architecture.

In 8th is a layout plan view 800 the land field effect transistor memory cell arrangement 700 shown. In the 7 shown cross-sectional view is along the in 8th recorded line CC 'recorded.

The land field effect transistor memory cell arrangement 700 is different from the one in 5 shown land field effect transistor memory cell arrangement 500 essentially by the fact that the word lines 107 parallel to the Finns 105 running and that the bitlines 703 perpendicular to the fins 105 are formed running. The bitlines 703 , which in the cross-sectional view of 7 to be recognized are from 5 n wordlines 107 by means of a TEOS layer 701 ("Tetra-ethyl-ortho-silicate") electrically decoupled. Furthermore, between word lines 107 an insulation layer 702 educated. In 8th is also a spacer 801 shown.

• [1] Eitan, B, Pavan, P, Bloom, I, Aloni, E, Frommer, A, Finzi, D (2000) „NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" IEEE Electron Device Letters 21(11): 543–545

This document cites the following publication:

• [1] Eitan, B, Pavan, P, Bloom, I, Aloni, E, Frommer, A, Finzi, D (2000) "NROM: A Novel Localized Trapping, 2-bit Nonvolatile Memory Cell" IEEE Electron Device Letters 21 ( 11): 543-545

100

Fin field effect transistor memory cell arrangement

101

Silicon substrate

102

buried Silicon oxide layer

103

first Silicon-Bar

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second Silicon-Bar

105

Channel region

106

ONO charge storage layer sequence

107

Carbon word line

108

Silicon nitride capping layer

109

Word line extending direction

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first Fin field effect transistor memory cell

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second Fin field effect transistor memory cell

200

electrical charge carrier

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layer sequence

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Silicon layer

302

SOI substrate

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layer sequence

311

first Silicon fin

312

second Silicon fin

320

layer sequence

321

Carbon layer

330

layer sequence

400

Fin field effect transistor memory cell arrangement

401

first Source / drain region

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second Source / drain region

403

Web-running direction

404

n-doped areas

500

Fin field effect transistor memory cell arrangement

501

first Charge storage region

502

second Charge storage region

600

Fin field effect transistor memory cell arrangement

601

first Sawtooth bit line

602

second Sawtooth bit line

700

Fin field effect transistor memory cell arrangement

701

TEOS layer

702

insulation layer

703

bit

800

Layout plan view

801

spacer

Claims (28)

Fin field effect transistor memory cell • with a first and with a second source / drain region and with an interposed Channel area, which Source / drain and channel regions are formed in a semiconductor land; • with a Charge storage layer, at least partially on the semiconductor land is arranged; • With a carbon material having gate area on at least a part of the charge storage layer; • wherein the charge storage layer is set up so that by means of applying specifiable electrical Potentials to the ridge field effect transistor memory cell in the charge storage layer electrical charge carrier are selectively introduced or removable therefrom. Bridge field effect transistor memory cell according to claim 1, in which the charge storage layer A silicon oxide-silicon nitride-silicon oxide layer sequence; • alumina; Yttria; Lanthanum oxide; Hafnium oxide; • amorphous Silicon; Tantalum oxide; • titanium oxide; Zirconia; and or • one aluminate or consists of. Bridge field effect transistor memory cell according to claim 1 or 2, wherein the gate region of carbon material consists. Bridge field effect transistor memory cell after a the claims 1 to 3, in which the carbon material doping material for increasing the electrical conductivity of the gate area. Bridge field effect transistor memory cell according to claim 4, in which the doping material Boron; • aluminum; Indium; • phosphorus; and or • arsenic; having. Bridge field effect transistor memory cell after a the claims 1 to 5, in which the semiconductor bridge off A bulk silicon substrate or • one Silicon-on-insulator substrate is formed. Fin field effect transistor memory cell arrangement, with a plurality of ridge field effect transistor memory cells according to one of claims 1 to 6th Fin field effect transistor memory cell arrangement according to claim 7, wherein the ridge field effect transistor memory cells essentially matrix-shaped are arranged. Fin field effect transistor memory cell arrangement according to claim 7 or 8, wherein arranged along a first direction Fin field effect transistor memory cell common wordline areas coupled to the gate regions of the associated land field effect transistor memory cells are made of the same material as the gate regions. Fin field effect transistor memory cell arrangement according to one of the claims 7 to 9, arranged as a NAND memory cell arrangement. Fin field effect transistor memory cell arrangement according to one of the claims 7 to 10, which is set up in such a way that it can be predetermined by means of application electrical potentials to at least one gate region and to at least a part the source / drain regions charge carrier into the charge storage layer of at least one selected ridge field effect transistor memory cell by means of Fowler-Nordheim tunnels selectively recoverable or removable are. Fin field effect transistor memory cell arrangement according to one of the claims 7 to 9, the at least one first bit line area and at least a second bitline region, wherein the first source / drain region a respective ridge field effect transistor memory cell with an associated first bitline area and the second one Source / drain region a respective ridge field effect transistor memory cell having an associated one second bitline area is coupled. Fin field effect transistor memory cell arrangement according to claim 12, wherein the first and second bit line areas arranged substantially along a second direction, which second direction diagonally is arranged to the first direction. Fin field effect transistor memory cell arrangement according to claim 12 or 13, wherein the first and second bit line areas have a zigzag-like structure. Fin field effect transistor memory cell arrangement according to claim 9, wherein the semiconductor fins of the ridge field effect transistor memory cells and the Word line areas along a third direction running are arranged and along first and second bit line areas are arranged running a fourth direction, which third Direction is arranged perpendicular to the fourth direction. Fin field effect transistor memory cell arrangement according to one of the claims 12 to 15, which is set up so that by means of applying predetermined electrical potentials to at least one word line region and to at least a portion of the first and / or the second bitline regions charge carrier into the charge storage layer of at least one selected land field effect transistor memory cell by means of tunneling hotter charge carrier are selectively introduced or removable therefrom. Fin field effect transistor memory cell arrangement according to one of the claims 12 to 16 arranged to store two bits of information by inserting of carriers in the charge storage layer in a boundary region between the first Source / drain region and the channel region and into a boundary region between the second Source / drain region and the channel region of a respective ridge field effect transistor memory cell. Fin field effect transistor memory cell arrangement according to one of the claims 12 to 17, in which the first and second bit line areas as Virtual ground wiring is performed. Fin field effect transistor memory cell arrangement according to one of the claims 7 to 18, at the semiconductor lands of adjacent land field effect transistor memory cells are arranged at a distance of 10nm to 100nm from each other. Fin field effect transistor memory cell arrangement according to one of the claims 9-19, with at least a portion of the wordline areas covering electrically insulating cover layer. Fin field effect transistor memory cell arrangement according to claim 20, wherein the cover layer is in cavities between extends with the word line area covered semiconductor ridges. A method of fabricating a ridge field effect transistor memory cell the • one first and second source / drain regions and one in between arranged channel region are formed in a semiconductor land; • a charge storage layer is formed at least partially on the semiconductor land; • a carbon material having gate region on at least a portion of the charge storage layer is formed; • the Charge storage layer is set up such that by means of applying specifiable electrical potentials to the ridge field effect transistor memory cell in the charge storage layer selectively introduces electrical charge carriers or removable from it. The method of claim 22, wherein the carbon material of the gate region using a chemical vapor deposition method is formed. A method according to claim 22 or 23, wherein the Forming the carbon material • methane; Acetylene; and or • ethene used becomes. Method according to one of claims 22 to 24, wherein during the Forming the carbon material containing a dopant Supplied substance is, which doping material is set up so that it electric conductivity of the gate area increases. A method according to any one of claims 22 to 25, wherein forming the carbon material of this annealing process step is subjected. Method according to one of claims 22 to 26, wherein during the Forming the ridge field effect transistor memory cell energy by means of an electromagnetic Radiation source is supplied. A method according to any one of claims 22 to 27, wherein the Carbon material first and then using a plasma etching process is structured to form the gate region.