DE10355575B4 - A method of making sidewall spacers for a circuit element by increasing etch selectivity - Google Patents

Abstract

Method for producing a semiconductor device with:
Providing a semiconductor substrate;
Forming a line structure element on the semiconductor substrate;
Performing a first dopant implantation using the lead device as part of an implantation mask;
Depositing a silicon dioxide layer over the substrate and the line structure element;
Heat treating the substrate to activate the first dopant implant at a first temperature and for a first time period;
Continuing the heat treatment at a second temperature for a second period of time to complete densification of the silicon dioxide layer;
Forming a spacer layer over the densified silicon dioxide layer; and
Etching the spacer layer, wherein the densified silicon dioxide layer is used as an etch stop layer to form sidewall spacers on the line structure element.

Description

FIELD OF THE PRESENT INVENTION

in the In general, the present invention relates to the manufacture of integrated Circuits and relates to the production of sidewall spacers, for example for the lateral structuring of a doping profile can be used, the adjacent to a circuit element, the sidewall spacers formed thereon is implanted.

DESCRIPTION OF THE STATE OF THE TECHNOLOGY

The Manufacturing integrated circuits requires a large number of process steps with, for example, photolithography, etching techniques, Implantation sequences, heating processes and the like. In the MOS technology is an important step in producing a Gate electrode of a field effect transistor, wherein the size of the gate electrode significantly affects the overall behavior of the MOS transistor element. The Gate electrode is a line-like Circuit element over a crystalline semiconductor region, typically a silicon region, is formed, with a thin Gate insulating layer between the semiconductor region and the gate electrode is arranged to provide a dielectric barrier and a capacitive coupling to the underlying semiconductor region to generate a conductive channel when creating a suitable Control voltage to the gate electrode is formed. The channel forms in the semiconductor region in the vicinity of the gate insulating layer and creates an electrical connection between the heavily doped Source and drainage area. The distance between the drain and the Source area, d. H. the lateral extent of the canal, with the lateral extent of the gate electrode is correlated and also as channel length is an important design parameter and now has 0.1 μm and achieved less in sophisticated integrated circuits.

In The standard MOS technology is the gate electrode formed before the drain and source regions are made by ion implantation become. While In the ion implantation process, the gate electrode serves as one Implantation mask, whereby a correct adjustment of the drain and source region with respect to the gate electrode. Because a variety of high temperature treatments after production the gate electrode executed be prepared before the structuring of the gate electrode Gate insulating layer, preferably based on silicon dioxide or silicon nitride is formed, and the gate electrode is made of polysilicon formed to thereby obtain a gate electrode structure, the has a high thermal stability. After patterning the gate electrode, the drain and source regions become manufactured by ion implantation, wherein the gate electrode as a Implantation mask is used. However, it turns out that transistor elements sophisticated with reduced component sizes Doping profiles in the lateral direction and also in the vertical Require direction, where the term "vertical" is the direction perpendicular to surface of the substrate while the term "lateral" roughly the flow direction of carriers in the channel corresponds. While the vertical Dotierstoffprofilierung by appropriate adjustment the implantation parameters, such as dose and energy for a given Ion species, achievable requires the lateral dopant profile an improved masking technique, typically by the Production of one or more sidewall spacers achieved becomes.

Related to the 1a to 1c Now, a typical conventional process flow for manufacturing sidewall spacers will be described in more detail to explain certain disadvantages of the conventional technology as feature sizes of circuit elements are further reduced in size.

1a is a schematic cross-sectional view of a transistor element 100 during an early manufacturing stage. The transistor element 100 includes a substrate 101 which may be a silicon substrate or an SOI (silicon on insulator) substrate in sophisticated devices. Regardless of the type of substrate used, the substrate 101 a substantially crystalline semiconductor region 103 on, that of an isolation structure 102 enclosed, which is typically provided in modern integrated circuits in the form of a trench isolation. The transistor element 100 further includes a gate electrode 105 made of polysilicon and over the silicon area 103 and through a gate insulating layer 104 is disconnected. In principle, the reduction of the gate length, ie in 1a the horizontal extension of the gate electrode 105 , a corresponding reduction in the thickness of the gate insulating layer 104 to ensure proper capacitive coupling for proper control of a channel located below the gate insulating layer 104 when creating a suitable control voltage is formed. For a gate length of about 100 nm, the thickness of the gate insulating layer is 104 if it has silicon dioxide in the range of about 2 to 4 nm. In view of correct channel controllability and the integrity of the gate insulating layer 104 To preserve, sophisticated implantation profiles are adjacent to the gate electrode 105 required. This is a sidewall spacer 106 which is often referred to as Offset or Off Set spacer is called, on the side walls of the gate electrode 105 formed in combination with the gate electrode 105 as an implantation mask during a first implantation, referred to as 108 is designated to serve. The corresponding dopant profile, with 107 is also referred to as extension area.

A typical process for manufacturing the transistor element 100 as it is in 1a may include the following processes. First, the trench isolations 102 in the substrate 101 formed by state-of-the-art photolithography, anisotropic etch and deposition techniques well established in the art. Thereafter, multiple implantation cycles are performed so as to provide a required vertical doping profile (not shown) in the semiconductor region 103 to create. Subsequently, a material layer for the gate insulating layer 104 on the substrate 101 formed for example by the most modern oxidation and / or deposition techniques. Next, a layer of polysilicon of a required thickness is deposited by, for example, low pressure chemical vapor deposition (LPCVD), based on process parameters well established in the art. Subsequently, the polysilicon layer and the material layer for the gate insulating layer 104 by sophisticated photolithography and anisotropic etching techniques, typically first forming a resist pattern element and shrinking it to specified dimensions, then serving as an etch mask during the subsequent anisotropic etch process, in which the gate electrode 105 is formed from the polysilicon layer while the material layer for the gate insulating layer 104 serves as an etch stop layer. Thereafter, the remnants of the material layer, which may be the gate insulating layer 104 forms, be removed, and the substrate 101 may be oxidized (not shown) to form a thin layer of silicon dioxide on exposed surfaces of the silicon region 103 and the gate electrode 105 to build. Then, a silicon dioxide layer is conformally deposited and then anisotropically selectively etched to the silicon around the offset spacers 106 to build.

Here is the width of the offset spacers 106 and thus determines the lateral blocking effect through the thickness of the deposited silicon dioxide layer. Finally, taking advantage of the gate electrode 105 and the offset spacers 106 implantation as implantation mask 108 carried out to the extension areas 107 to define their doping profile in the vertical direction by the type of dopants used and the corresponding implantation energy and in the lateral direction by the offset spacers 106 is determined.

1b schematically shows the transistor element 100 in an advanced manufacturing stage. A spacer layer 110 silicon nitride, for example, is conformal over the substrate 101 and the gate electrode 105 formed with a thickness which is responsible for the further profiling of the lateral dopant concentration in the semiconductor region 103 is required. Further, a thin etch stop layer 109 having silica, between the spacer layer 110 and the substrate 101 arranged. A typical process involves the deposition of the etch stop layer 109 by plasma enhanced chemical vapor deposition followed by plasma enhanced chemical vapor deposition of the spacer layer 110 followed. Since the lateral doping profiling on the accuracy of the deposition of the spacer layer 110 Silicon nitride is a preferred candidate since this material can be deposited more precisely by well established CVD techniques compared to, for example, silicon dioxide. After depositing the layers 109 and 110 is an anisotropic etch process with a suitably selected etch chemistry that provides a moderately high etch selectivity between the etch stop layer 109 and the spacer layer 110 has performed. Due to the ever decreasing structure sizes, the thickness of the spacer layer must 110 and also the etch stop layer 109 be adapted according to the reduced feature sizes, so that a thickness of the etch stop layer 109 typically in the range of 1 to 5 nm.

1c schematically shows the transistor element 100 after the anisotropic etching process, wherein the spacer layer 110 except at the areas on the side wall of the gate electrode 105 , now called sidewall spacers 110a are substantially removed. While for larger structure sizes and thus greater thicknesses of layers 109 and 110 typically the thickness of the thin etch stop layer 109 is sufficient to reliably stop the etching front when the excess material of the spacer layer 110 is substantially completely removed from horizontal surface areas since the etch stop layer 109 only the etching process at the exposed areas must slow down until the entire material of the spacer layer 110 over the entire substrate 101 away, the situation is very different for extremely small size components. In this case, the deposited etch stop layer 109 ; For example, in the form of silicon dioxide, due to the reduced thickness, provide local "channels" through which the etch chemistry covers the surface area of the area 103 and the gate electrode 105 can attack, creating a "pitting" effect.

As previously explained, the gate electrode 105 although this is heavily doped, a relatively ge In contrast to, for example, metals, such as aluminum, tungsten, and the like, they have conductivity as typically used in semiconductor manufacturing. Therefore, in a typical MOS technology, the conductivity of the gate electrode becomes 105 by forming a metal silicide region on the gate electrode 105 increased so as to reduce their resistance. During the silicidation process, the sidewall spacer serves 110a in addition, self-aligning production of a metal silicide in the drain and source regions to be formed as well as in the gate electrode 105 to allow silicidation on the sidewall spacer 110a essentially does not take place. Because the amount of metal silicide that is in the gate electrode 105 in the subsequent process, depending on the process conditions based on the size of the exposed silicon region of the gate electrode 105 can be determined, in some processes, the anisotropic etching process is continued to the vertical extent of the spacer element 110a while further reducing its lateral width substantially. Due to the continuation of the anisotropic etching process, exposed portions of the etching stopper layer become 109 is increasingly consumed due to the limited etch selectivity, thereby further increasing the pitting effect and seriously compromising the integrity of the underlying material surfaces.

1d schematically shows the transistor element 100 upon completion of the anisotropic etch process described above. The sidewall spacers 110a show a significantly reduced vertical extent, so that upper side wall portions of the gate electrode 105 are exposed, but still from residues of Ätzstoppschicht 109 and the offset spacers 106 covered in a subsequent isotropic wet-chemical etching process based on, for example, hydrogen fluoride. Further, exposed portions of the etch stop layer 109 , as 109a are markedly reduced in thickness and may cause pitting than 111 is referred to lead in the underlying material. The locally inhomogeneous damage, ie the pitting 111 , is disadvantageous for the further processing of the transistor element 100 because z. B. the mechanical and electrical properties of the affected surface areas are significantly impaired. Also, in extremely size-reduced transistor elements, the available surface area for forming contacts is also greatly reduced, and excessive degradation of transistor performance caused by surface areas caused by pitting can be observed 111 during the etch sequence for the spacers were damaged. The problem is even more acute, as in advanced transistor elements more than two spacers, such as the offset spacer element 106 and the spacer 110a , must be formed to the required lateral profiling in the semiconductor region 103 to ensure. Thus, in a subsequent patterning process for further sidewall spacers, which may also be anisotropically etched, upper side wall regions of the gate electrode may be found 105 are exposed, a further impairment of exposed surface areas by, for example, pitting instead. Reducing the effect of pitting during anisotropic etching by, for example, increasing the thickness of the etch stop layer 109 is less desirable because of the subsequent isotropic removal of remnants of the layer 109 and the offset spacers 106 then to an intolerable undercutting of the sidewall spacer 110a would lead. Further, increasing the thickness of the layer 109 at the expense of reducing the thickness of the spacer layer 110 lead to a reduced controllability of the lateral dopant profile.

in view of The problems identified above therefore have a need for an improved one Technique for the production of sidewall spacers, whereby the damages be reduced in exposed surface areas during the anisotropic patterning of a spacer layer.

Further prior art is known from US 5,013,675 which discloses a method of making and removing lightly doped drain spacers made of polysilicon. A biphasic heat process for activating the dopants of the LDD, as well as densifying a silicon dioxide layer used as an etch stop layer, is not shown in this document.

The US Pat. No. 6,448,167 B1 relates to a method for reducing the undercut phenomenon in the production of sidewall spacers. For densifying the silicon dioxide serving as the etching stop layer over the gate structure, the heat treatment provided for the activation of the dopants is used.

OVERVIEW OF THE INVENTION

The The present invention provides a method having the features of claim 1.

In general, the present invention is directed to a technique that provides increased etch selectivity of a silicon dioxide coating relative to a spacer layer, typically comprising silicon nitride, to reduce the likelihood of pitting through the silicon dioxide coating during a subsequent anisotropic etch process to pattern the spacer layer. The durability of the silicon dioxide coating with respect to the etch chemistry used to pattern the sidewall spacers can be increased by compacting the structure of the silicon dioxide coating typically deposited by plasma assisted chemical vapor deposition.

consequently comprises according to a illustrative embodiment the present invention in principle a method of deposition a silicon dioxide layer over a substrate having a line structure element, and the Heat treating the Substrate to densify the silicon dioxide layer. After that will a spacer layer over the silicon dioxide layer is formed and the spacer layer becomes etched while the densified silicon dioxide layer is used as an etch stop layer, around sidewall spacers adjacent to the line structure element to build.

BRIEF DESCRIPTION OF THE DRAWINGS

Further Advantages, tasks and embodiments The present invention is defined in the appended claims and go more clearly from the following detailed description when studying with reference to the accompanying drawings becomes; show it:

1a to 1d schematically a transistor element during various stages of production according to a typical conventional process flow; and

2a to 2d schematically cross-sectional views of a line structure element, such as a gate electrode, during different manufacturing steps in the formation of sidewall spacers using a compacted silicon dioxide layer.

DETAILED DESCRIPTION

Even though the present invention is described with reference to the embodiments, as in the following detailed description as well as in the following Drawings are shown, it should be self-evident that the present detailed description as well as the drawings not intended to limit the present invention to the specific ones illustratively disclosed embodiments restrict but merely the illustrative embodiments described exemplify the various aspects of the present invention, the scope of which is defined by the appended claims is.

The The present invention is generally based on the concept of the inventors, that the structure of a deposited by CVD (Chemical Vapor Deposition) Silicon dioxide compacted by a heat treatment can be. It is well known that deposited silicon dioxide typically deformed bonds and a reduced density in comparison to an oxide obtained by oxidation there is a reduced resistance to the diffusion of atoms and molecules, about of water molecules and in particular the components of an etching chemistry used for structuring a sidewall spacer is used results. by virtue of The reduced density can therefore be the interaction of an etch chemistry with the silicon dioxide layer, except for a material removal of silicon dioxide, to a local limited attack on the underlying material by the diffusion of etching components to lead, what a pitting of the underlying material layer results. By heat treatment of the deposited silicon dioxide can compact its structure which reduces resistance to the diffusion of etching components elevated becomes.

Related to the 2a to 2c Now, further illustrative embodiments of the present invention will be described in more detail.

In 2a includes a semiconductor device 200 a substrate 201 which may represent a suitable substrate suitable for manufacturing integrated circuits therein and thereon. In particular, the substrate 201 may represent a silicon substrate or an SOI (silicon on insulator) substrate having a substantially crystalline silicon region formed thereon. In other cases, the substrate may be 201 have any other suitable semiconductor layer formed thereon, such as a germanium-containing semiconductor layer or other II / VI or III / V semiconductor compounds. Also, since silica is also advantageously useful in the fabrication of semiconductor devices having crystalline regions other than silicon regions, the present invention should not be considered as limited to silicon devices unless such specifications are explicitly set forth in the appended claims.

The substrate 201 includes an isolation structure 202 which is a crystalline area 203 encloses a suitable type, over which a line structure element 205 is formed, which may represent a gate electrode of a field effect transistor in the present example. It should be noted, however, that the line structure element 205 may represent any other circuit element, such as polysilicon lines used to connect individual circuit elements or different chip areas of an integrated circuit can be used. When the line structure element 205 may represent a gate electrode, the line structure element 205 from the crystalline area 203 through a gate insulating layer 204 be separated. The gate insulating layer 204 may be constructed of silicon dioxide, silicon oxynitride, silicon nitride, or a high-k dielectric material or a combination of the foregoing materials, depending on the design requirements. The present invention is particularly advantageous in connection with highly sophisticated transistor elements of critical dimensions - that is, in the device 200 as it is in 2a is shown, the horizontal dimension of the line structure element 205 - in the order of 100 nm and much less. As before with reference to the 1a to 1d sidewall spacers may be used in such devices to provide accurate lateral dopant profiles, wherein the spacers and associated etch stop layers must be reduced in thickness. It should be noted, however, that the present invention also applies to the device 200 with a critical dimension larger as specified above, allowing for increased production yield. An offset spacer 206 is on the sidewalls of the line structure element 205 formed, wherein a width of the offset spacer 206 is set in accordance with process requirements so as to provide the required lateral dopant profile of extension regions 207 that are in the crystalline area 203 are formed to ensure. A silicon dioxide layer 209 is compliant on the substrate 201 and the line structure element 205 including the offset spacers 206 educated. In demanding applications, a thickness of the silicon dioxide layer can 209 in the range of 1 to 10 nm. In other embodiments, a larger thickness may be suitable.

A typical process for manufacturing the semiconductor device 200 as it is in 2a may include the following processes. The isolation structure 202 , the line structure element 205 , the gate insulating layer 204 and the offset spacers 206 can be made with substantially the same process steps as previously referred to 1a are described. It will be readily appreciated that various modifications to the individual process steps and materials may be made depending on design and process requirements for a specified product. For example, the isolation structures 202 in the form of locally oxidized areas or in any other suitable form. Furthermore, the process flow and the process recipes for producing the insulation structure 202 in the form of trench isolation in front of the type of material that is in the crystalline area 203 used, depend. Next is the silicon dioxide layer 20 typically deposited by plasma assisted chemical vapor deposition from TEOS (tetraethyloxysilicate) or silane, with usually deposition based on TEOS and ozone being preferred in view of the conformity of the resulting layer. As previously discussed, a deposited silicon dioxide layer has a lower density compared to a silicon dioxide layer formed by oxidation, and therefore offers less resistance to the diffusion of etch components, resulting in reduced etch selectivity with respect to a specified etch chemistry found in FIG a subsequent patterning process for a spacer layer is applied. Therefore, according to the present invention, the substrate 201 after depositing the silicon dioxide layer 209 heat treated at temperatures in the range of about 700 ° C and more to reconfigure the near order of the structural composition of the silica. In one embodiment, the substrate becomes 201 heat treated at a temperature of about 730 ° C and more for a period of about 60 to 200 seconds.

In a further embodiment, the dopants that are the extension regions 207 after deposition of the silicon dioxide layer 209 activated at a temperature of about 800 to 1000 ° C for about 5 to 50 seconds. While activating the dopants in the extension regions 207 also becomes the silicon dioxide layer 209 which achieves the requisite structural reconfiguration for the subsequent etching process. In other embodiments, the anneal process may be to activate the dopants of the extension regions 207 be controlled to a required degree of densification of the silicon dioxide layer 209 when the time to activate the dopants at the above-specified elevated temperature is considered insufficient for the required densification. For this, the bake temperature may be lowered to about 700 ° C after activation of the dopants, and may be maintained until a required degree of compaction is achieved. As at least one further implantation step and a corresponding annealing cycle is required when the device 200 To represent a field effect transistor, the additional diffusion of the dopants of the extension regions 207 by, for example, suitably the width of the offset spacer 206 is determined. That is, unlike a single anneal process for activating the dopants in the extension regions 207 and from still in the crystalline areas 203 to be implanted doping In a subsequent bake cycle, an additional bake cycle may increase the diffusion activity of the dopants in the extension regions 207 lead, since this further diffusion may result in a smaller channel length due to the additional lateral movement of the dopants. This reduction of the channel length can be achieved by increasing the width of the offset spacers accordingly 206 and also compensated for by increasing the dose of implantation so as to have substantially the same dopant concentration at the PN junction, ie at the interface between the regions 203 and 207 compared to a smaller offset spacer width and a single bake cycle. After the heat treatment of the substrate 201 ie after densification of the silicon dioxide layer 209 , becomes a spacer layer 210 compliant on the silicon dioxide layer 209 deposited.

2 B schematically shows the semiconductor device 200 after the preparation of the spacer layer 210 , In a specific embodiment, the spacer layer 210 Silicon nitride on. The spacer layer 210 can be applied by well established plasma enhanced chemical vapor deposition for which well established process recipes are known in the art.

In another illustrative embodiment, starting from the component 200 as it is in 2a the silicon dioxide layer is shown 209 deposited, followed by the application of the spacer layer 210 followed, as is the case in the conventional procedure. However, unlike the conventional technique, the heat treatment is then performed to the silicon dioxide layer 209 to condense. In one embodiment, densifying the layer 209 immediately before or during the deposition of the spacer layer 210 be executed. For example, the spacer layer 210 are deposited by thermal CVD, wherein elevated temperatures compared to the plasma assisted deposition of the spacer layer 210 required are. Heating the substrate 201 to the required temperature can then be advantageously used to achieve a desired densification of the silicon dioxide layer 209 to reach.

In a further embodiment, the silicon dioxide layer 209 deposited and compacted by means of a corresponding heat treatment. Thereafter, when the heat treatment to densify the layer 209 in view of a thermal budget for the production of the semiconductor device 200 is considered inappropriate, the extension areas 207 formed by a specified dopant species through the compacted silicon dioxide layer 109 is implanted, the effect of the heat treatment to densify the layer 109 on the dopants in the area 207 is avoided.

It is now up again 2 B referenced; the spacer layer 210 is then anisotropically patterned with an etch chemistry that is selective with respect to the densified silicon dioxide layer 209 , wherein the selectivity is clearly due to the heat treatment of the compacted layer 209 is increased. Thus, during the action of the etch chemistry on the silicon dioxide layer 209 the probability of pitting through the compacted layer 209 significantly reduced, whereby the manufacturability and the production yield are improved.

2c schematically shows the semiconductor device 200 after completion of the anisotropic etching process to pattern the spacer layer 210 , whereby a sidewall spacer element 210a is formed. In the in 2c The embodiment shown is the vertical size of the spacers 210a reduced so as to upper side wall portions of the line structure element 205 expose, these areas still from the offset spacer 206 and the silicon dioxide layer 209 are covered. Due to the increased selectivity of the densified silicon dioxide layer 209 in relation to those for the production of the spacer elements 210a The etch chemistry used is the probability of pitting through the layer 209 is reduced even if the anisotropic etching process is continued until a reduced height of the spacers is achieved. In other embodiments, the spacers become 210 not reduced in height, with the increased etch selectivity of the densified silicon dioxide layer 209 Improved the production yield compared to the conventional process. Further, source and drain regions are in the crystalline region 203 formed, wherein in the corresponding implantation process, the spacer elements 210a serve as an implantation mask.

The process steps used to manufacture the semiconductor device 200 as it is in 2c can be applied substantially include the same processes as previously described with reference to the 1c and 1d are described. Further, after implantation to form the source and drain regions 217 a corresponding annealing process may be performed to activate the dopants and to at least to a certain extent heal lattice damage caused during implantation. The exposed areas of the densified silicon dioxide layer 209 and the offset spacers 206 can be used before or after implantation to create the drain and source regions 217 be removed.

As previously discussed, the lateral dopant profile may be in the crystalline region 203 require the formation of three or more sidewall spacers. For this purpose, a further silicon dioxide layer can be deposited and the sequence previously described with reference to the 2a and 2 B can be repeated to provide another sidewall spacer, wherein the increased selectivity of the corresponding densified silicon dioxide layer also ensures a significantly reduced likelihood of pitting through the layer during the patterning process.

After the finally desired dopant profile in the crystalline area 203 can be generated metal silicide areas in the extension areas 207 and the line structure element 205 are formed, wherein the enlarged exposed surface area of the line structure element 205 results in a greater amount of metal silicide formed therein.

2d schematically shows the semiconductor device 200 after completion of the sequence described above with another spacer element 220a resting on a densified silicon dioxide layer 219 is formed. metal silicide 218 are in the line structure element 205 and the drain and source regions 217 including the extension areas 207 educated. Thus, the semiconductor device represents 200 a field effect transistor having an improved lateral dopant profile, wherein the densified silicon dioxide layer 209 and the layer 219 if provided, significantly reduces pitting which, in the conventional art, can lead to low production yields and / or even prevent the use of thin silicon dioxide layers during the production of spacers. Thus, the present invention provides a technique that enables the formation of sidewall spacers, including, for example, silicon nitride, more reliably compared to the conventional process flow, by heat treating a silicon dioxide layer that serves as an etch stop layer to increase its density , The increased density results in less likelihood of pitting or even complete pitting leakage through the silicon dioxide layer during the anisotropic etch process. Thus, a more efficient manufacturing process and production yield are achieved even when considering extremely reduced size semiconductor device elements that require a very thin silicon dioxide layer as the etch stop layer during anisotropic patterning of the spacers.

Claims (9)

Method for producing a semiconductor device With: Providing a semiconductor substrate; Forming a Line structure element on the semiconductor substrate; Perform a first dopant implantation using the lead structure element as part of an implantation mask; Depositing a silicon dioxide layer over the substrate and the line structure element; Heat treating the substrate, to activate the first dopant implant at a first temperature and for a first period of time; Continue the heat treatment at a second temperature for a second period of time to densify the silicon dioxide layer complete; Forming a spacer layer over the densified silicon dioxide layer; and Etching the spacer layer, wherein the densified silicon dioxide layer is used as the etch stop layer Sidewall spacers to form the line structure element. The method of claim 1, wherein the spacer layer Has silicon nitride. The method of claim 1, wherein the second temperature a temperature of about 700 ° C and higher. The method of claim 1, further comprising: Depositing a second silicon dioxide layer over the substrate, heat treating of the substrate to densify the second silicon dioxide layer, Depositing a second spacer layer over the second silicon dioxide layer and forming a second sidewall spacer adjacent to the sidewall spacer by etching the second spacer layer. The method of claim 1, further comprising implanting a second dopant in the substrate, wherein the sidewall spacer element is used as an implantation mask. The method of claim 4, further comprising implanting a third dopant in the substrate, wherein the sidewall spacer and the second sidewall spacer as an implantation mask be used. The method of claim 1, wherein a thickness of the Silicon dioxide layer is in the range of about 1 to 10 nm. The method of claim 1, wherein the spacer layer is anisotropically etched about an upper sidewall portion of the line structure element expose. The method of claim 4, wherein the second spacer layer anisotropically etched like this is to an upper side wall portion of the line structure element expose.