DE10259783A1 - Method for improving process step sequence in forming semiconductor memories with charge trapping memory cells, used same masks as used for forming doped troughs outside memory cell field for removing HV gate dielectric - Google Patents

Abstract

In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.

Description

In the manufacture of semiconductor memories in a semiconductor body by introducing dopant for n-line and for p-line doped wells designed for the manufacture of memory transistors and the CMOS transistors or the like components of a drive circuit (Periphery) are provided. For the memory transistors can also suffice if the semiconductor body is included a sufficiently high basic funding. For low-voltage transistors and for high-voltage transistors the control circuit will have wells with different doping levels intended. Moreover are the gate dielectrics of these transistors in thickness from each other different.

First, those for the high-voltage transistors provided troughs and on their tops the high-voltage gate dielectric required for the high-voltage transistors manufactured. Then the for the troughs provided on the low-voltage transistors and on their tops that for the low-voltage transistors required low-voltage gate dielectric manufactured. In the for The area provided by the low-voltage transistors must first have the high-voltage gate dielectric be removed. For that is So far, a separate mask was provided. Also a separate one Mask is intended to be one for Charge trapping memory cells, in particular NROM memory cells, are provided Storage layer sequence, which is usually is an oxide-nitride-oxide storage layer sequence in the area of the drive periphery to remove. The storage layer sequence is also buried above Bit lines formed within the memory cell array are removed in certain areas.

Object of the present invention is a process to improve the process sequence to specify the manufacture of semiconductor memories, in particular charge-trapping memory cells, with which masks can be saved.

This task is done with the procedure with the features of claims 1 and 8 solved. Refinements result themselves from the dependent Claims.

In this process, the same masks those for the production of the doped wells outside the memory cell array used, used in the areas concerned High-voltage gate dielectric and / or one for charge-trapping memory cells to remove the intended storage layer sequence.

The attached figure shows for further explanation a semiconductor memory chip in cross section.

In the figure is a semiconductor body 1 or substrate with a storage layer sequence applied to the entire surface on top to form charge-trapping memory cells known per se, such as SONOS memory cells or NROM memory cells. The memory layer sequence comprises a first boundary layer 2 , a storage layer 3 and a second confinement layer 4 and can in particular be an oxide-nitride-oxide layer sequence. Before applying this storage layer sequence, STI isolations are made 5 manufactured with which the memory cell array is electrically isolated all around.

Troughs are shown as examples in the figure 6 of a first conductivity type and tubs 7 of a second conductivity type. The conductivity types are n-line and p-line, although it is fundamentally not essential whether the n-type wells or the p-type wells are manufactured first. The sizes and the arrangement of the tubs can be selected according to the respective requirements. Also in the area of the memory cell array 9 dopant is introduced to form a trough, which is not shown separately. Instead, the semiconductor body 1 or the substrate has already been provided with a sufficiently high basic doping.

The in the memory cell array 9 manufactured buried bit lines 8th are indicated by the contours drawn in dashed lines. These buried bit lines are produced by introducing dopant. They connect the cell transistors in columns. The one from the tubs 6 areas occupied by the first conductivity type 10 the areas occupied by the tubs of the second conductivity type 11 and other areas 12 above the buried bit lines 8th are indicated with the braces.

A first exemplary embodiment of a process sequence provides that in a first step the semiconductor body 1 or a substrate with STI insulation 5 is provided. On the top is the storage layer sequence 2 . 3 . 4 applied. A sequence of process steps can then be inserted with which the buried bit lines are produced. Instead, it is also possible to produce the bit lines only after the troughs provided for the high-voltage transistors have been produced.

Using a suitable photolithography, the wells doped for the first conductivity type 6 manufactured. The mask that is used for this process step is also used to sequence the storage layer in the areas left free by the mask 10 to remove. After the mask has been removed, a further mask is produced which corresponds to the regions of the troughs to be produced which are doped for the second conductivity type 7 leaves free. This mask is also used in the area in question 11 to remove the memory layer sequence. The further mask is then removed so that the high-voltage gate dielectric can be produced for the high-voltage transistors.

An alternative exemplary embodiment of this process sequence provides that after the troughs doped for the first conductivity type have been produced 6 using the mask used, initially only the material of the second boundary layer 4 (especially top oxides) is removed. The troughs doped for the second conductivity type are then produced 7 ; the mask used for this is also used to mark the material of the second boundary layer in the relevant areas 4 to remove. This is followed by the production of the buried bit lines 8th by introducing dopant.

In the memory cell array 9 the storage layer sequence is initially still completely present. As part of the further processing will be in the areas 12 above the buried bit lines 8th the layers of the memory layer sequence are removed. Masks are used again. After the second boundary layer 4 becomes the storage layer 3 , especially a nitride. This also happens in the control periphery, at least in those areas in which the second boundary layer 4 has already been removed. Using a block array lithography provided for covering a memory cell array, the first boundary layer in the areas in question is then also removed. The high-voltage gate dielectric provided for the high-voltage transistors is then produced.

A corresponding procedure can be applied to that after manufacturing the for the high voltage transistors provided high-voltage gate dielectric applied in the area of the wells to remove the low-voltage tubs to be manufactured.

For this, first of all the for the high-voltage transistors before seen tubs made in the manner described. After that the high-voltage gate dielectric is applied. Another Mask technology will then be used for the first conductivity type endowed tubs for the low-voltage transistors are provided, produced by introducing dopant. The The mask used is also used to connect the high-voltage gate dielectric in the areas left blank by this mask. The mask is removed to make another mask for the second conductivity type endowed tubs for the low-voltage transistors are intended to manufacture. This Masks are also used in the ones left free Areas to remove the high-voltage gate dielectric. After this The low-voltage gate dielectric can also remove this mask for the Low-voltage transistors are applied.

The process sequence described last can with the previously illustrated embodiments be combined. After making the high voltage gate dielectric in the manufacture of a semiconductor memory with charge trapping memory cells this further process step sequence is used in order for the low-voltage transistors Areas to remove the high voltage gate dielectric before there that for the low-voltage transistors provided low-voltage gate dielectric is applied.

1

Semiconductor body

2

first boundary layer

3

storage layer

4

second boundary layer

5

STI isolation

6

tub of a first conductivity type

7

tub of a second conductivity type

8th

buried bit

9

Memory cell array

10

of the troughs of the first conductivity type

areas

11

of the tubs of the second conductivity type eingenom

mene areas

12

Further Areas above the buried bit lines

Claims (10)

Method for improving a process step sequence in the production of semiconductor memories with charge-trapping memory cells, in which in a first step a semiconductor body ( 1 ) or substrate with STI insulation ( 5 ) and a storage layer sequence consisting of a first boundary layer ( 2 ), a storage layer ( 3 ) and a second boundary layer ( 4 ) is applied in a second step using mask technology for a first conductivity type doped wells ( 6 ) by introducing dopant into the semiconductor body ( 1 ) or substrate are produced, in a third step using mask technology for an opposite second conductivity type doped wells ( 7 ) by introducing dopant into the semiconductor body ( 1 ) or substrate are produced and a) in an area provided for the memory cells ( 9 ) buried bit lines ( 8th ) by introducing dopant into the semiconductor body ( 1 ) or substrate are produced, and b) in an area provided for components of a control circuit ( 10 . 11 ) the storage layer sequence ( 2 . 3 . 4 ) is removed, characterized in that in the second step using the same mask at least the second boundary layer ( 4 ) the storage layer sequence in the area ( 10 ) of the wells doped for the first conductivity type ( 6 ) away and in the third step using the same mask at least the second boundary layer ( 4 ) the storage layer sequence in the area ( 11 ) of the wells doped for the second conductivity type ( 7 ) Will get removed. Method according to Claim 1, in which between the first step and the second step the buried bit lines ( 8th ) and other areas ( 12 ) the storage layer sequence are removed. Method according to Claim 1, in which, after the third step, the buried bit lines ( 8th ) and other areas ( 12 ) the storage layer sequence are removed. Method according to one of Claims 1 to 3, in which, in the second and third steps, the storage layer ( 3 ) and the first boundary layer ( 2 ) are removed in the relevant areas. A method according to claim 3, wherein in the second and third steps the second confinement layer ( 4 ) is removed in the relevant areas and after the production of the buried bit lines ( 8th ) the storage layer ( 3 ) and the first boundary layer ( 2 ) in the areas of the tubs produced in the second step and the third step ( 6 . 7 ) can be removed. The method of claim 5, wherein the first confinement layer ( 2 ) is removed using a block array lithography provided for covering the memory cell array. Method according to one of claims 1 to 6, in which in the second and third step tubs ( 6 . 7 ) which are intended for high-voltage transistors and after the production of the buried bit lines ( 8th ) and the area-by-area removal of the storage layer sequence ( 2 . 3 . 4 ) a high-voltage gate dielectric is produced for the high-voltage transistors. Method for improving a process step sequence in the production of semiconductor memories, in which in a semiconductor body ( 1 ) or substrate using mask technology for a first conductivity type doped wells ( 6 ) and wells doped for an opposite second conductivity type ( 7 ), which are intended for high-voltage transistors, are produced by introducing dopant, a high-voltage gate dielectric for the high-voltage transistors on a relevant upper side of the semiconductor body ( 1 ) or substrate is applied and after the application of the high-voltage gate dielectric by means of a further mask technique for the first conductivity type further wells doped and for the second conductivity type further wells which are intended for low-voltage transistors are produced by introducing dopant, characterized in that, using the same masks that are used for the production of the further troughs, the high-voltage gate dielectric is removed in the regions left free by the masks. The method of claim 8, wherein a semiconductor memory is produced with charge trapping memory cells and the process steps according to one of the claims 1 to 7 executed become. The method of claim 8 or 9, wherein according to the Production of the further tubs a low-voltage gate dielectric for the low-voltage transistors will be produced.