DE10221033C1 - Method and device for temporarily storing data of a pixel-oriented, photosensitive component - Google Patents

Abstract

The arrangement has a memory element with data input alternately connected to output channels. Lower and higher address data are successively read from first and second data channels respectively. A shifted second clock is connected to a LSB memory address input. A rough address produced by a counter clocked by a first clock or its inversion is connected to the remaining memory address inputs if the first or second output channel is connected. The arrangement has a memory element with at least one data input and an address output, whereby the data input is alternately connected to output channels of the photosensitive component, whereby data for lower addresses and for higher addresses are successively read from the first and second data channels respectively and the memory element is larger than the number of pixels in the component. A rough address (RA) is produced by an incremental counter clocked by a first system clock (CLK). A second system clock (CLK1) shifted with respect to the first is connected to a LSB memory address input and the rough address is connected to the remaining memory address inputs of the first output channel is connected and inverted rough address is applied if the second output channel is connected. An Independent claim is included for a method of temporarily storing data for a pixel-oriented photosensitive component.

Description

The invention relates to a method and a device for temporarily storing data pixel-oriented, photosensitive component.

To increase the readout speed when acquiring the output data, for example a CCD sensor, the respective sensor is provided with a plurality of outputs so that more information can be read out in parallel at the same time. The following advantages result for the application of the respective sensor:

• 1. A reduction in the drive clock frequencies to reduce the current account and Current load in the area of the control clocks, since mostly high capacitive loads are driven Need to become.
• 2. A reduction in video output stage requirements.

An internal assignment to the respective video output with simultaneous parallel control to ensure, the sensor field is segmented. This results in relation to the Recording format of the sensor a nested reading of the corresponding sensor information. After the acquisition of the sensor data in a subsequent data processing system mostly the task of a data stream corresponding to the optical image for data correction and to create storage.

If the sensor data is directly, i.e. nested, read out and recorded, a must always Sorting by hardware or software. A representation of this signal stream as identical serial signal is only possible through additional post-processing (by hardware or software) possible. In addition to a normal additive signal correction (e.g. pixel-related Dark current correction) may also be macropixels (summarizing from an optical point of view) successive pixels) or a PRNU correction (e.g. pixel-related sensitivity correction to compensate for the edge drop of an optic) this can only be accomplished with considerable hardware or software expenditure. At Time-critical applications face the considerable hardware or software expenditure of a fast  Processing of the desired signals directly in the opposite direction.

US Pat. No. 6,172,352 B1 describes a storage element for temporarily storing data pixel-oriented photosensitive component with several parallel-operated output channels known. The memory element has a data input and an address input, the Data input alternately with the output channels of the photosensitive component via a Multiplexer is connected, the order of the data at the data input is not the Order of the pixels of the photosensitive element corresponds.

The invention is therefore based on the technical problem, a method and an apparatus for To temporarily store data of a pixel-oriented photosensitive component, by means of which an identical serial signal stream can be generated with little technical effort is.

The solution to the technical problem results from the objects with the characteristics of Claims 1 and 7. Further advantageous embodiments of the invention result from the Subclaims.

For this purpose, a raw address is generated by means of an incrementing counter System clock is clocked, and a second system clock, which is shifted to the first system clock is, the second system clock at least with the LSB address input of the memory element is connected, the raw address from the remaining address inputs of the memory element is present when the first output channel is switched to the data input and the inverted Raw address is present at the other address inputs when the second output channel is on the Data input of the memory element is switched. This will result in minimal circuitry generates an address regime by means of which the data of the pixels are sequential in the correct order be written into the memory element. The effort consists only in a counter and a second system clock shifted to the first system clock. The necessary inversion of the Meter reading, some of the usual meters even have inverting outputs, does not represent a large circuit effort in digital technology.  

The solution shown for generating a digital data stream, the internal arrangement of which Data values represent a direct image of the recorded optical image, enables a strong Simplified further processing of the sensor signals, such as macropixel formation and PRNU correction in the linear address space.

Since the output and transmission of the formed sensor data corresponds to the optical image, is also direct linear addressing of correction values both when writing and later  possible when reading out, so that no complicated and possibly very hardware-intensive Address calculations for programming the correction value memory must be made. The segmentation of the temporary storage element makes it possible, on the one hand, to Forming sensor data is read into the temporary memory and simultaneously formed Sensor data for the subsequent signal correction are provided.

If the inversion is not performed internally in the meter, this can preferably be done via XOR Gates are generated, each bit of the raw address being assigned an XOR gate, at the the respective bit of the raw address on one input and the system clock on the other input is created.

In a further preferred embodiment, the second system cycle is 90 ° to the first System clock shifted so that the raw addresses of the meter are stable in terms of run times before the LSB changes.

In a further preferred embodiment, the memory element is in the form of a dual-port RAM trained so that you can write and read at the same time, the Further processing of the sensor data is increased by a factor of two, which in turn is used in applications Supported or made possible in real time.

The photosensitive, pixel-oriented component is preferably in the form of a CCD line or lines or as CCD matrix formed.

In a further preferred embodiment, the device for generating a Read address for the memory element another incremental counter, which is a comparator is assigned a threshold value that is half of the maximum addressable data volume of the When the sensor reaches it, the counter reading is inverted and loaded as a new counter reading becomes.

The invention is explained in more detail below on the basis of a preferred exemplary embodiment. The  Figure show:

Fig. 1 is a schematic representation of a dual-port RAMs with 16 memory locations,

Fig. 2 is a schematic representation of a CCD line scanner with four output channels

Figure 3 is a schematic block diagram of a direction Bilddatenverarbeitungsein.,

Fig. 4 is a schematic block diagram for generation of the address for writing the data in a memory element,

Fig. 5, an exemplary waveform for the circuit of Fig. 4,

Fig. 6 is a schematic representation of the memory element after registered and

Fig. 7 is a schematic block diagram for generation of the address for reading the data from the memory element.

A memory element with 16 memory locations is shown by way of example in FIG. 1, the binary address being shown in the individual memory locations. There is any date on the storage space. As arranged by the two outer arrows, the memory element should be constructed in such a way that the data can be read out via two output channels, the data of the addresses 1-8 via the left output channel and the data of the addresses 16-9 via the right output channel can be read out one after the other. If one now looks at the binary addresses, it is found that the addresses of the memory locations present at the same time on the two output channels can be represented in binary form as an inversion of the others.

The device according to the invention for Buffering data of a pixel-oriented, photosensitive component are explained.  

In FIG. 2, a 12 k-CCD line sensor is shown schematically, whose data are read out in parallel from the four output channels, over the first two left output channels, the optically at the leftmost optical pixel and the other two furthest the optically at the right arranged optical pixels can be read out. Thus, the data read out are no longer in the correct order of the image recorded by the CCD line sensor, which is to be remedied by the device shown schematically in FIG. 3. The circuit initially comprises four analog-to-digital converters A / D 1-4, each of which is assigned to a data output channel of the CCD line sensor. The output data of the four analog-digital converters A / D 1-4 can be switched in succession to a data input D of a dual-port RAM DPR via a multiplexer MUX or a suitable tri-state control of the outputs of the A / D converters. whereby an associated memory address for the dual-port RAM DPR is generated by means of an address generator AG 1 and a corresponding read-out address for the dual-port RAM DPR is generated by means of a second address generator AG 2, so that at the output of the dual-port RAM RAMs DPR the data stream is again arranged in the order of the figure. As a result, this can easily be processed in a subsequent image processing unit BVE with correction data KOR. Before the specific embodiments for the address generators AG 1 and AG 2 are described, the preliminary consideration from FIG. 1 should first be transferred to the representation according to FIG. 2.

Table 1

Table 1 shows how the output signals correspond to the optically consistent pixel numbers be assigned. The generation of corresponding memory addresses would only be extensive  Hardware possible through adder with signed calculation. It is important to minimize this effort. Therefore, in continuation to Tab. 1, a memory address assignment according to Tab. 2 is proposed Hexadecimal memory addresses specially marked here refer to Memory segment with a maximum of 16384 addressable memory locations in which more than the 12000 at least the necessary memory locations for the temporary storage of a complete CCD line available.

Table 2

As can be seen from Table 2, half of the 12,000 pixels are incrementing starting from 0 written towards the middle of the memory while the other half from the end of the memory (3FFFH) starting with decrementing towards the middle of the memory.

In order to be able to better illustrate the principle of memory address generation, they are already shown in Table 3 Assignments known from Tab. 2 between readout clock, CCD output and hexadecimal Memory location address in an equivalent representation of readout clock, CCD output and binary Storage location address changed.  

Table 3

Based on the values generated in Table 3, the following address formation rule can be defined:

• 1. For each read cycle CLK of the CCD sensor is a simple (value +1) incrementing Raw address RA formed.
• 2. The least significant address bit C of the address counter to be created is closed by a through 90 ° CLK shifted clock CLK1 formed.
• 3. The individual address bits of the raw address RA are each identified by a logical XOR Link with CLK formed as value B.
• 4. The memory address A is synthesized from the temporarily stored values B and C.

FIG. 4 shows a possible embodiment for implementing this formation rule for the address generator AG 1, it being assumed that the complete address is (n + 1) bits long, where (n + 1) according to the example in Table 3 14 is. The circuit comprises an incrementing counter Z which generates a raw address RA, the raw address RA forming the uppermost n bits of the address bits of the lower pixels. Each individual bit of these n bits is linked via an XOR gate to the first system clock CLK, by means of which the counter Z is also incremented. The output signal B represents the uppermost n bits of the address bits for the dual-port RAM DPR. The LSB C of the address signal A is formed by a second system clock CLK 1, which is shifted by 90 ° to the first system clock CLK. As can be seen from the signal curve in FIG. 5 for any point in the sequence, the raw address RA is incremented by the positive edge of the first system clock CLK, the second system clock CLK 1 still being low. Due to the high state of CLK, the raw address RA is only switched through via the XOR gates. The second system clock CLK1 is still low, so that the LSB C is also low. A = RA + C is therefore the desired address for CCD output 1. Due to the 90 ° shift, CLK1 then changes to high, so that the desired address for CCD output 2 is generated. With the negative edge CLK, the XOR gate invests the raw address RA, with CLK1 still high. This represents the desired address A = RA + C for CCD output 3. Then CLK1 goes low and the desired address for CCD output 4 is set.

As can be seen from FIG. 5, two clock cycles CLK and CLK1, which are phase-shifted by 90 °, can be used to generate exactly the address sequence which is necessary in accordance with the task described, without major hardware expenditure. No arithmetic hardware expenditure is required and nevertheless a four times higher address change frequency is generated in relation to the clock CLK. In an electronic system, the output signals A can of course be latched off with the system clock in order to avoid spikes when activating memories. The address sequence generated in this way generates the memory addresses necessary for storing digitized sensor data. The data values stored herewith are now located in two areas of the memory symmetrically to the center of the memory.

The result is shown in Table 4 and Fig. 6 below. The first 6000 pixels are stored chronologically on the first addresses and the second 6000 pixels (6001-12000) are stored chronologically on the last addresses, the middle of the memory being empty. This enables a very simple address generation for reading out the temporarily stored data

Table 4

As can be seen from Table 4, the first half of the cached digitized Sensor signals (pixels 1 to 6000) from the hexadecimal address 0000 \ H to Address 176F \ H can be addressed incrementally with the value 1. The to address the 6001. Pixel necessary address is obtained by simply negating all address bits of the address of the 6000th pixel synthesized. The subsequent addresses of the cached Sensor signals are now again through a counter incrementing with the value 1 up to End of storage generated.

In FIG. 7 shows a possible circuit implementation of this rule is shown for the second address generator AG2. The counter Z2 counts up to the address of the 6,000th bill point. As a result, the first 6000 pixels were read out chronologically. The address of the 6000th pixel is also the threshold value S of a comparator KOMP, which generates a load pulse, so that the address fed back via an inverter is loaded as a new counter reading. The binary inverted address of the 6000th pixel is exactly the address of the 6001st pixel. Then the counter is simply up to the address of the 12,000. Incremented pixel. The counter then starts again from zero.

The described method and the described device can also be extended to elements with more than 4 output channels. In an embodiment with 8 output channels, only the two lowest bits of the address have to be generated by the system clocks. The two system clocks can be used, for example, to generate a sequence:
00
01
10th
11
are linked, the upper bit being generated simply by negating CLK and the lower bit by a link CLK ⊕ CLK1. However, another sequence with fewer changes of state, for example, can also occur for reasons of power loss
00
01
11
10th
be better, in which case only the output channels 3, 4 or 7 and 8 have to be exchanged accordingly.

Claims (10)

1. Device for temporarily storing data of a pixel-oriented photosensitive component, comprising at least one pixel-oriented photosensitive component with at least two output channels operated in parallel, the order of the data on the output channels not corresponding to the order of the pixels on the photosensitive component and a storage element with at least one data input and an address input, the data input being mutually connectable to the output channels of the photosensitive component, the data of the lower addresses being successively read out via the first output channel and the data of the upper addresses being successively read out via the first output channel, the memory element being greater than the number of pixels of the photosensitive element Component is characterized in that a raw address (RA) can be generated by means of an incrementing counter (Z), which is clocked by a first system clock (CLK), and a second system clock (CLK1), which is shifted to the first system clock (CLK), the second system clock (CLK1) being connected at least to the LSB address input of the memory element, the raw address (RA) being applied to the remaining address inputs of the memory when the the first output channel is connected to the data input (D) and the inverted raw address is present at the address inputs when the second output channel is connected to the data input (D) of the memory element. 2. Device according to claim 1, characterized in that the bits of the raw address (RA) are each linked to the first system clock (CLK) via an XOR gate. 3. Device according to claim 1 or 2, characterized in that the second system clock (CLK1) is 90 ° out of phase with the first system clock (CLK). 4. Device according to one of the preceding claims, characterized in that the Memory element is designed as a dual-port RAM (DPR).   5. Device according to one of the preceding claims, characterized in that the pixel-oriented photosensitive component is designed as a CCD sensor. 6. Device according to one of the preceding claims, characterized in that the Device for generating a read address for the memory element a second Incrementing counter (Z2), to which a threshold value (S) is assigned, which the corresponds to the highest address of the date read in via the first output channel at the counter reading is inverted and loaded as a new counter reading. 7. Method for temporarily storing data of a pixel-oriented photosensitive Component, by means of at least one pixel-oriented photosensitive component, with at least two parallel operated output channels, the order of the data the output channels not the order of the pixels on the photosensitive device corresponds and a storage element with at least one data input and one Address input, whereby the data input alternates with the output channels of the Photosensitive component is connected, the. Via the first output channel Data of the lowest addresses and the second output channel the data of the upper Addresses are read out successively, the memory element being larger than the number is the pixel of the photosensitive component, characterized in that by means of an incrementing counter (Z) a raw address (RA) by a first one System clock (CLK) is generated by means of a second system clock (CLK1), which is the first System clock (CLK) is shifted, at least the LSB address input of the memory element is applied, the raw address (RA) on the remaining bits of the address input of the Memory element is present when the first output channel on the data input (D) of the Storage element is switched and the inverted raw address on the other bits of the Address input is present when the second output channel on the data input (D) of the Storage element is switched. 8. The method according to claim 7, characterized in that the first and / or second System clock for switching the output channels of the photosensitive component to the  Data input of the memory element is used. 9. The method according to claim 7 or 8, characterized in that the second system clock (CLK1) is 90 ° out of phase with the first system clock (CLK). 10. The method according to any one of claims 7 to 9, characterized in that an address signal for reading out the data is generated by a second incremental counter (Z2), the one Threshold value (S) is assigned, which is the highest address of the first output channel corresponds to the read-in date, when reached the counter reading is inverted and as a new one Meter reading is loaded.