DE10219396A1 - Semiconductor memory cell with storage capacitor consisting of two electrodes, sandwiching ferroelectric storage region containing several ferroelectric storage dielectric sections - Google Patents

Abstract

The memory cell contains a storage capacitor (C) formed by two electrodes (BE,TE) sandwiching ferroelectric dielectric storage region (F), containing several ferroelectric sections (F1...Fn). Pairs of sections have different characteristics, e.g. electric properties. Due to the different characteristics, can be formed in the sections a corresponding number of binary individual polarisation states (P1...Pn). Thus a number of binary bits can be stored in storage capacitor. Independent claims are included for semiconductor memory and method of operation of the memory cell.

Description

The invention relates to a memory cell, in particular Semiconductor memory cell according to the preamble of Claim 1, a semiconductor memory device according to the Preamble of claim 14 and an operating method for the memory cell.

One of the main efforts in the further development modern storage technologies is increasing the Integration density or storage density, that is the pro Area unit of information that can be stored in the storage device. there So far, the reduction in the structure sizes of the Storage cells underlying storage devices favored.

Another aspect to increase the per unit area Storage device available storage volume is the provision of memory cells, the higher value Information units in the form of multiple states in one place in the Allow multi-level storage. Other Methods provide so-called multi-bit storage technologies, at which in a cell at different, but spatially one closely adjacent location of the memory cell with two possible states, so that A total of several binary bits can be stored in one memory cell are.

For non-volatile and especially ferroelectric Storage devices is storing multiple states in a single cell due to the course and in particular due to the steep rise in ferroelectric Hysteresis curve in the area of the coercive voltage of the storage medium very difficult.

The invention has for its object a ferroelectric memory cell and a cell based thereon Specify semiconductor memory device, in which on particular simple and yet reliable way of density storable information can be increased. Another The object of the present invention is a corresponding operating method for the invention To provide memory cell.

The task is performed in a generic memory cell, in particular semiconductor memory cell according to the invention the characterizing features of claim 1 solved. Further the task with a generic Semiconductor memory device according to the invention by the characterizing Features of claim 14 solved. Furthermore, the Invention underlying object by a Operating method according to the invention by the characterizing features of Claim 15 solved.

A generic memory cell and in particular the Semiconductor memory cells have a storage capacitor. This is formed by a first electrode device and a second electrode device. Essentially between the two electrode devices is an im Main ferroelectric memory dielectric area formed, due to its ferroelectric properties Information storage by forming a retentive Polarization state possible in a non-volatile manner is.

The memory cell according to the invention is thereby characterized in that the storage dielectric region a plurality in Essential ferroelectric dielectric individual areas having. The dielectric individual areas have pairs different characteristic properties. In particular, the individual dielectric regions differ in pairs in terms of their characteristic electrical Characteristics. Because of the different characteristic properties of the dielectric individual areas is in Dielectric range and especially in the Dielectric single areas a corresponding plurality of binary Individual polarization states can be formed, whereby in Storage capacitor a corresponding number of binary bits can be stored.

It is thus a key aspect of the present invention that essentially ferroelectric Memory dielectric region of the memory cell in a plurality To divide individual dielectric areas, which in turn one can realize ferroelectric memory effect. Thus, in the A plurality of individual dielectric regions provided in each case binary polarization single state are formed, wherein then the entirety of the plural binary Polarization individual states defined a plurality of binary bits. This binary Bits then encode a corresponding information content, namely by superimposing the individual polarization states the dielectric individual areas to one Overall polarization state of the dielectric region of the memory cell.

In an advantageous embodiment of the invention Memory cells are the individual dielectric areas with regard to their retentive polarization or polarizability, their dielectric constants or dielectric numbers, Coercive field strengths, coercive voltages, access and / or Switching times and / or a combination of these quantities trained in pairs differently or differently. To this Way, in a simple form, there is the possibility different or same materials, which are different have electrical characteristics, for example due to a different texture, appropriately to combine with each other so advantageously that a the highest possible density of information in a whole Dielectric range by the plurality of Dielectric single areas can be realized. According to their material Properties can be different materials with each other be combined to take this multiplication effect into account towards the memory content or information content realize.

The structure of the memory cell according to the invention when the Dielectric individual areas in each case contiguous, one-piece, one-piece and / or the like, in particular simply coherent are. This has particular advantages in terms of process technology the realization of a manufacturing process for the memory cell according to the invention.

A further simplification of the structure of the Dielectric range arises when this is a result of layers is formed, with one layer through one of the Dielectric single areas is formed.

The direction of the sequence of the Layers essentially as a direction from one of the Electrode device to the other of each Electrode devices selected.

In a particularly advantageous embodiment, for example, one of the dielectric individual regions is essentially formed from SBT or the like, or it has this as a material. In particular, a specific polarization or specific polarizability of 4-20 μC / cm ² , a coercive voltage of 0.4 V, in particular with a layer thickness of 90 nm, and / or a write, switchover or state change time τ1 = τ _SBT of about 50 ns is provided.

In another advantageous embodiment of the memory cell according to the invention, one or another of the dielectric regions is essentially formed from PZT or the like or has this as a material, in particular with a specific remanent polarization or specific polarizability of approximately 40 μC / cm ² , a coercive voltage of approximately 1 V, in particular with a layer thickness of approximately 90 nm, and / or a write, switchover or state change time τ2 = τ _PZT of approximately 100 ns, in particular at 1.6 V.

• a) Reine Materialien, zum Beispiel BaTiO₃, PbTiO₃, usw.
• b) Mischungen aus reinen Materialien, zum Beispiel (Ba, Pb)TiO₃, SrBi₂(Ta, Nb)₂O₉, usw.
• c) Nichtstöchiometrische Materialien der oben genannten, zum Beispiel Sr_0,85Bi_2,2Ta₂O₉.
• d) Dotierte reine oder gemischte oder nichtstöchiometrische Materialien, zum Beispiel La-dotiertes PZT (auch PLZT).
• e) Polymere, zum Beispiel PVDF.
• f) Copolymere, zum Beispiel PVDF/TRFE.

The following other ferroelectric materials are conceivable and usable:

• a) Pure materials, for example BaTiO ₃ , PbTiO ₃ , etc.
• b) Mixtures of pure materials, for example (Ba, Pb) TiO ₃ , SrBi ₂ (Ta, Nb) ₂ O ₉ , etc.
• c) Non-stoichiometric materials of the above, for example Sr _0.85 Bi _2.2 Ta ₂ O ₉ .
• d) Doped pure or mixed or non-stoichiometric materials, for example La-doped PZT (also PLZT).
• e) Polymers, for example PVDF.
• f) copolymers, for example PVDF / TRFE.

The following ferroelectric materials are conceivable as pure materials for use: perovskite-like compounds, lithium niobate-like compounds, manganite-like compounds, tungsten-bronze-like compounds, in particular oxides, pyrochlore-like compounds, layer-like oxides, barium fluoride-like compounds, molybdates, borazites, colemanites, other oxides, antimony sulphide compounds, iodine Nitrites, nitrates, potassium dihydrogenphosphate-like sulfates and related compounds, alums, guadine compounds, selenites, potassium cyanides, triglyzine sulfates and related compounds, Rochelle salts and related compounds, metallic solids, for example also SnTe, GaTe, V ₅ Si, complex organic compounds and / or the like.

In another advantageous embodiment of the The memory cell according to the invention is the first electrode as the lower one or bottom electrode. Additionally or alternatively is the second electrode device as the upper electrode or Top electrode formed.

It is to connect the memory cell according to the invention provided that one of the electrode devices with a provided plate line device of the memory cell is connected and / or that the other electrode device with a source / drain region and in particular with the Drain area of an intended selection transistor or Access transistor of the memory cell is connected.

Basically, different architectures are available for the Storage capacitor conceivable. In a first embodiment of the The storage cell according to the invention is the storage capacitor as a substantially vertically extending capacitor trained, especially in stack architecture or in stacked architecture. On the other hand, there is also one Offset architecture conceivable for the storage capacitor.

In a variant for the construction and structuring of the Dielectric range from the different Dielectric individual areas, it is provided that between Dielectric single areas and / or groups thereof dielectric and / or electrically conductive intermediate areas, are provided in particular as layers.

Additionally or alternatively, is between Dielectric single areas and the first and / or second Electrode device each an intermediate area, in particular as a layer provided which is dielectric and / or electrical is conductive.

(Thin) layers that are dielectric (for example Al ₂ O ₃ , BTO, Bi ₃ Ti ₄ O ₁₂ ) or metallic (Pt) or also metal oxide (for example IrO ₂ , RuO ₂ ) are suitable as intermediate regions.

Reasons for introduction (examples)

• - Process engineering reasons, for example lowering the Crystallization temperature of a ferroelectric layer "seed layers". Example: BTO for SBT
• - Determination of a texture of the subsequent ferroelectric layer. Example: Al ₂ O ₃ for PZT
• - Adjustment / adjustment of the device-prescribed Voltage level to the special possible requirements of the Multibitkondensators.
• - Avoiding degradation effects in the event of long-term stress stress stress (fatigue problem). Example: SrTiO ₃ (STO) at PZT
• - Avoidance of diffusion processes between the individual ferroelectric layers, contamination effects, chemical reaction, defined interfaces.
• - Solving adhesion problems (for example using Ti or TiO ₂ for better adhesion of Pt in SBT) and balancing mechanical stress.

For further interconnection of the memory cell according to the invention a word line device is provided, which with the Gate area of an intended selection transistor device the memory cell is connected. Alternatively or additionally a bit line device is provided which is connected to the Source area of one or the intended Selection transistor device is connected. Further alternatively or additionally is a sense amplifier device for reading out the Information content and to provide the read information intended.

The generic semiconductor memory device has one Plurality of memory cells and is thereby characterized in that memory cells according to the invention are provided.

Another aspect of the present invention is that Providing an appropriate operating procedure for the memory cell according to the invention. In particular, it is too take into account that an electrical influence on the entire dielectric range or Memory dielectric area Influences on all dielectric single areas be exercised. The operating method for the memory cell according to the invention must take this into account Take into account when selective writing or reading the individual dielectric areas are to be realized.

In the operating method according to the invention for the The memory cell according to the invention is used when or for reading out a Total polarization stored in the storage capacitor Bit information successively the storage capacitor for a reading voltage pulse is applied for a certain time. A resulting reading current pulse and / or one Resulting reading charge quantity are measured and as a measured value provided. The provided measured values or the Measured value ranges of the measured values are bit combinations according to the invention assigned. The one measured and provided The bit combination assigned to the measured value is determined and as stored stored read from the storage capacitor n-bit information provided and / or output.

A fundamental aspect of the present operating procedure is that when reading out the total polarization of the Dielectric range, i.e. the superposition of the Individual polarization states of the dielectric individual regions quasi as Representation of the stored n-bit information viewed becomes. The storage capacitor will last for a period of time acted upon with a reading voltage pulse, in which Follow a reading current pulse or an output one Reading charge amount is measurable. An underlying mapping between possible measured values or ranges of measured values corresponding possible n-bit information is used to determine the measured and provided measured value with a to connect the corresponding assigned bit combination. The for the respective measured value or its measuring range assigned bit combination is then called n-bit information provided and / or issued.

Another aspect of the present invention is that Provide another operating method for the Memory cell according to the invention, in which at or Write one as a total polarization in the storage capacitor n-bit information to be stored is first the one to be stored n-bit information is provided as a bit combination. To the bit combination provided is assigned first sequence of individual polarization states determined, which serve as target levels for the individual dielectric areas should. Then one of the first episodes of Second sequence of voltage signals assigned to individual polarization states determined. The storage capacitor then follows according to the second sequence of voltage signals with these Voltage signals applied, whereby the Dielectric single areas the respectively assigned Individual polarization states are impressed.

It is therefore a key aspect of this operating method for the memory cell according to the invention when writing the Establish correspondence between the ones to be saved n-bit information and a corresponding overall polarization for the Storage capacitor. The total polarization to be written or n-bit information corresponds to a bit combination, which again a sequence of individuals Individual polarization states for the dielectric individual regions as target states is assigned or assigned. So it has to be Total polarization as a superposition of the sequence of Individual polarization states in the dielectric individual regions are determined become. From the found sequence or sequence of Individual polarization states for the dielectric individual regions results then an assigned sequence or sequence of Voltage signals, by which when the Storage capacitor with the corresponding memory signals assigned first sequence of individual polarization states in the Dielectric single areas is generated in each case. After this Loading the storage capacitor with the sequence of Each of the voltage signals then has Dielectric individual regions the polarization individual state assigned to it, whose superposition is that of the n-bit information to be stored corresponding total polarization in the storage capacitor results.

Preferred embodiments of the operating method which is used for writing, and the operating procedure, which is used for reading is that combining reading and writing become.

In a particularly advantageous embodiment of the Operating method according to the invention is the assignment between Bit combinations and the first sequence of Individual polarization states and / or assignment between measured value ranges and bit combinations, in particular in the form at least one table, at least one list and / or the like, and in each case these assignments also become these Specifications taken. Such a table leads to Example from the values of the retentive polarization of the individual ferroelectric layers.

In further advantageous embodiments of the Operating methods according to the invention are intended for writing Writing order in relation to the Dielectric individual areas and the voltage signals to be impressed determined and / or complied with.

The respective writing order is determined by the characteristic properties of the individual dielectric regions determined, in particular by mutual proportions of their values.

It is particularly advantageous that due to the given or determined writing order in each case Dielectric single areas with higher coercive voltage before each Dielectric single regions with low coercive voltage to be discribed.

This is particularly useful if, with regard to the Coercive voltages different Dielectric single areas when writing with differently aligned Individual polarization states are to be formed. By an orientation on the individual dielectric area with the The greatest coercive voltage is the layer which has the greatest coercive voltage, with one predetermined polarization state, wherein also all other layers at the same time Preserve polarization direction, since their coercive voltage is smaller. Then, for example, the next layer smaller coercive voltage oppositely polarized are applied accordingly oppositely directed voltage signal instead and generated one opposite to the polarization written first directional polarization for all subsequent layers lower coercive voltage, but with that layer the largest coercive voltage is not polarized.

Appropriate programming then takes place in the order from larger to smaller coercive voltages instead, so all dielectric individual areas independently polarized and thus described or can be programmed.

In particular, the writing processes can be optimized , for example, if you want to write consecutively or identical dielectric states to be polarized should have aligned polarization directions. Then namely the application of a corresponding one is sufficient Voltage pulse on a group as a one-time action because Dielectric single areas of this group, which lower Have coercive voltages, just not opposite need to be polarized. You have to be explicit Only then will the polarity be reversed again in the layer or layers which are polarized in opposite directions have to.

An alternative or additional approach to selective writing is based on the given or determined writing order in each case Dielectric single areas with a longer switchover time Describe individual dielectric areas with a shorter switchover time. there you don't start with the highest coercive voltage, but with the longest switching time as the application time for the voltage signals and then works the Voltage signals in the order from higher to lower Switching times from.

These and other aspects also result from the following comments:
The present invention is concerned with increasing the storage density of non-volatile ferroelectric memories. This problem is to be solved by storing several bits per memory cell.

One of the most strongly pursued strategies for Increasing the storage density is reducing the Structure sizes (feature size), which consequently also includes the memory cells must be reduced in their structure sizes. This is at Ferroelectric storage with considerable process engineering problems, e.g. B. in structuring the ferro Materials and the electrodes, in 3-D structures, connected.

In the case of non-volatile memory cells based on Charge storage based will also be another way of increasing the Storage density by storing more than one bit in walked in a cell. Both multi-level cells, Storing more than two states in a cell, as well Multi-bit cells, storage of two states each different locations in a cell are conceivable.

With ferroelectric memories, the storage of multiple states in one cell due to the steep rise the hysteresis curve in the area of the coercive voltage very much difficult.

The invention solves the problem by several ferroelectric layers with different dielectric numbers in a ferroelectric capacitor can be integrated. By suitable choice of materials and / or by suitable thickness of the individual layers, selective writing and Reading the state of ferroelectric polarization from every single shift. To do this special read and write procedures proposed.

• - Multibitspeicherung pro Speicherzelle bzw. pro Auswahltransistor und damit
• - Verdopplung/Vervielfachung der Integrationsdichte
• - keine Veränderungen im vorgegeben Prozessablauf des Kondensatormoduls, d. h.: keine zusätzlichen Lithographieebenen und Ätzschritte, bis auf lediglich die Abscheidung und evtl. Temperung einer oder mehrerer zusätzliche ferroelektrischen Schichten im Kondensatormodul,
• - keine wesentliche Änderung im Frontend- oder Backendflow,
• - keine wesentlichen Veränderungen im Lesezyklus,
• - schnelleres Erreichen von High-Density FeRAMs, Wettbewerbsvorteil, schnellerer Markteintritt, im Vergleich zu Konkurrenten, und
• - Verzicht auf prozesstechnisch kompliziertere Speicherarchitekturen, zum Beispiel Stacked Capacitor, möglich bei gleichem Resultat, d. h.: Unter Umständen erreicht man mit der Flächeneinsparung durch einen derartigen Multiferroelektrika-Kondensator einen vorübergehenden Wettbewerbsvorteil auf dem nichtflüchtigen Speichermarkt, wenn man zunächst auf die prozesstechnisch nicht so aufwendige Offset-Architektur zurückgreift. Auf längere Sicht, wenn die Integration der Stacked Capacitor Prozesse erreicht wurde, ist in jedem Fall mit einem Wettbewerbsvorteil hinsichtlich höherer Speicherdichte zu rechnen gegenüber Firmen die keinen Multibit-Kondensator verwenden.

The advantages of the proposed arrangement are:

• - Multi-bit storage per memory cell or per selection transistor and thus
• - Doubling / multiplying the integration density
• no changes in the specified process sequence of the capacitor module, ie: no additional lithography levels and etching steps, apart from the deposition and possibly annealing of one or more additional ferroelectric layers in the capacitor module,
• - no significant change in the frontend or backend flow,
• - no significant changes in the reading cycle,
• - faster achievement of high-density FeRAMs, competitive advantage, faster market entry compared to competitors, and
• - Dispensing with more complex storage architectures in terms of process technology, e.g. stacked capacitors, is possible with the same result, i.e.: Under certain circumstances, the space saved by such a multiferroelectric capacitor can achieve a temporary competitive advantage in the non-volatile memory market if one initially focuses on the process technology-less complex offset Architecture. In the longer term, if the integration of the Stacked Capacitor processes has been achieved, a competitive advantage in terms of higher storage density can be expected in any case compared to companies that do not use a multibit capacitor.

A first inventive idea consists in the vertical stacking (layering) of different ferroelectric films or layers, which differ significantly in the characteristic electrical properties with regard to remanent polarization P _r , dielectric constant ε in combination with coercive field strength E _c and / or the minimum required access time for the writing or switching of the retentive polarization.

A second inventive idea consists in the method for reading out and / or writing to the storage capacitor. To read out the multi-bit state, the clear difference in the remanent polarizations of the different layers / materials is used. Each quantity of charge arriving at the signal amplifier can be uniquely assigned to a bit state in the storage capacitor. The description of the capacitor or the impressing of the m = 2 ⁿ bit states in the capacitor may be carried out with the aid of a multi-stage process using different coercive field strengths or voltages of the different material layers or using different switching times or any other physical property, on the basis of which a selective one Describing the different layers is made possible. Combinations of the above-mentioned writing methods can also be used.

In the following, the n-bit storage is exemplified in 1- Transistor 1 capacitor 1T-1C design, for example integrated as Stacked-Capacitor- or Offset-Capacitor- Architecture.

Let n ferroelectric layers be stacked within the capacitor, which differ in their remanent polarization P _r .

In this embodiment, the description of the individual bit states using different Voltage levels happen. The construction of the capacitor corresponds to the stratification of n different materials than one Voltage divider. Since you look at the differences when describing in the coercive field strength, you have to make sure you go for describing the layer you want finds a suitable minimum voltage or coercive voltage.

For a simplified description, the layers are arranged below in such a way that the layer indicated with layer 1 corresponds to the layer deposited first and at the same time has the lowest coercive voltage. In general, the individual materials can be layered in any order. In the case of an n-layer system, the voltage dropping at the i-th layer corresponds to the voltage divider formula and insofar as the layers are arranged in a planar manner:


with i, k = 1,. , ., n. Here, d denotes the layer thickness, ε the dielectric constant, U the voltage applied to the capacitor plates and U _i the voltage dropping across the i-th layer.

This is done by adapting the layer thicknesses d to the dielectric constant of the materials used, as listed in the following calculation. A specific embodiment in the context of 2-bit storage per cell is obtained if the known ferroelectric materials SrBi ₂ Ta ₂ O ₉ (SBT) are used in combination with Pb (Zr, Ti) O ₉ (PZT).

Reading information

As with most FeRAM concepts, it is about reading out the bit information (here: bit information) a destructive process, d. H. the imprinted condition is changed by reading out and must in a subsequent step be re-registered again.

With a sufficiently high read pulse, i. H. with at least so high amplitude that the layer 1 and layer 2 falling voltages to switch the retentive Polarization can lead to the senseamplifier or Charge amplifier has clearly discharged the existing bit states can be assigned. Here comes to Wear that the two materials have significant differences in the remanent polarizations. Depending on This results in clear differences in the initial state Readout currents via the bit line.

A layer system is a further embodiment called, in which between one or more ferroelectric Layers or at the interface to the electrode dielectric or conductive layers that are not are contacted on the outside, are inserted.

One reason for inserting such layers could be that certain textures of those above it ferroelectric layer to be achieved.

Describe the memory cell

Writing requires two different threshold voltages via the ferro condenser (version 1) or two different ones Pulse durations (version 2).

Version 1

An example of how the sequence of voltage pulses and levels is now shown. Should both Bit states are switched, a voltage is required which is so large that the layers F1 and F2 falling voltages are at least as high as that corresponding coercive voltages and thus a switching process cause. Should only the polarization of the layer with the smaller coercive field strength can be switched (here F1 or SBT), the one falling on the capacitor module Voltage just so great that only layer F1 is polarized, and however the voltage drop across F2 be less than the coercive voltage of layer F2. On Writing to F2 without changing F1 is only possible if both layers are first described with one sufficiently high voltage at the ferro capacitor c and then with a lower voltage as described above Layer F1 is rewritten again.

Version 2

One can selectively describe the individual layers also achieve using the existing differences in the switching times.

A combination of version 1 and version 2 is also possible.

Criterion for the functionality of the multibit FeRAM and for the setting of layer thicknesses:
The voltage divider rule for the series connection of two capacitors is:

The capacitance C of plate capacitors with area A and thickness d is calculated


where ε _{0 is} the dielectric constant of the vacuum and ε is the dielectric constant of the layer located between the capacitor plates.

A prerequisite for the functionality of the multibit capacitor is that the layer that has a lower coercive field strength (in this example, be E _C1 <E _C2 ) can be switched separately without reversing the layer with the higher coercive field strength in its direction of polarization.

This means that when the voltage U is applied to the capacitor, the voltage U ₁ dropping across layer F1 must be greater than the coercive voltage U _C1 = E _C1 d ₁ required for the switchover, it also having to be satisfied that the voltage U ₂ dropping across layer F2 is smaller than their coercive voltage U ₂ = E _C2 d ₂ :

Define the size K as follows:


so you can write shortened as a necessary and sufficient condition for the basic functionality of the multibit storage capacitor

This condition is not always met. In the event that the layer with a low E _{C1 has} a high dielectric constant ε ₁ , sufficient voltage never drops to switch these switches without simultaneously switching layer F2 with a higher coercive field strength E _C2 and a lower dielectric constant ε ₂ .

Example calculation for a non-functioning material system:
Material 1: E _C1 = 100 kV / cm and ε ₁ = 100
Material 2: E _C2 = 200 kV / cm and ε ₂ = 10

It follows:


which cannot be fulfilled with any choice of the thicknesses d ₁ and d ₂ .

However, the SBT / PZT multi-bit memory model fulfills that above requirement, how to easily use the listed Can check data.

The value can be determined by choosing the layer thickness combination Set K. K enables the setting for the Switching process.

Generalization of the criterion for the functionality of the multi-bit memory:
A multibit memory is composed of a total of n layers F ₁ , F ₂ ,. , ., F _n . For a simplified description, the layers are arranged so that with increasing index number i, layers with increasing coercive field strength E _{C, I are} designated.

E _{C, 1} <E _{C, 2} <. , , <E _{C, n} , i = 1. , , n (1)

According to the voltage divider formula, the voltage drop U _i at the i-th layer results

U _tot denotes the externally applied voltage, which can be calculated from the capacitances C _{i of} the individual layers i. The capacitance C _{i of} a planar layers in the capacitor with area A, dielectric constant ε _j and a layer thickness d _{j are} calculated

By using Eq. (3) in Eq. (2) necessary conditions for the functionality of the multi-bit memory can be derived, which can be described as follows.

If there are n layers, then n externally applied voltage levels U ⁱ _{ges are} required for the function of the n multibit memory. The index i denotes the external voltage at which the i-th layer is to switch, but the (i + 1) -th layer is not.

The voltage drop at the i-th layer should be greater than its necessary coercive voltage, but less than that of the (i + 1) -th layers. It follows:

From this, n - 1 criteria can be derived, which must be fulfilled for the function of the multibit capacitor. By introducing n - 1 values for K ⁱ , the notation for the conditions can be shortened. K ⁱ is defined as follows:

The function of the multibit capacitor is fulfilled if a set of n - 1 values of K ⁱ exists, according to Eq. ( 7 ) is always fulfilled:

Dimensioning example

According to equations (1) and (2), the voltage drop across layer F1 to be switched must be Δ1 greater than the coercive voltage of this layer, while the voltage drop across the other layers must be correspondingly Δn smaller than the respective coercive voltage. In the case of two layers n = 2, this results in the relationship between the layer thicknesses, coercive field strengths and dielectric constant:

The applied voltage U must then apply

U = E _C2 .d ₂ + E _C1 .d ₁ + Δ ₁ -Δ ₂ .

The invention will be described with reference to the accompanying Drawings explained in more detail:

Fig. 1 shows in schematic form a circuit arrangement for the inventive memory cell.

Fig. 2A shows the arrangement of a memory capacitor of the memory cell of the invention.

Fig. 2B shows a memory cell of the invention in Stapelarchitaktur.

Fig. 2C shows a memory cell of the invention in offset architecture.

Fig. 3 shows hysteresis curves with respect to the dielectric region of a storage capacitor of a memory cell embodiment of the invention.

FIGS. 4A-C show a read voltage pulse as a function of time and the resulting sense current pulses as a function of time in a first embodiment of an operating method according to the invention as well as a coding table.

Fig. 5 is a general flow schematically illustrates the writing in an inventive method of operation.

Fig. 6 shows another write sequence in an inventive method of operation.

Fig. 1 shows a schematic circuit diagram for an inventive semiconductor memory cell 10, which is formed in this case of the actual storage capacitor C and a storage capacitor C accessing this selection transistor T or access transistor T.

The storage capacitor C has a first or lower electrode device BE, which can also be referred to as a bottom electrode. Furthermore, a second or upper electrode device TE is provided, which can also be referred to as a top electrode. A dielectric region F, which is also referred to as a storage dielectric region F, is provided between the first electrode device BE and the second electrode device TE. The first electrode device BE is connected to a plateline device PL of the memory cell 10 . The second electrode device TE is connected to the drain region D of the selection transistor T of the memory cell 10 . The source region S of the selection transistor T is connected to the bit line device BL of the memory cell 10 . The gate region G of the selection transistor T is connected to the word line device WL of the memory cell 10 .

Due to the respective loading of the plateline device PL, the bit line device BL and the word line device WL of the memory cell 10 , the storage capacitor C can be accessed in a reading or writing manner in order to read or write information.

FIG. 2A shows a schematic and sectional side view of the storage capacitor C to a first embodiment of the memory cell 10 of the invention. Only the first, lower or bottom electrode device BE, the second, upper or top electrode device TE as well as the dielectric area F provided between the electrode devices BE, TE, which consists of a plurality of n individual dielectric areas F1,. , ., Fn is formed. The two electrode devices BE and TE are designed approximately as plate electrodes or layer electrodes. The dielectric individual regions F1,. , ., Fn of the dielectric region F are formed as parallel plane-parallel layers between them, which have certain dielectric constants ε ₁ ,. , ., ε _n have.

In the arrangement shown in FIG. 2A, the different dielectric individual areas F1,. , ., Fn, which are also called the ferroelectric layers F1,. , ., Fn, differently oriented individual polarization states P1, P2,. , ., Pn, which overlap overall to a total polarization state P for the entire dielectric region F, which can then be read from the outside.

According to the orientation of the different Individual polarization states P1, P2,. , ., Pn are in the Dielectric single areas F1, F2,. , ., Fn corresponding binary Individual bits then formed their order and arrangement defines a corresponding bit combination 8, which one corresponds to corresponding n-bit information.

The embodiment of a storage capacitor C of FIG. 2A can be arranged in different architectures for a memory cell 10 , as shown in FIGS. 2B and 2C, which show a stacked or stacked architecture or an offset architecture.

In the stack architecture of Fig. 2B, the bottom electrode BE is connected through a polysilicon plug to the drain region D of the selection transistor T, the top electrode TE while the plate line device of the memory cell 10 is connected.

In contrast to this, in the embodiment of FIG. 2C in an offset structure, the top electrode device TE is connected via a corresponding contact area to the drain area D of the selection transistor T, whereas the bottom electrode device BE is laterally elongated and is connected to the plate line device PL of the memory cell 10 according to the invention.

Fig. 3 shows two Hystereseverläufe for two different dielectric materials, which-forming in a storage capacitor C and the two dielectric region F Dielektrikumseinzelbereichen F1 and F2 are used. The ferroelectric polarization P is shown there as a function of the applied voltage U. The remanent polarization is designated P1 and P2 and is also referred to as the individual polarization state P1, P2. The individual voltages U1 and U2 shown are also referred to as coercive voltages. These result from the coercive field strengths on the basis and as a function of the respective layer thicknesses d1 and d2 of the layers of the dielectric individual regions F1 and F2.

With the capacitor device C on which FIG. 3 is based, a total of m = 4 different polarization states P can be formed by means of two binary bits: m = 2 ⁿ = 2 ² = 4.

FIGS. 4A to 4C show, in schematic form in the form of graphs the time characteristics of a read voltage pulse U, four possible resulting from the read voltage pulse U readout currents I1 to I4, and a coding of the read currents I1 to I4 in corresponding bit combinations B1 to B4, wherein - as shown in Fig. 3 - a storage capacitor C and the two Dielektrikumseinzelbereichen F1 and F2 is taken as a basis, which have the properties in terms of coercive shown in Figure 3 and the polarization individual states P1, P2 or remanent polarization P1 and P2..

After applying a read voltage pulse U to the storage capacitor C according to the course of FIG. 4A, that is to say with an exposure time τ, one of the possible results shown in FIG. 4B results in the form of a readout current I1 to I4, which differ from one another in terms of their magnitude , Depending on the orientation of the individual polarization states ± P1, ± P2, there are different total polarizations and correspondingly different read currents I1 to I4. These readout currents I1 to I4 of different sizes are coded to one another in the form shown in the table in FIG. 4C, so that the four different polarization possibilities, corresponding to four different total polarization states, are related to one another with the four different readout currents I1 to I4.

Fig. 5 a schematic flow diagram showing in the form of a possible profile for a write operation with respect to a Dielekrikumsbereich F, which, from n Dielektrikumseinzelbereichen F1. , ., Fn is constructed, the dielectric individual regions F1,. , ., Fn with regard to their coercive voltages U1,. , ., Un according to U1 <U2 <. , , <Un distinguish.

After an initial phase in step S1, step S2 checked whether the bit with the number n, i.e. the Dielectric single area Fn is to be changed. If so, so in step S3, the write voltage to the Coercive voltage Un or a value above and / or set so that at least the coercive voltage at the nth layer drops. In step S4, the Dielectric range Fn with the corresponding positive or negative Coercive voltage Un or a voltage above or below applied as a write voltage, which accordingly the polarization state Pn is aligned positively or negatively and the corresponding bit is set to 1 or 0.

Ultimately, this will apply to all subsequent ones Dielectric single areas Fn - 1,. , ., F1 performed like that in the Steps S2 ', S3', S4 'and S2 ", S3", S4 "schematically is indicated. After going through the cascade of these steps are all n dielectric individual areas F1,. , ., Fn according to the present n-bit information I and the corresponding assigned bit combination B with a positive or negative Single polarization P1,. , ., Pn programmed.

FIG. 6 shows in schematic form the sequence of a write process for a storage capacitor C with three dielectric individual areas F1, F2, F3, the bit combination (1,0,1) being written into the dielectric area F based on the information content (0,0,0) shall be.

In the first section A1 of FIG. 6, the positive coercive voltage U3 is applied as a write voltage to the entirety of the dielectric individual areas F1, F2, F3, that is to say to the dielectric area F as a whole, so that all of the individual polarization states P1, P2, P3 are aligned positively, which is a bit combination (1,1,1).

In the subsequent step A2 of the procedure in FIG. 6, the negative coercive voltage U2 for the second dielectric region F2 is then applied to the entirety of the dielectric individual regions F1, F2, F3, that is to say to the entire dielectric region F, so that the first and second Dielectric regions F1 and F2 are negatively polarized, whereas the third dielectric region F3 remains with its positive polarization according to the individual polarization state P3. The bit combination (1,0,0) results after method step A2.

Finally, in the last method step A3, the coercive voltage U1 is again applied in positive form to the entire dielectric region F, as a result of which only the third dielectric individual region F1 is positively polarized with a corresponding positive polarization individual state P1, whereas the second and third dielectric individual regions F2 and F3 have their negative polarization P2 or maintain positive polarization P3. Overall, as desired, a bit combination (1,0,1) results from the sequence. Reference numeral list 10 memory cell
B bit combination
BE first electrode device, lower electrode device, bottom electrode
BL bit line device, bit line
B1,. , ., Bm bit combination
C storage capacitor
D drain area, drain
F storage dielectric range, storage dielectric
F1,. , ., Fn single memory dielectric regions
G gate area, gate
I readout current
I1,. , ., I4 reading current pulse
P state of polarization
PL plate line device, plate line
P1,. , ., Pn polarizability, remanent polarization, single polarization state
T selection transistor, access transistor
U read voltage pulse, read voltage
U1,. , ., Un coercive voltages, writing voltages
WL word line device, word line
τ1,. , ., τn access time, changeover time

Claims (25)

1. A memory cell, in particular a semiconductor memory cell, with a storage capacitor (C), which is formed by a first electrode device (BE) and a second electrode device (TE) and an essentially ferroelectric storage dielectric region (F) provided between them, characterized in that that the storage dielectric region (F) has a plurality (n) of essentially ferroelectric dielectric individual regions (F1,..., Fn), - That the dielectric individual regions (F1,..., Fn) have different characteristic properties in pairs, in particular electrical properties, and - That due to the different characteristic properties of the dielectric individual regions (F1,..., Fn) in the dielectric individual regions (F1,... Fn), a corresponding plurality (n) of binary polarization individual states (P1,..., Pn) can be formed and thus this plurality (n) of binary bits can be stored in the storage capacitor (C). 2. Memory cell according to claim 1, characterized in that the dielectric individual regions (F1,..., Fn) with regard to their polarizability, remanent polarization (P1,..., Pn), dielectric constants (ε1,..., Εn), coercive field strengths (E _{C, 1} ,..., E _{C, n} ), coercive voltages, access and / or switching times (τ1,..., Τn) and / or a combination of these quantities are formed differently in pairs. 3. Memory cell according to one of the preceding claims, characterized, that the dielectric individual areas (F1,..., Fn) each coherent, one-piece, one-piece and / or the like, are in particular simply coherent. 4. Memory cell according to one of the preceding claims, characterized, that the dielectric region (F) as a result of layers is formed, with one layer through one of the Dielectric single areas (F1,..., Fn) is formed. 5. Memory cell according to claim 4, characterized, that the direction of the sequence of layers is essentially towards one of the electrode devices (BE, TE) the other electrode devices (TE, BE). 6. Memory cell according to one of the preceding claims, characterized in that one of the dielectric individual regions (F1) is essentially formed from or has SBT or the like, in particular with a specific remanent polarization of approximately 4-20 μC / cm ² , a coercive voltage of about 0.4 V, in particular with a layer thickness of about 90 nm, and / or a write, switchover or state change time τ1 = τ _SBT of about 50 ns. 7. Memory cell according to one of the preceding claims, characterized in that another one of the dielectric regions (F2) is essentially formed from or has PZT or the like, in particular with a specific polarization of approximately 40 μC / cm ² , a coercive voltage of approximately 1 V, in particular with a layer thickness of approximately 90 nm, and / or a write, switchover or state change time τ2 = τ _PZT of approximately 100 ns, in particular at approximately 1.6 V. 8. Memory cell according to one of the preceding claims, characterized, that the first electrode device (BE) as a lower one or bottom electrode (BE) is formed. 9. Memory cell according to one of the preceding claims, characterized, that the second electrode device (TE) as an upper or top electrode (TE) is formed. 10. Memory cell according to one of the preceding claims, characterized in that - That one of the electrode devices (BE, TE) is connected to a provided plateline device (PL) of the memory cell ( 10 ) and / or - That the other electrode device (TE, BE) with a source / drain region (D) and in particular with the drain region (D) of an intended selection transistor (T) or access transistor (T) of the memory cell ( 10 ) is connected. 11. Memory cell according to one of the preceding claims, characterized, that the storage capacitor (C) turns out to be essentially vertically or laterally extending capacitor is, especially in stacked architecture or stacked Architecture or in offset architecture. 12. Memory cell according to one of the preceding claims, characterized, - that between individual dielectric regions (F1,..., Fn) and / or groups thereof each dielectric and / or electrically conductive intermediate areas, in particular as Layers are provided and / or - That between individual dielectric regions (F1,..., Fn) and the first and / or second electrode device (BE, TE) each dielectric and / or electrically conductive Intermediate areas, in particular as layers, are provided. 13. Memory cell according to one of the preceding claims, characterized in that - That a word line device (WL) is provided, which is connected to the gate region (G) of an intended selection transistor device (T) of the memory cell ( 10 ), and / or - That a bit line device (BL) is provided, which is connected to the source region (S) of one or the provided selection transistor device (T), and / or - That a sense amplifier device (SA) is provided. 14. Memory cell according to one of the preceding claims, characterized in that the strengths d _i , the coercive field strengths E _{C, i} and dielectric constants ε _{i of} the i-th and (i + 1) -th layer for all i = 1,. , ., n - 1 the conditions


are sufficient, where U ⁱ _{ges means} the external voltage applied to the capacitor, so that the i-th layer can be switched and the (i + 1) -th layer cannot be switched. 15. A semiconductor memory device with a plurality of memory cells ( 10 ), characterized in that the memory cells ( 10 ) are designed according to one of claims 1 to 13. 16. Operating method for a memory cell according to one of claims 1 to 14, in which for reading out an n-bit information (I) stored as total polarization (P) in the storage capacitor (C) in succession: the storage capacitor (C) is subjected to a read voltage pulse (U _L ) for a certain time (τ), a measured reading current pulse (I _L ) and / or a resulting read charge quantity (Q _L ) are measured and made available as a measured value (M), - a bit combination (B) assigned to a measured value range (MB) of the measured value (M) or the measured value (M) is determined and - The determined bit combination (B) is provided and / or output as stored n-bit information (I) read from the storage capacitor (C). 17. Operating method according to claim 16, characterized, that to write one as an overall polarization (P) in Storage capacitor (C) n-bit information to be stored in succession: - The n-bit information (I) to be stored as a bit combination (B) is provided - a first sequence (SP) assigned to the bit combination (B) Individual polarization states (P1,..., Pn) as target states of the Dielectric individual regions (F1,..., Fn) is determined, - one of the first episodes (SP) of Second sequence (SU) assigned to individual polarization states (P1,..., Pn) Voltage signals (U1,..., Un) is determined, - The storage capacitor (C) according to the second sequence (SU) Voltage signals (U1,..., Un) with the voltage signals (U1,..., Un) is applied and - thereby the dielectric individual areas (F1,..., Fn) the assigned individual polarization states (P1,..., Pn) be imprinted. 18. Operating method for a memory cell according to one of claims 1 to 14, in which for writing an n-bit information to be stored as a total polarization (P) in the storage capacitor (C) in succession: the n-bit information (I) to be stored is provided as a bit combination (B), a first sequence (SP) assigned to the bit combination (B) (individual polarization states (P1,..., Pn)) is determined as the desired states of the dielectric individual regions (F1,..., Fn), a second sequence (SU) voltage signals (U1,..., Un) assigned to the first sequence (SP) of individual polarization states (P1,..., Pn) is determined, - The storage capacitor (C) according to the second sequence (SU) voltage signals (U1,..., Un) is acted upon by the voltage signals (U1,..., Un) and - As a result, the respective individual polarization states (P1,..., Pn) are impressed on the dielectric individual regions (F1,..., Fn). 19. Operating method according to claim 17, characterized in that for reading out an n-bit information (I) stored as total polarization (P) in the storage capacitor (C) in succession: - The storage capacitor (C) is subjected to a reading voltage pulse (U _L ) for a certain time (t), a measured reading current pulse (I _L ) and / or a resulting read charge quantity (Q _L ) are measured and made available as a measured value (M), - a bit combination (B) assigned to a measured value range (MB) of the measured value (M) or the measured value (M) is determined and - The determined bit combination (B) is provided and / or output as stored n-bit information (I) read from the storage capacitor (C). 20. Operating method according to one of claims 16 to 19, characterized, that the assignment between bit combinations (B1,..., Bm) and the first sequence (SP) polarization individual states (P1,..., Pn) and / or the assignment between measured value ranges (MB1,..., MBm) and bit combinations (B1,..., Bm) are specified, in particular in the form of at least one table, at least a list and / or the like, and each of these specifications be removed. 21. Operating method according to one of claims 16 to 20, characterized, that for writing a certain writing order (R) in Determined with respect to the individual dielectric regions (F1,..., Fn) and / or is observed. 22. Operating method according to claim 21, characterized, that the writing order (R) by the characteristic Properties of the dielectric individual regions (F1,..., Fn) is and / or is determined, in particular by mutual proportions of their values. 23. Operating method according to one of claims 21 or 22, characterized in - That, based on the given or determined writing sequence (R), dielectric individual areas (F2) with a higher coercive voltage (U2) are respectively described before dielectric individual areas (F1) with a lower coercive voltage (U1) and / or - That, based on the given or determined writing sequence (R), dielectric individual areas (F2) with a longer switching time (τ2) are described in front of dielectric individual areas (F1) with a shorter switching time (τ1).