DE10206554A1 - Teletext arrangement has programmable external program memory with write enable input coupled to processing unit so memory content can be changed depending on signal applied to input - Google Patents

Abstract

The teletext arrangement has a processing unit (10) and at least one external memory (20) connected to the processing unit for storing a program for implementation by the processing unit. The external memory has a write enable input (23) coupled to the processing unit so that the memory content of the external memory can be changed depending on the signal applied to this input.

Description

The present invention relates to a teletext arrangement with a processing unit and at least one to the Processing unit connected to the first external Memory that is designed to be a through the Processing unit to save executable program.

Such a teletext arrangement is described, for example, in "APPLICATION NOTE KITS / BOARDS, SDA 55xx TVText Pro Evaluation Board", Edition Oct. 9, 2001, Micronas GmbH, Freiburg. In the known arrangement according to FIG. 1-1 of the publication, the processing unit is an IC of the type "SDA 55xx TVText Pro" from Micronas GmbH, Freiburg, and the first external memory is in the form of flash memory or EPROM (Erasable Programmable Read Only Memory ) educated.

The first external memory contains one through the Processing unit executable program and can also contain data included after switching off the arrangement or at a Loss of voltage should not be lost. Such data concern, for example, data for an electronic Programming support (EPG = Electronic Program Guide). The program stored in the first external memory is on the desired functionality of the teletext arrangement matched, this functionality with the decoding of a teletext data transmitted on a television signal Preparation of video program system (VPS) data and others Control functions for a television set and the display of Information on a screen (OSD = On Screen Display) may include.

This program memory determining the functionality must by the manufacturer according to the wishes of the customers, usually the manufacturers of TV sets, are programmed in Contrary to one commonly used in such applications volatile data storage also used, which is also connected to the processing unit and which is used, for example, for the information from Save teletext pages.

The aim of the present invention is to provide a teletext Arrangement of the type mentioned in the introduction in which flexible programming of the Program memory is possible.

This goal is achieved by a device according to the features of claim 1 achieved. Advantageous configurations are Subject of the subclaims.

The teletext arrangement according to the invention has a Processing unit and at least one to the processing unit connected to the first external memory, to do so is designed to be executable by the processing unit Save program. The external memory has one write enable coupled to the processing unit Input on so depending on one at that input adjacent, provided by the processing unit Signal a memory content of the external memory changeable is.

The first memory is preferably from the manufacturer preprogrammed with a loader that works in one of several memory banks of the memory is stored, and that is suitable to other of the memory banks of the memory program when it runs in the processing unit becomes. The memory can, for example, after switching on be supplied with a signal that determines whether that Loader executed by the processing unit and the Memory should be programmed or whether one in the memory stored, which determines the function of the teletext arrangement Program to be executed by the processing unit.

The teletext arrangement according to the invention can be done by the customer (the TV manufacturer) or during one TV set services for the end customer (the TV set buyer) or programmed to the seller of the television become.

The data that is programmed into the first memory are through the loader through a serial Interface read in the processing unit. From there they will programmed into the first memory. The data with which the first memory is programmed, any data be, for example, an executable code, which are constants or which are the contents of a table represent. This data can also, for example, via the Teletext channel are transmitted.

In one embodiment of the invention it is provided that the teletext arrangement a second external memory has, which is connected to the processing unit and the one coupled to the processing unit Write enable input and one to the processing unit coupled reading enable input. The read release The input of the second external memory is in particular to a read enable output of the processing unit connected.

In addition, the first external memory has one Read enable output of the processing unit coupled Read enable input to depending on one at which Read enable input pending signal program code and / or data from the first memory into the processing unit read.

The first and second memories each have address inputs for addressing the memory areas and Data inputs / data outputs for reading in / reading out data, where this data in particular in the first memory Program data included.

In one embodiment of an arrangement with a first and second memory is a write enable output and a Selection signal output of the processing unit provided, which are connected to a multiplexer, the Multiplexer according to the selection signal on the Write enable output of the processing unit applied signal the write enable input of the first external memory or the write enable input of the second external Memory feeds to one of the two memories for writing unlock while the other is locked.

The second external memory is preferably volatile Memory, such as RAM, in particular an SRAM memory, and the first external memory is preferably a non-volatile memory, such as a flash memory or an EEPROM.

The processing unit also has an internal one Main memory in which the program sequences just required or data, especially those required for programming Program sequences or those in the first external memory if necessary, program data to be saved be cached.

The present invention is described below with reference to an in the attached figure embodiment explained. The figure contains the names of some signals, marked with an overline to indicate that the connections to which these signals are present are low active. These sweeps are as follows replaced by the character "/", which corresponds to the signal designation is prefixed.

The figure shows a teletext arrangement with a processing unit 10 , a first external memory 20 connected to the processing unit 10 , which is designed to store a program executable by the processing unit 10 , and a second external memory 30 connected to the processing unit 10 . The processing unit can be designed, for example, as a programmable microcontroller of the type SDA 5550 from Micronas GmbH, Freiburg, as shown in the example. In the example, the first external memory 20 is designed as a flash memory with a capacity of 1 M × 8 bits and an access time of less than 115 ns. The second external memory is designed as an SRAN memory with a capacity of 256 k × 8 bits and an access time of less than 230 ns.

The first external memory 20 is preferably designed to store data in a non-volatile manner in addition to a program that can be executed by the processing unit. Such data can include, for example, information that is necessary for the operation of the processing unit 10 in addition to the executable program. In addition to the EPG data mentioned at the outset, this can be any data that is transmitted via a data channel, in particular the teletext channel.

The first external memory 20 has a read enable input 26 which is connected to a read enable output 16 of the processing unit 10 in order to read the first external memory for reading out the stored program or, depending on a read enable signal / PSEN generated in the processing unit 10 output stored data. Both the read enable output 16 and the read enable input are low-active, that is to say the first external memory is enabled for reading when the signal / RD present at the read enable input 26 assumes a logic low level.

The addresses of the 8-bit wide memory areas in the example, which are to be read out, are fed to the first external memory via an 20-bit address signal at address inputs A0-A19 and are available at an output 11 of the processing unit. During a read operation, the data are read out via the data connection 25 and fed to a data connection 15 connected to the processing unit.

The first external memory also has a write enable input 23 coupled to the processing unit 10 , which is also low-active and which, when a write signal / WR with a logic low level is present, enables the first external memory for writing, the address information being transmitted via the memory areas to be written are contained in the address signal A0-A19 present at address input 27 . The data are fed to the first external memory via the data connection 25 , which in this case functions as a data input.

The provision of a write enable input on the first external memory enables the first external memory 20 serving as a program memory to still be programmable during operation or after delivery to the customer, a program stored in the external memory 20 also programming this Memory 20 controls, whereby of course only those memory areas of the first external memory 20 can be overwritten in which this load program is not stored.

The second external memory 30 likewise has a read enable input 32 , which is low-active and which is connected to a read enable output 12 of the processing unit 10 , this read enable output 12 also being low-active in the example. In addition, the second external memory 30 has a write enable input 33 , which is also low-active.

The second external memory 30 also has a data connection 35 with a width of 8 bits, which is coupled to the data connection 15 of the processing unit 10 .

In the exemplary embodiment, the write enable inputs 23 , 33 of the first and second external memories 20 , 30 are connected to a write enable output 13 of the processing unit 10 via a logic circuit designed as a multiplexer MUX, the multiplexer additionally being connected to a selection output 14 of the processing unit 10 applied selection signal SEL is supplied. In accordance with this selection signal, the multiplexer MUX supplies a write enable signal WR2 present at the write enable output 13 to either the write enable input 23 of the first external memory or the write enable input 33 of the second external memory 30 . The write enable output 13 of the processing unit 10 is also low-active in the example.

In the exemplary embodiment, the multiplexer MUX has an ODE gate 40 , a NAND gate 41 and an inverter 43 , the selection signal SEL being supplied to one of the inputs of the OR gate and the NAND gate. The write enable signal / WR3 is fed to a second input of the OR gate 40 and the inverted write enable signal / WR2 is fed to a second input of the NAND gate. The output of the OR gate 40 is connected to the write enable input 33 of the second external memory 30 and the output of the NAND gate is connected to the write enable input 23 of the first external memory 20 .

This internal structure of the multiplexer MUX ensures that a high level or a logic one is present at a LOw level or a logic zero of the selection signal SEL at the output of the NAND gate, by the first external memory 20 , whose Write enable input 23 is low-active to lock for writing. In the event of a low level or a logic zero of the selection signal SEL, the level of the write enable signal / WR2 is also present via the OR gate 40 at the write enable input 33 of the second external memory 30 , in order to have a logic zero at the Write enable output 13 of the processing unit 10 to enable the second external memory 30 , whose write enable input 33 is also low-active, for writing.

If the selection signal SEL assumes a logic high level, the output of the OR gate 41 is permanently at a high level and blocks the second external memory 30 for writing, while the level of the write enable signal / WR2 via the inverter 43 and NAND gate is applied to the write enable input 23 of the first external memory 20 .

This means that only one of the two external memories can be written at a time, while the reading processes of the two memories 20 , 30 can take place independently of one another, since the reading process of the first external memory 20 via the read enable output 16 of the processing unit 10 and the reading process of the second external memory 30 is controlled via the read enable output 12 of the processing unit 10 .

The teletext arrangement according to the invention can be implemented in a simple manner by means of conventional components, for example the SDA 5550 microcontroller and two memory modules, only one multiplexer MUX being present as an additional component, which is located between the write enable output 13 of the processing unit 10 and the write enable inputs 23 , 33 the external memory 20 , 30 is coupled. The write enable output 13 can be the standard write enable output previously used only to write to a volatile external memory, while the selection output 14 , to which the selection signal SEL is present, can be a freely programmable output of the processing unit 10 .

Finally, a special feature of the teletext arrangement shown in the figure should be pointed out. The processing unit 10 has an internal memory XRAM, shown in dashed lines, which is written simultaneously to the first external memory 20 and the second external memory 30 , namely when the write signal / WR2 at the output 13 of the processing unit 10 is one of the two external memories 20 , 30 releases for writing.

The internal memory XRAM has a number, for example Memory banks with 16 kB each, the address range of these memory banks of the internal memory XRAN the top one 16 kB of the memory banks of the first and second external Correspond to memory, these memory banks for example each comprise 64 kB.

Because of the simultaneous writing of the first external memory 20 and the internal memory XRAM, the first external memory in the example cannot therefore be written in an address area (the top 16 kB of a memory bank) which is also used by the internal memory. This memory area is then preferably used for permanently programmed data.

In order to be able to fully utilize the memory area of the second external memory 30 , provision is made to use one of the address bits, the address bit A15 in the example, as an enable signal at an enable input 31 for the second external memory 30 . The address bits A0 to A14 and A16 to A18 are then present at the address input 37 of this memory, the memory being only written to if the address bit A15 has a logic zero. The lowest 32 kB of a 64 kB memory bank of the second external memory are addressed by the address bits A0-A14. Address bit A16 is also used to address the top 32 kB, address bits A17-A19 are used to select the individual memory banks. Since the selection input 31 of the second external memory is low-active, the second external memory can only be released for writing if the address bit A15 is zero, i.e. if there is no address that addresses the internal memory XRAM, whose memory addresses are between C000h and FFFFh lie.

Table 1 summarizes the various memory accesses depending on the control signals present at the outputs of the processing unit 10 for a memory bank of 64 kB size in each of the individual memories, ie in the first external memory 20 , the second external memory 30 and the internal memory XRAN. As already explained, when the write enable signal / WR2 is active at the write enable output 13 of the processing unit 10 , either the first external memory 20 or the second external memory 30 is written, depending on the selection signal SEL. The entire area of a 64 kB memory bank in the first external memory 20 is addressed by means of the address bits A0 to A15, the higher order address bits are used to select the individual 64 kB memory banks.

In contrast, address bits A0 to A14 only address the lowest 32 kB (this corresponds to 7FFFh) of a memory bank of the second external memory, since address bit A15 is used to select the second external memory 30 and this memory is only written to if it is Address bit is zero. The upper 32 kB of this external memory is selected using the address bit A16.

Addressing the upper 16 kB of a 64 kB memory bank of the first external memory, ie the addresses C000h to FFFFh, also results in access to the internal memory XRAM, so that the first external memory 20 in the area of the upper 16 kB is not used can.

Simultaneous writing to the second external memory 30 and the internal memory XRAM is not possible since the upper 32 kB of the second external memory are selected by the address bit A16.

When reading out the second external memory 30 , in which the read signal / RD assumes a logic zero at the output 12 , both the second external memory 30 and the internal memory are released for reading, which, as explained, due to the use of the address bit A15 as chip release - Signal for the second external memory 30 does not overlap the address areas of the second external memory 30 and the internal memory XRAM.

The writing and reading out of the second external memory 30 and thus also the writing of the first external memory 20 takes place as a function of the controller command MOVX, a low level of the signal / WR2 identifying the writing by means of this command and a low level of the signal / RD indicates reading using this command.

The first external memory 30 is read out independently of the second external memory 30 and the internal memory XRAM when the read enable signal / PSEN at the output 60 assumes a logic low level. Correspondingly, instructions of a program stored in the first external memory 20 are executed, wherein the reading out of data and the execution of instructions do not differ with regard to the reading mechanism of the first external memory 20 . The low level of the / PSEN signal indicates reading using the MOVC controller command.

Claims (8)

1. Teletext arrangement with a processing unit ( 10 ) and at least one to the processing unit ( 10 ) connected to the first external memory ( 20 ), which is designed to store a program that can be executed by the processing unit ( 10 ), characterized in that the external memory ( 20 ) has a write enable input ( 23 ) coupled to the processing unit ( 10 ), so that a memory content of the external memory ( 20 ) can be changed depending on a signal present at this input. 2. Teletext arrangement according to claim 1, which has a second external memory ( 30 ) which is connected to the processing unit ( 10 ) and which has a write enable input ( 33 ) coupled to the processing unit ( 10 ) and one to the processing unit ( 10 ) coupled read enable input ( 32 ). 3. Teletext arrangement according to claim 2, wherein the read enable input ( 32 ) of the second external memory ( 30 ) is connected to a read enable output ( 12 ) of the processing unit ( 10 ). 4. Teletext arrangement according to claim 1 or 2, in which the first external memory ( 20 ) has a read enable input ( 26 ) coupled to a read enable output ( 16 ) of the processing unit ( 10 ). 5. Teletext arrangement according to one of claims 1 to 4, which have a multiplexer (MAX), to which a write enable signal from a write enable output ( 13 ) of the processing unit ( 10 ) is supplied and to which a selection signal from the processing unit ( 10 ) is supplied and which applies the write enable signal in accordance with the selection signal to the write enable input ( 23 , 33 ) of the first or second external memory ( 20 , 30 ). 6. Teletext arrangement according to one of claims 2 to 6, at the second external memory is a RAM memory, is in particular an SRAM memory. 7. Teletext arrangement according to one of the preceding claims, where the first external memory is flash memory. 8. Teletext arrangement according to one of the preceding claims, in which the processing unit has an internal memory having.