DE102021129663A1 - DEVICE FOR A RECEIVER USING MULTIPLE MODULATION SCHEMES AND RELATED METHODS - Google Patents

Abstract

An apparatus includes a radio frequency (RF) receiver for receiving RF signals. The RF receiver has multiple modulation signal detectors (MSDs) to generate multiple detection signals when multiple RF signals modulated using multiple modulation schemes are detected. The RF receiver further includes a controller operable to receive the plurality of RF signals in response to the plurality of detection signals.

Description

Cross reference to related applications

This application takes priority from the application filed December 30, 2020 U.S. 17/138,850 claim.

technical field

The disclosure generally relates to communication devices and associated methods. More specifically, the disclosure relates to radio frequency (RF) devices, such as RF receivers, that use multiple modulation schemes and associated methods.

General state of the art

As technology has advanced, an increasing number of circuit elements have been incorporated into devices such as integrated circuits (ICs). In addition, an increasing number of devices such as ICs or subsystems have been incorporated into products. Developments such as the Internet of Things (IoT) are expected to continue this trend.

The growing number of circuit elements, devices, subsystems, etc. has also resulted in a corresponding increase in the amount of power consumed by the products containing those components. In some applications, such as battery-powered mobile or portable products, a limited amount of power or energy is available. Given the relatively small amount of power or energy available in such applications, reduced power consumption of the components or products provides advantages or benefits, for example, an increase in battery life, an increase in "up time" or system active time, and the like .

Even in an unsustainable environment, increased power consumption will inevitably lead to greater amounts of heat being generated as electrical energy is not used 100% efficiently. Therefore, reduced power consumption of the components or products offers advantages or benefits such as reduced heat quantity, reduced electricity costs, and the like.

The description in this section and each (all) corresponding figure(s) are included as background information. The materials in this section should not be taken as an admission that these materials constitute prior art to the present patent application.

Summary of the Invention

According to example embodiments, a variety of devices and associated methods for RF devices are contemplated. According to an exemplary embodiment, an apparatus has an RF receiver for receiving RF signals. The RF receiver has multiple modulation signal detectors (MSDs) to generate multiple detection signals when multiple RF signals modulated using multiple modulation schemes are detected. The RF receiver further includes a controller to cause reception of the plurality of RF signals in response to the plurality of detection signals.

According to another exemplary embodiment, an apparatus for communication using RF signals includes a transmitter for transmitting a modulated RF signal. The transmitted information is modulated onto the modulated RF signal using one of several modulation schemes. The device further includes a receiver for receiving packets of received modulated RF signals. The receiver has multiple modulation scheme detectors (MSDs) to generate multiple detection signals. A packet is received by configuring the receiver based on a detection signal among the plurality of detection signals. The detection signal is obtained from the packet.

According to another exemplary embodiment, a method of operating an RF receiver includes generating using multiple modulation signal detectors (MSDs) to generate multiple detection signals when multiple RF signals modulated using multiple modulation schemes are detected. The method further includes causing receipt of the plurality of RF signals in response to the plurality of detection signals.

character list

• 1 zeigt eine Schaltungsanordnung für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 2 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 3 zeigt Darstellungen von Frequenzantworten in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 4 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 5 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 6 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 7 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 8 zeigt Darstellungen von Frequenzantworten in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 9 zeigt eine Schaltungsanordnung für das digitale Modem eines HF-Empfängers nach einer beispielhaften Ausführungsform.
• 10 zeigt das Abtasten in einem herkömmlichen Empfänger.
• 11 zeigt eine Schaltungsanordnung für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 12 zeigt das gleichzeitige Abtasten in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 13 zeigt die schlimmstmögliche Präambelankunft in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 14 zeigt ein Ablaufdiagramm für die gleichzeitige Detektion in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 15 zeigt die Kanalfilterbandbreitenwahl in einem HF-Empfänger nach einer beispielhaften Ausführungsform.
• 16 zeigt eine Schaltungsanordnung für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 17 zeigt eine Schaltungsanordnung für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 18 zeigt einen Netzwerkstapel mit einer gemeinsam verwendeten Medienzugriffssteuerung (medium access control, MAC) nach einer beispielhaften Ausführungsform.
• 19 zeigt eine Schaltungsanordnung für einen Netzwerkknoten nach einer beispielhaften Ausführungsform.
• 20 zeigt eine Steuerung für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 21 zeigt ein Steuerablaufdiagramm für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 22 zeigt ein Steuerzustandsdiagramm für einen HF-Empfänger nach einer beispielhaften Ausführungsform.
• 23 zeigt eine Steuerung für einen HF-Sender nach einer beispielhaften Ausführungsform.
• 24 zeigt ein Steuerablaufdiagramm für einen HF-Sender nach einer beispielhaften Ausführungsform.
• 25 zeigt ein Steuerzustandsdiagramm für einen HF-Sender nach einer beispielhaften Ausführungsform.
• 26 zeigt ein System für die Funkkommunikation nach einer beispielhaften Ausführungsform.
• 27 zeigt eine Schaltungsanordnung für eine IC, die einen HF-Empfänger aufweist, nach einer beispielhaften Ausführungsform.
• 28 zeigt eine Schaltungsanordnung für eine IC, die einen HF-Empfänger und einen HF-Sender aufweist, nach einer beispielhaften Ausführungsform.

The accompanying drawings illustrate exemplary embodiments only and therefore should not be taken as limiting the scope of the application or the claimed subject matter. Those of ordinary skill in the art will understand that the disclosed concepts are capable of other equally effective embodiments. In the drawings, the same numerical reference numbers used in more than one drawing indicate the same, similar, or equivalent function, component, or block.

• 1 shows a circuit arrangement for an HF receiver according to an exemplary embodiment.
• 2 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 3 12 shows plots of frequency responses in an RF receiver according to an exemplary embodiment.
• 4 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 5 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 6 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 7 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 8th 12 shows plots of frequency responses in an RF receiver according to an exemplary embodiment.
• 9 FIG. 12 shows a circuit arrangement for the digital modem of an RF receiver according to an exemplary embodiment.
• 10 shows sampling in a conventional receiver.
• 11 shows a circuit arrangement for an HF receiver according to an exemplary embodiment.
• 12 12 shows simultaneous sampling in an RF receiver according to an exemplary embodiment.
• 13 12 shows the worst case preamble arrival in an RF receiver according to an example embodiment.
• 14 12 shows a flowchart for simultaneous detection in an RF receiver according to an exemplary embodiment.
• 15 12 shows channel filter bandwidth selection in an RF receiver according to an exemplary embodiment.
• 16 shows a circuit arrangement for an HF receiver according to an exemplary embodiment.
• 17 shows a circuit arrangement for an HF receiver according to an exemplary embodiment.
• 18 10 shows a network stack with shared medium access control (MAC) according to an example embodiment.
• 19 shows a circuit arrangement for a network node according to an exemplary embodiment.
• 20 FIG. 1 shows a controller for an RF receiver according to an exemplary embodiment.
• 21 12 shows a control flow diagram for an RF receiver according to an exemplary embodiment.
• 22 12 shows a control state diagram for an RF receiver according to an exemplary embodiment.
• 23 FIG. 1 shows a controller for an RF transmitter according to an exemplary embodiment.
• 24 12 shows a control flow diagram for an RF transmitter according to an exemplary embodiment.
• 25 12 shows a control state diagram for an RF transmitter according to an exemplary embodiment.
• 26 12 shows a system for radio communication according to an exemplary embodiment.
• 27 FIG. 12 shows a circuit arrangement for an IC having an RF receiver according to an exemplary embodiment.
• 28 FIG. 12 shows a circuit arrangement for an IC having an RF receiver and an RF transmitter according to an exemplary embodiment.

Detailed description

The disclosure generally relates to communication devices and associated methods. More specifically, the disclosure relates to communication devices wherein RF receivers employ multiple modulation schemes, transmitters suitable for transmitting RF signals to such receivers, and associated methods.

One aspect of the disclosure relates to an RF device having receivers with simultaneous preamble detection (or simultaneous detection) and associated methods. Some applications, such as IoT applications, for short-range wireless communications define a receiver that can evaluate more than one frequency channel or more than one PHY layer or more than one PHY mode (e.g., Zigbee and Bluetooth). In the context of the description, a Fre quenzkanal be a channel or a frequency range with overlapping frequency or separate frequency. Examples include asynchronous frequency hopping, network detection (e.g., passive scanning in IEEE 802.15.4), automatic frequency control (AFC) in scanning, and received signal strength indication (RSSI) or energy detection scanning. For brevity, the description refers to one or more or multiple frequency channels (multi-channel), however, as those of ordinary skill in the art will understand, the disclosed techniques and apparatus are also applicable to multiple PHYs or PHY modes.

The transmissions in applications such as the IoT applications mentioned above can take place on more than one carrier frequency. In addition, more than one modulation scheme or more than one PHY or more than one PHY mode can be used. In such applications, a system on chip (SOC) that includes the radio (RX, TX, or both) typically includes a packet handler and a protocol timer (either in hardware, software, firmware, or a combination thereof implemented) on. Under these circumstances, RF receivers according to various embodiments avoid duplicating various parts or blocks of the RF receiver, such as the packet handler and the protocol timer.

When receiving multiple signals with different corresponding RF frequencies, RF receivers according to various embodiments avoid duplication of some digital processing functions. Digital processing typically entails processing from some layers of the protocol stack (including the PHY, the Media Access Control (MAC), the network layer). Typically, digital processing uses a variety of resources such as hardware, memory, and software. The RF receivers avoid duplicating some digital processing functions by searching for properties associated with the multiple signals through multiple signal detectors and selecting a subset of the multiple signals for digital processing or for simultaneous digital processing. The properties can be contained in the preamble, or the sync word, or the PHY header, or the MAC header, or a combination thereof. In some embodiments, the election is based on the first successful detection among the multiple signal detectors (first come, first serve) and subsequent detections are ignored if a subset of the multiple signals undergoes digital processing.

The signal detectors can include a variety of circuit types and detection techniques as described below. The signal detectors provide signal quality metrics (metrics that indicate the likelihood that the received signal is a desired signal, e.g. a Frequency deviation within the limits of a predetermined maximum and minimum deviation threshold and/or a correlation with a desired symbol sequence (preamble or sync word) and/or a frequency error that is less than a predetermined frequency offset threshold and/or a signal-to-noise ratio (signal to noise ratio, SNR) greater than a predetermined SNR threshold). In exemplary embodiments, the signal detectors can be any of preamble detectors, sync word detectors, RSSI detectors (ie, to provide RSSI metrics for a received or provided signal), signal arrival detectors (such as described in US patent application filed November 14, 2013). patent application no. 14/080,405 , now U.S. Patent No. 10,061,740 , described), cost function detectors (such as described in U.S. Patent Application No. 16/177,373 described), correlators (such as in that filed on December 6, 2016 U.S. Patent Application No. 15/370,693 , meanwhile the U.S. Patent No. 10,389,482 , described), magnitude detectors, phase detectors, phase discriminators, differentiated phase detectors, phase click detectors, deviation detectors, and any combination of the above. In general, any circuit or block that detects the presence of a desired or transmitted signal, such as an RF signal, in a frequency channel can be used. Additionally, note that in exemplary embodiments, a scan across frequencies for unwanted signals may be performed, eg, an RSSI scan may be performed to determine a "clean" channel. Once a "clean channel" is found, that channel can then be used for transmission.

Some traditional approaches have been used in applications such as IoT applications. One approach is to evaluate one frequency at a time. This technique can be a relatively slow process as the recipient may be able to repeat this assessment many times. In addition, this solution involves hopping of the frequency synthesizer from one frequency to the next, which is necessary for the completion of the Adds a settling time to the rating. A longer evaluation time leads to more energy consumption. A second approach is to implement multiple intermediate frequency (IF) paths, with each IF followed by a corresponding demodulator. This approach has a relatively high power consumption for all the demodulators. Also, multiple demodulators are expensive in terms of die area, circuit complexity, and so on. Additionally, demodulating multiple parallel channels entails running multiple frame controllers in parallel, increasing power consumption and cost, making this approach generally impractical for low-performance, low-cost IoT applications.

RF receivers according to various embodiments address the above issues. There are additional use cases as well. As an example, Z-Wave defines a separate frequency on which the radio can receive frames while also scanning the other Z-Wave channels. An apparatus supporting simultaneous signal detection, according to various embodiments, would allow a frame to be received without the additional delay and power consumption associated with receivers evaluating one frequency at a time. In turn, this attribute allows the sending device to use very short preambles and payloads, thereby reducing the energy per transmit (TX) frame. This scheme would allow the use of energy harvesting sources that power the transmitters.

Another example is as for example in https://www. silabs. com/community/wireless/proprietary/knowledgebase.entry.html/2019/06/20/channel scanning-8x31. This scheme specifies that a node should be able to scan some channels for a signal with a limited preamble length. This determination leaves relatively few preamble signals per channel for detection of a preamble, which limits the time to reliably detect the signal. By receiving multiple channels simultaneously, RF receivers according to various embodiments allow more time per channel to be available. This time can be used to improve signal quality detection performance (e.g. fewer false positive detections) or to save power, for example by switching to power saving mode or going to sleep mode in the preamble detection mode. Another example is Bluetooth Low Energy (BLE). For example, BLE determines relatively rapid channel scanning while searching for advertising packets. RF receivers according to various embodiments can accommodate BLE's rapid channel scan.

In exemplary embodiments, the RF receiver is capable of simultaneously detecting signals on multiple frequency channels without the overhead of multiple parallel demodulators. The RF receiver does this using relatively simple, low power signal detectors (one per IF path) and at least one demodulator. For most IoT use cases, a demodulator would suffice. The signal detectors can have much less complexity and much lower performance compared to the traditional multiple demodulator solution, thereby saving power and reducing complexity and/or cost. In exemplary embodiments, a multi-frequency channel RF receiver is used to receive at least one received signal on multiple of the frequency channels. It does this by using front-end circuitry in the RF receive circuitry to apply frequency shifts to the frequency channels to produce multiple filtered baseband signals. Signal detectors are used to measure the signal quality of each filtered baseband simultaneously. A controller selects (at least) one of the filtered base signals for demodulation by (at least) one demodulator.

The RF receiver according to various embodiments utilizes the low duty cycle activity found in some applications such as in IoT networks. For example, a door sensor, light switch, motion sensor, or glass breakage detector may trigger less than about ten times a day. In other words, the RF receiver has a low duty cycle of operation (being at least partially in sleep mode most of the time). In these low duty cycle applications, it is more efficient to operate multiple signal detectors than to operate multiple demodulators. In most cases, one demodulator can suffice, reducing costs. For example, die area on a chip or IC could be reduced or saved. None of the signal detectors may detect a valid signal in any of the filtered baseband signals. In this case, the demodulator(s) can remain in a non-active, low-power state. If at some point later a signal detector trips, the controller can then “wake up” a demodulator and provide the demodulator with the associated filtered baseband signal for demodulation. If for example a signal detector 1 triggers, a controller can then provide a filtered baseband signal 1 (provided by the IF circuit 1) to the demodulator for demodulation.

According to various embodiments, if multiple PHYs or multiple PHY modes are used on multiple frequency channels, the RF receiver may use multiple signal detectors (one for each expected PHY or each expected PHY mode) on each filtered baseband signal. If one of the signal detectors triggers, the controller can then select a demodulator suitable for demodulating the detected PHY (or PHY mode detected) and provide that demodulator with the associated filtered baseband signal. In other embodiments, instead of choosing a demodulator, a configurable demodulator can be configured to demodulate the detected PHY or PHY mode. If a particular frequency channel is assigned to a single PHY or PHY mode (e.g. known in advance, per startup), then a single signal detector can be used on the associated filtered baseband signal. In other example embodiments, when multiple signal detectors fire, the controller may use the soft detection outputs of the signal detectors to choose a filtered baseband signal based on maximum likelihood or maximum correlation. In other exemplary embodiments, the RF receiver uses an analog down-converter (e.g., a low noise amplifier (LNA), an in-phase & quadrature (IQ) mixer, a programmable gain amplifier (PGA )) to apply a frequency shift to the multiple frequency channels to produce a combined analog IF signal.

An IF analog-to-digital converter (IF ADC) converts the combined analog IF signal to produce a combined digital IF signal. Multiple digital downconverters apply a set of frequency shifts to the combined digital IF signal to produce multiple baseband signals. Multiple channel filters can filter the multiple baseband signals to generate multiple filtered baseband signals. Note that a single ADC and front-end circuitry (F-mixer, etc.) are used in conjunction with multiple IF path circuits or branches, resulting in less complexity, lower cost, and lower power or power consumption.

To allow for increased flexibility, a true IF ADC (as opposed to complex) is used in some embodiments. The true IF ADC will pass both positive and negative frequencies, allowing separate frequency channels above and below the local oscillator (LO) frequency to be received. The final frequency position of each individual frequency channel is established by its associated complex mixer and complex IF filter stage. In such cases, the IF ADC bandwidth should be as follows in conjunction with 3 described to accommodate the highest (|ZFx| + 0.5 BWx) of the various ZF paths, where |ZFx| equals the absolute value of the RF receive frequency minus the LO frequency, and BWx is the appropriate or required bandwidth for receiving a desired or transmitted signal (see 3 ). In various embodiments, the RF receiver uses multiple digital mixer stages, each digital mixer being driven by a combined digital IF signal and a numerically controlled oscillator (NCO), each with its own NCO frequency. The NCO frequency is equal to the IF frequency for that IF path or stage (IFx). Each digital mixer is followed by a filter stage. As will be understood by those of ordinary skill in the art, the filter stage may include a decimator, a finite impulse response (FIR) filter, an infinite impulse response (IIR) filter, a direct current (DC) filter have etc.

In various embodiments, circuitry or hardware of the RF receiver could be saved or reduced by sharing functions. For example, a second channel filter can share a multiplier with the first channel filter. As another example, the Look Up Table (LUT) for sine/cosine generation in NCOs can be shared between the NCOs of the digital mixers. As described below, RF receivers according to various embodiments include image reject calibration (IR-cal) circuitry. The IR-cal stage can be shared or separate IR-cal circuits can be used. Separate IR-cal stages or circuits can provide better image rejection due to the frequency dependence in the IQ errors caused by mismatches in a practical implementation of various circuits or blocks such as mixers, PGAs, etc. and/or self-mixing in the mixer circuits. as will be understood by those of ordinary skill in the art. Conversely, sharing the IR-cal circuits as discussed above allows for an on saving hardware, cost, etc. In exemplary embodiments, the signal detectors used in the RF receiver are relatively simple signal detectors. As will be understood by those of ordinary skill in the art, examples include correlators, cost function detectors, digital signal arrival detectors (DSA detectors), RSSI detectors, magnitude detectors, phase detectors, phase discriminators, differentiated phase detectors, etc.

1 shows a circuit arrangement for an HF receiver 5 according to an exemplary embodiment. The RF receiver 5 is coupled to an antenna 10 through which it receives RF signals. The received RF signals are input to LNA 15, which amplifies the received RF signals and provides the amplified RF signals to mixer 20 (labeled "HFMIX"). The mixer 20 mixes the amplified RF signals with an LO signal provided by the LO 25 to produce a mixed or down-converted signal. The mixed signal is provided to the PGA 30. The PGA 30 amplifies the mixed signal using a programmable gain to produce an amplified mixed signal.

The ADC 35 receives the amplified mixed signal, an analog signal, and converts it to a digital mixed signal. The ADC 35 provides the digital composite signal to the digital modem 40, which can filter, decode, demodulate, etc. the digital composite signal to extract data and provide the data at its output. Note that the digital modem 40 can perform various functions such as channel filtering, signal detection, and modulation, as described below. Additionally, it should be noted that while some embodiments may omit the transmit (modulation) functionality, the term "digital modem" is used for brevity. In exemplary embodiments, the front-end circuitry (e.g., the LNA 15, the mixer 20, the LO 25, the PGA 30, and the ADC 35 mentioned above) is used by the various IF branches or circuits in the digital modem 40. The following "Description describes various digital modems 40 according to example embodiments. It should be noted that while the figures and accompanying description show two IF paths or circuits for brevity and clarity of presentation, in various embodiments more than two. *** " IF paths or circuits can be used, as will be understood by those of ordinary skill in the art.

2 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The output signal of the ADW 35 (see 1 ) is provided to the decimator 55 (labeled "DEC0"), which decimates the signal and provides a decimated signal at its output. The output of the decimator 55 is fed to the input of a DC compensation circuit 60 (labeled "DC-comp"), which eliminates or attenuates or compensates for any DC component present in the decimated signal. The output of the DC compensation circuit 60 drives two IF path circuits as described below. In the first IF path circuit, the output of the DC compensation circuit 60 drives the input of the IR calibration circuit 65 (labeled "IR-cal_a"), which performs an IR calibration, as will be understood by those of ordinary skill in the art. The output of the IR calibration circuit 65 drives the input of a digital mixer 75 which mixes the signal with the output of the NCO 70 (labeled "NCO a") to produce a mixed digital signal at the digital mixer 75 output. The decimator 80 (labeled "DEC1a") receives and decimates the digital mixed signal and provides the resulting decimated signal to the channel filter 85 (labeled "CHFa"). Channel filter 85 filters the decimated signal (e.g., performs low-pass filtering) and provides the resulting filtered signal to DSA 90.

The DSA 90 acts as a signal detector. Therefore, the DSA 90 detects (or looks for or waits for) the arrival of a desired or particular signal. If detected, the DSA 90 provides a signal to the controller 105 to indicate signal arrival. In response, the controller 105 provides a select signal to the multiplexer (MUX) 95 to cause the MUX 95 to provide the output of the channel filter 85 to the digital signal processor (DSP) 100 or, generally, to one or more demodulators. Thus, in various embodiments, reference to the DSP 100 includes the use of one or more demodulators. The controller 105 also programs, configures or sets up the DSP 100 for the type of signal detected, the PHY, the PHY mode, etc. In response, the DSP 100 extracts the data from the packet in the channel filter 85 output that triggered the DSA 90 and provides the data on an output.

The second IF path circuit is similar to the first IF path circuit and operates in a similar manner. Various blocks in the second IF path circuit use a suffix “b” (e.g. “IR-cal_b” instead of "IR-cal_a" for the first IF path circuit). Thus, the second IF path circuit has the IR calibration circuit 135 (labeled "IR-cal_b"), the NCO 130 (labeled "NCO b"), the decimator 120 (labeled "DEC1b"), the channel filter 115 (labeled "CHFb") and the DSA 110 (labeled "DSAb") When the DSA 110 through the second IF path circuitry, ie, in the output of the channel filter 115, detects the arrival of a desired or designated signal , it provides an indication of signal arrival to the controller 105. In response, the controller 105 provides a select signal to the MUX 95 to cause the MUX 95 to provide the output of the channel filter 110 to the DSP 100.

The controller 105 also programs, configures or sets up the DSP 100 for the type of signal detected, the PHY, the PHY mode, etc. In response, the DSP 100 extracts the data from the packet in the channel filter 115 output that triggered the DSA 110 and provides the data on an output. This enables the RF receiver to simultaneously detect multiple PHYs or PHY modes or signals on multiple frequency channels. It should be noted that the NCOs of the first and second IF path circuits have output frequencies corresponding to the two frequency channels on which the respective IF path circuits operate. In exemplary embodiments, controller 105 may set, program, or configure the output frequencies of NCO 70 and NCO 130. It should also be noted that, as described above, in some embodiments more than two IF path circuits may be used depending on the number of frequency channels that it is desired to sample simultaneously. It should also be noted that in some embodiments, DSA 90 and DSA 110 can be programmed to receive the same PHY or PHY mode but at different frequencies, as desired.

3 12 shows plots of frequency responses in an RF receiver according to an exemplary embodiment. More specifically, the plot shows the frequency response 150 of decimator 55, frequency channel 155 (formed by the frequency responses of digital mixer 75, decimator 80 and channel filter 85) (labeled "BWa"). Frequency channel 155 is centered at frequency (F _LO - F _NCOa ), where F _LO and F _{NCOa denote} the output frequencies of LO 25 and NCO 70, respectively. Likewise shows 3 channel 160 (formed by the frequency responses of digital mixer 125, decimator 120 and channel filter 115) (labeled "BWb"). Frequency channel 160 is centered at frequency (F _LO + F _NCOb ), where F _LO and F _{NCOb denote} the output frequencies of LO 25 and NCO 130, respectively. Note that the plot also shows the IF frequencies of the two IF path circuits. These are labeled ZF _a and ZF _b , respectively.

4 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The circuit arrangement in 4 is the circuit arrangement in 2 similar, except that the output of channel filter 85 drives the inputs of random access memory 180 (labeled "RAMa") and correlator 185 (labeled "KOR a"), and the output of channel filter 115 drives the inputs of random access memory 195 (labeled "RAMb") labeled) and correlator 190 (labeled "KOR b"). RAM1 and RAM2 denote memory that the DSP 100 can use, for example, as scratch pad memory, etc., to perform its functions (eg, demodulation).

The samples (IQ or phase or magnitude or some combination) are stored in circular buffers formed by RAM 180 and RAM 195. In this circuit of the RF receiver, the correlator 190 can detect a correlation peak while processing a synch word (a synchronization word) for sync word a. Then, using RAM 195, the DSP 100 can “rewind” to the sync word and apply forward error correction decoding (FEC decoding) followed by sync word demodulation (e.g., as in a BLE encoded PHY or a PHY mode). It should be noted that a combination of the in 2 and 4 Circuit arrangements shown can be used. Therefore, in some embodiments, one or more of the IF paths uses DSA(s), while one or more of the IF paths uses the combination of RAM(s) and correlator(s). Additionally, in some embodiments, instead of using RAM 180 and RAM 195, a single dual port RAM may be used, in which case one port receives the output of channel filter 85 and another port receives the output of channel filter 115.

5 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The circuit arrangement in 5 is the circuit arrangement in 4 similarly, except that the output of channel filter 85 does not drive RAM 180 and correlator 185, but instead drives the input of IF processor circuitry 205 (labeled "IF Processor_a"). The output of the IF processor 205 drives the inputs of the RAM 180 and Corre lators 185. Likewise, the output of channel filter 115 does not drive RAM 195 and correlator 190, but instead drives the input of IF processor circuitry 210 (labeled "IF Processor_b"). The output of IF processor 210 drives the inputs of RAM 195 and correlator 190.

In exemplary embodiments, IF processors 205 and 210 may each be a coordinate rotary digital computer (CORDIC) or any other cartesian-to-polar conversion circuit. Each of the IF processors 205 and 210 can also be constructed using a CORDIC followed by a phase differentiator, where the differentiation can be oversampled (multiple differentiations per symbol) or one differentiation per symbol can be used. It is also possible that IF processors 205 and 210 may provide magnitude or logarithmic magnitude for amplitude shift keying (ASK) or on-off keying (OOK) applications. In addition, the IF processors 205 and 210 could be augmented with a slicer to separate the raw magnitude, phase, or differentiated phase into 1 or 0 values. In addition, a combination of the in 2 and 4 detector circuitry shown can be used. Thus, in some embodiments, one or more of the IF paths may use an IF processor, while one or more of the IF paths may use any of the signal detectors (eg, a DSA) described above.

6 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The circuit arrangement in 6 is the circuit arrangement in 2 similar except that the output of channel filter 85 drives the input of RSSI circuit 220 (labeled "RSSI a") and the output of channel filter 115 drives the input of RSSI circuit 225 (labeled "RSSI b"). The RSSI circuit in each of the IF path circuits extracts the signal level (RSSI, magnitude, energy detect (ED) or RMS level) from the respective channel filter output. The signal level can be evaluated on multiple frequency channels simultaneously by using the multiple IF path circuits, thereby speeding up RSSI sampling. The signal levels are sent to the controller 105 for processing. Controller 105 then controls MUX 95 as described above in connection with 2 was described. In some embodiments, the controller 105 may include memory in which to store the signal levels. Applications of the embodiment in 6 include signal level scanning for signal agility (connection), listen before talk and fast frequency analyzer.

7 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The circuit arrangement in 7 is the in 2 embodiment shown is similar, except that the controller 105 in the embodiment of FIG 7 drives an HF synthesizer. The RF synthesizer changes the output frequency when the number of frequencies to be sampled or desired to be sampled is greater than the number of IF path circuits in the RF receiver. For example, if the RF receiver has two IF path circuits and it is desired to perform RSSI evaluation on twenty channels, the RF synthesizer should be tuned to ten frequencies. As an example shows 8th that six channels are evaluated using three RF synthesizer (LO) frequencies. It should be noted that the recipient in 7 any other detection architecture such as those described above (e.g., DSA, IF processor, etc.) may also be used. In embodiments where two DSAs or correlators are used and neither detects a signal for a particular time window, the controller will cause the LO frequency to change to a next frequency value for re-evaluation. Alternatively, the controller can change the frequencies of the NCOs. In such embodiments, the sampling may be temporarily stopped as soon as one of the DSAs or the correlators triggers, ie detects a signal.

The DSA or correlator that fires first causes the controller 105 to select the MUX 95 to pass the associated channel filter output to the DSP 100 and configures the DSP 100 depending on the detected signal, detected PHY, or detected PHY mode as described above. The DSP 100 extracts the data from the packet on which the DSA triggered. If both DSAs or correlators fire at the same time, the highest correlation result could be used to choose the channel from which the DSP 100 extracts the data. Alternatively, a priority scheme could be used so that whenever both correlators or DSAs fire at the same time, a particular PHY gains priority to be demodulated first. In addition, the DSA or a TRECS (Timing RECovery System) could also extract the residual frequency offset to improve alignment by regulating the LO or the NCO frequency. Once the modulation is aligned in one of the channel filters, the bandwidth of that channel filter can be reduced to increase sensitivity, reduce noise and improve channel selectivity. As will be understood by those of ordinary skill in the art, adding more IF path circuits (simultaneous receive channels) speeds up sampling AFC systems.

8th 12 shows plots of frequency responses in an RF receiver according to an example embodiment using two IF path circuits. If no valid signal is received, the LO can sample from F _LO2 to F _LO3 to F _LO1 to F _LO2 and so on. If a valid signal is received on channel F _LO2 + _FNCO2 , the LO scan will stop at F _LO3 and the DSP 100 will begin demodulating the signal in the second IF path circuit. As mentioned above, the sample time can be further reduced by using more IF path circuitry.

9 FIG. 4 shows a circuit arrangement for the digital modem 40 of an RF receiver according to an exemplary embodiment. The circuit arrangement in 9 is the circuit arrangement in 5 similar in that IF processors 205 and 210 are used as described above. In contrast to the embodiment in 5 drives in the embodiment in 9 the output of the channel filter 85 the inputs of the RAM 270 (labeled "RAM a") and the TRECS 265 (labeled "TRECS a"). Likewise, the output of channel filter 115 drives the inputs of RAM 275 (labeled "RAM b") and TRECS 280 (labeled "TRECS b"). Each of the TRECS 265 and 280 finds the timing (on the preamble, the sync word, or a combination of the two). When the timing is found in an IF path circuit, the corresponding TRECS also has an estimate of the frequency offset. This frequency offset estimate can be provided to the appropriate NCO in the IF path circuit to center the modulated spectrum in the channel filter bandwidth. The output of the TRECS 265 forms an AFC loop in the first IF path circuit by providing a frequency offset signal to the NCO 70 . Likewise, by providing a frequency offset signal to the NCO 130, the output of the TRECS 280 forms an AFC loop in the second IF path circuit. The frequency offset signals are used to clip or adjust or program or tune or configure the respective frequencies of the NCO 70 and NCO 130 to center the modulated signal in the channel filter bandwidth as described above.

Another aspect of the disclosure relates to simultaneous signal detection in RF receivers by using multiple signal detectors. Generally speaking, RF receivers according to various embodiments provide simultaneous detection of patterns (or detection of patterns in signals). The patterns may contain a preamble, a synchronization (synch) word, or both. Therefore, in various embodiments, the simultaneous pattern detection constitutes a simultaneous preamble detection, a simultaneous synch word detection, and/or a simultaneous preamble and synch word detection. Without limiting the general character, the following description may concern preamble detection, synch word detection or both. In other words, as mentioned, the patterns generally contain preamble(s), synch word(s), and/or both. Therefore, references in the specification to preamble detection or detector may be generalized or applied to patterns or pattern detection in general, as will be understood by those of ordinary skill in the art. Likewise, references in the specification to synch word detection or synch word may be generalized or applied to patterns or pattern detection in general, as will be understood by those of ordinary skill in the art.

10 shows sampling in a conventional receiver. The sampling conforms to the Z-Wave standard, which may have three PHY types, R1, R2, and R3 (eg, in Federal Communications Commission (FCC) territories). R1 and R2 transmit at around 908.4MHz while R3 transmits at a different frequency, 916MHz. The Z-Wave specification (currently available at https://www.itu.int/rec/T-REC-G.9959-201501-1) defines three PHYs, R1, R2 and R3, in clause 7.1.2.2. With channel configuration 2, all three PHYs can be used. The preamble for these PHYs is specified in paragraph 7.1.3.2, which states that “the preamble length shall conform to Table 7-10. The values allow a receiver to scan all channels and obtain synchronization on any channel for the duration of the preamble”. The specifications imply sequential sampling of all three PHYs when using channel configuration 2. The challenge for the receiver is to find the preamble for all three PHY possibilities within the available preamble length.

The receiver may not have any prior knowledge of what type of PHY is being sent (what type of PHY the sent signal corresponds to). As a result, the receiver must sample the three PHY types during a single preamble transmission in order to perform preamble detection. The preamble lengths are just long enough to accommodate this scheme support while maintaining acceptable battery life. In 10 the receiver performs a sequential cyclic scan loop as shown. The preamble detection window with respect to symbols is approximately such that balanced performance is obtained. As will be appreciated by those of ordinary skill in the art, a longer detection window will reduce false detections and increase detection sensitivity 10 In the receiver sampling timing diagram shown, the sampling periods are proportional to the data rate (R1 = 9.6 kbps, R2 = 40 kbps and R3 = 100 kbps) and are sequential as mentioned above.

With Z-Wave, the specifications require preamble detection during the duration of the transmitted preamble. Accordingly, the preamble is longer than a certain length to support the specification. A sample period typically constitutes the period that the receiver is on (energized) to detect for a specified period of time. Typically, the sample period is the sum of the automatic gain control (AGC) settling time, the group delay from the antenna to the preamble detector, the receiver settling time (e.g., the AFC loop settling time), the asynchronous delay (the phase of the incoming preamble could be reversed to the correlator in the preamble detector) and the detection window (the evaluation time for the signal detector or the preamble detector to detect the PHY sequence). As will be understood by those of ordinary skill in the art, a relatively long detection window is desirable, but the sample periods (AZ) are limited by the preamble length. As mentioned, Z-Wave receivers operating according to the Z-Wave specification sample (sample for received signals corresponding to the multiple PHYs) multiple PHYs, e.g., R1, R2, and R3. In terms of time, the PHY R2 has the shortest preamble. As mentioned above, conventional solutions configure the receiver to scan for preambles sequentially. The preambles of all PHYs are quite long, so the sequentially scanning receiver should never miss a packet. But Z-Wave ensures the incorporation of an additional PHY for long-distance communication. Scanning for four PHYs could become problematic since the preamble lengths of the legacy PHYs cannot be changed. Sequential sampling would mean speeding up the sampling periods, which means that the length of the preamble correlator would have to be reduced. However, this causes an increased packet error rate floor, loss of sensitivity, and reduced robustness to interference.

RF receivers according to various embodiments support simultaneous signal detection, i.e., simultaneous preamble detection, by using multiple signal detectors (e.g., preamble detectors). A typical application for such receivers would be in a communication system using multiple PHYs, where the receiver has no prior knowledge (prior knowledge) of which PHY is being transmitted. As mentioned above, Z-Wave governs this scheme. In RF receivers according to various embodiments, to increase the communication range, an additional PHY is present to support long-distance applications (e.g., in areas or countries that comply with FCC regulations). Scanning for four possible PGHYs (signals sent through the corresponding PHYs) is even more difficult than scanning for three PHYs. RF receivers according to various embodiments take advantage of the fact that PHYs R1 and R2 share the same channel to sample PHYs R1 and R2 simultaneously (sampling the received RF signals corresponding to the two respective PHYs). RF receivers according to various embodiments exhibit increased reception sensitivity, a lowered packet error rate floor, and increased robustness to interference.

Although the following discussion refers to the use of receivers according to various embodiments in systems using Z-Wave, use of receivers according to various embodiments is contemplated and possible by making appropriate modifications in systems with specifications other than Z-Wave , as those of ordinary skill in the art will understand. Therefore, references to Z-Wave, the related description, and receiver architectures and circuitry are exemplary only and not limiting. In various embodiments, a concurrently sampled RF receiver architecture or a partially concurrently and partially sequentially sampled RF receiver architecture is used. In order to reduce the power consumption and cost of the receiver, the channel filter and all the circuits before the channel filter (that is, between the antenna interface and the channel filter, such as the LNA, the RF mixer, the frequency synthesizer, the PGA, the ADC, the ADC loop, decimators and the digital mixer) together the front-end circuitry (or front-end circuitry) is shared as will be described below. It should be noted that the embodiments described and shown in the figures are only illustrative and exemplary, as will be understood by those of ordinary skill in the art. Like average subject as people will understand, other embodiments are contemplated and possible. For example, in some embodiments, the channel filter, digital mixer, and/or decimators may not be shared, if desired.

In some embodiments, a single channel filter is used for all PHYs using simultaneous preamble search during simultaneous preamble search. In such embodiments, the channel filter bandwidth is configured (or set up or programmed to the bandwidth specifications of the PHY with the highest specified bandwidth) so that the channel filter can pass the signals for all PHYS for a simultaneous preamble search. In some embodiments, the above scheme is extended and multiple preamble detectors are used to support simultaneous preamble search. Each preamble detector is configured for one of the PHYs used in simultaneous preamble search so that preamble detection can be associated with the received PHY (i.e., the PHY to which a received RF signal corresponds). This scheme allows PHY specific optimization in the receiver.

Examples of receiver optimization are (a) the AFC settings, (2) the channel filter bandwidth, (3) the sample rate converter ratio, (4) the demodulator configuration, (5), the decoder settings (e.g. Manchester/Non-Return-to-Zero (NRZ ), de-interleaving, data de-whitening and FEC engine), (6) an additional preamble detection and (7) the configuration of the sync word detection. Each of the optimizations is described below, and one or more optimizations may be used with the example receiver architectures shown in the figures and described in detail below.

(1) The AFC settings: In order to minimize the delay, the frequency error is measured during the preamble search so that the frequency error is immediately available when the preamble is detected. When one of the preamble detectors finds a preamble, a frequency correction is applied to align the incoming signal close to the channel center frequency. Alignment can be accomplished by changing either the RF local oscillator or the oscillator driving the digital mixer. The AFC can use a parameter (AFC Limit) to limit the maximum amount of frequency offset compensation to prevent over-tuning caused by inaccurate measurements. Since different PHYs may have different AFC limits, performance can be optimized by adjusting the AFC limit based on the PHY found by the preamble detector (where the PHY corresponds to the received RF signal for which a preamble was detected).

(2) The channel filter bandwidth: Since different PHYs may have different modulation bandwidth and frequency offset range, performance can be optimized by adjusting the channel filter bandwidth depending on the PHY found by the preamble detector. Narrower bandwidths can be chosen depending on the PHY found by the preamble detector after the AFC has settled, which will increase receive sensitivity and selectivity. The channel filter bandwidth is usually determined by the filter sampling rate and the channel filter coefficients. In some embodiments, the filter coefficients are changed such that the sample rate used by subsequent or subsequent circuits remains unchanged.

(3) The sample rate migration ratio: Some PHYs may use sample rate adaptation for further detection after the preamble of such PHYs has been detected (where the PHY corresponds to the received RF signal for which a preamble was detected). Further detection may involve detection of the preamble, sync word, payload data, and so on. (4) The demodulator configuration: The preamble detectors can be separate blocks as desired without using any demodulator circuitry. In such embodiments, a demodulator would be activated or configured depending on the PHY found by the corresponding preamble detector.

(5) The decoder settings: To keep costs down or reduce costs (minimum or reduced die area), a single decoder can be used. To support such a configuration, the decoder can be tuned based on the PHY found by the preamble detector. For example, the decoding may involve Manchester/non-return-to-zero (NRZ) decoding, de-interleaving, data deskewing, forward error correction, block decoding, and so on. (6) The additional preamble detection: After an initial detection of the preamble as part of the simultaneous PHY detection, an additional detection can be employed to increase the overall reliability of the preamble detection. For example, a preamble detector can be configured depending on the PHY found by the initial preamble detector. (7) The configuration of the sync word detection: When two or more PHYs share the sync word detection circuitry, this circuitry can be configured depending on the PHY found by the preamble detector.

As noted, in various embodiments, the above optimizations can be used individually, i.e. each optimization by itself, or multiple optimizations can be used together. Additionally, or instead, in some embodiments, multi-channel reception may be supported or used, specifically by any combination of preamble detection with the multi-channel reception techniques described above (described in more detail in above-referenced US priority patent application Serial No. 16/668,834). More specifically, each IF path may have at least one detector to detect a preamble or a synchronization word (or synch word). If a preamble or sync word is detected then optimizations could be performed in the same way as described above. For example, the oscillator driving the digital mixer could be tuned on the IF path corresponding to detection to compensate for frequency offset, and the channel filter bandwidth could be narrowed to improve sensitivity and selectivity performance. In addition, the other IF path(s) could be shut down (or disabled or turned off) to reduce power consumption. All other optimizations described in this document can also be applied as desired in a multi-channel configuration.

The following description provides RF receiver architectures, flow charts, and associated illustrations corresponding to simultaneous detection according to various embodiments. The RF receivers can use any of the optimizations described above. In addition, the RF receivers are free to use the techniques described above to implement and use multi-channel reception. The RF receivers use some of the blocks or circuitry (e.g. LNA 15, mixer 20, PGA 30, ADC 35, decimator 35, etc.) shown in previous figures (e.g 1 until 2 , 4 until 7 and 9 ) described above were used. The blocks or circuits provide similar functionality and features to those associated with above 1 until 9 described. Accordingly, the description of these blocks or circuits will not be repeated below.

11 FIG. 1 shows a circuit arrangement for an HF receiver 5 according to an exemplary embodiment, which supports simultaneous detection. The HF receiver 5 has a front-end circuit arrangement 277 . In the embodiment shown, the front-end circuitry 277 includes the LNA 15 (which receives a gain adjust signal LNA_Gain from the controller 105), the mixer 20, the RF frequency synthesizer (LO) 25, the PGA 30 (which receives a gain adjust signal PGA Gain from the controller 105 receives), the ADC 35, the decimator 55, the DC compensation circuit 60, the digital mixer 75, the decimator 80, the channel filter 85 and the NCO 70. To reduce power consumption, cost and complexity, certain blocks or circuits are shared between the different PHYs. In the figure, the shared blocks or circuits (or the hardware (which might include or use firmware or software)) are labeled 280 . Therefore, note that the shared circuitry 280 also includes the frame controller circuitry (FRC) 315 in addition to the front-end circuitry 277 . The output of channel filter 85 is provided to demodulator 305 (labeled "Demod_a, PHYa" and corresponding to a first PHY) and demodulator 310 (labeled "Demod_b PHYb" and corresponding to a first PHY). Demodulator 305 and demodulator 310 are used for simultaneous preamble and/or sync word detection of the two respective PHYs.

Some techniques known to those of ordinary skill in the art can be used to detect the preamble and/or the sync word. A simple method for detecting the preamble and/or the synchronization word can consist of demodulating the signal and performing a binary comparison between a predefined sequence and the demodulated output. If a match occurs with no errors or relatively few errors, the sequence could be considered detected. Examples of more complex detection methods are described in US patent application no. 15/370,674 entitled "Radio-Frequency Apparatus with Digital Signal Arrival Detection and Associated Methods" and in U.S. Patent Application No. 16/177,373 entitled Apparatus for Radio Frequency Receiver with Improved Timing Recovery and Frequency Offset Estimation and Associated Methods.

The demodulator 305 provides the controller 105 with signals FOEa (the frequency offset estimate FOE of Demod_a corresponding to the PHYa) and PDa (the preamble detect tion signal from Demod_a). Likewise, the demodulator 310 provides the controller 105 with signals FOEb (the frequency offset estimate of Demod_b corresponding to the PHYb) and PDb (the preamble detection signal of Demod_b). In response to the FOEa and FOEb signals, the controller 105 generates, depending on which demodulator detected the preamble (i.e. whether the FOEa-corresponding demodulator 305 or the FOEb-corresponding demodulator 310 detected the preamble), the frequency compensation signal (Freq_komp) that is used to adjust the NCO 70 output frequency and/or the RF frequency synthesizer 25 output frequency. Signals PDa and PDb are used to indicate preamble detection by demodulator 305 and demodulator 310, respectively.

Demodulator 305 also generates and provides a signal RSSIa indicative of the RSSI of the signal processed by demodulator 305 and provides it to controller 105. Likewise, demodulator 310 generates and provides a signal RSSIb indicative of the RSSI of the signal processed by demodulator 310 es the controller 105. The RSSIa and RSSIb signals are respectively used to determine the gains of the LNA depending on which demodulator detected the preamble (ie, whether the RSSIa-corresponding demodulator 305 or the RSSIb-corresponding demodulator 310 detected the preamble). 15 and the PGA 30. The RSSI signals (or power level signals) are typically obtained after the channel filter and indicate the in-band power level. When the RSSI exceeds the level at which reliable detection is possible, ie when the RSSI exceeds the detection level, the gain in the front-end circuitry 277 can be reduced while still aiming for sufficient RSSI for reliable detection becomes. In other words, the excess signal-to-noise ratio (SNR) at the input of the demodulator is traded for improved linearity in the front-end circuitry 277 while maintaining relatively good demodulation performance. This scheme helps improve the receiver's intermodulation tolerance. Different PHYs may have different detection levels, requiring different AGC thresholds (if the RSSI exceeds the AGC threshold, the gain of the front-end circuitry 277 may be reduced). For example, when signal PDa indicates detection of PHYa, controller 105 may set the ACGT threshold to the value corresponding to the detection level of PHYa. Another example of RSSI-based gain control is in U.S. Patent No. 10,469,112 entitled "System, apparatus and method for performing automatic gain control in a receiver for a packet-based protocol".

Demodulator 305 demodulates the signal corresponding to PHYa to generate data signals DATAa. Demodulator 310 demodulates the signal corresponding to PHYb to generate data signals DATAb. The respective data signals (DATAa and DATAb) feed the two inputs of MUX 95. In response to the DATAa/DATAb control signal from controller 105, MUX 95 provides FRC 315 with either the DATAa signal or the DATAb signal. The controller 105 provides the channel filter 85 with a bandwidth adjustment signal (CHF_BW, which may contain multiple bits). The CHF_BW signal is used to program the channel filter 85 bandwidth. Alternatively, the CHF_BW signal can be used to change the shape of the filter characteristics or the transfer function. For example, when a PHY is detected, the filter can be altered to provide a matched filter response, i.e. matched to the detected PHY, which can be beneficial for receive sensitivity.

As mentioned above, the RF receiver can be in 11R1 and sample R2 simultaneously. 12 shows details of the scanning process while 13 shows the worst possible R2 preamble arrival for a communication system operating according to the Z-Wave protocol. Referring again to 12 Sampling PHYs R1 and R2 simultaneously (sampling the received RF signals corresponding to the respective two PHYs) shortens the sampling cycle. For the same preamble length, simultaneous sampling allows for longer sample periods and hence fewer false preamble detections and higher receiver sensitivity. Note that the "sampling period R1 + R2" is dictated by the PHY R1 since the PHY R1 corresponds to the lower data rate. R2 detection may be enabled throughout the R1 sample period (AZ). R2 sensing should be enabled for at least the length of time of the "Minimum R2 Detection Window" (labeled "Min R2 Detect Window"). But enabling R2 sensing across the entire R1-AZ allows for an even longer R2 detection window.

Referring again to 13 For example, the time labeled 330 indicates that the R2 preamble has arrived somewhat late and as a result the first preamble detection may fail. The time labeled 332 indicates that the preamble is within the RS-AZ and can therefore be successfully detected. In addition to the simultaneous preamble detection functionality, RF receivers have various which embodiments have certain other features and attributes. As an example, the FRC 315 and the various blocks in the front-end circuitry 277 (the shared circuits 280) may be shared between multiple PHYs. Furthermore, depending on which preamble detector triggers (ie, which one detects a preamble first), various optimizations can be performed.

For example, in some embodiments, the PHYa and the PHYb may have different channel filter bandwidth specifications. First, the bandwidth of the channel filter 85 is set to the widest specified bandwidth to allow both PHYs to receive (receive the RF signals corresponding to the PHYs). By matching the bandwidth of the channel filter 85 to the particular bandwidth of the PHY for which the preamble is detected, improved sensitivity and improved interference immunity are obtained. As another example of an optimization or feature, the different PHYs may have different maximum frequency offsets in some embodiments. Usually, the AFC range has a frequency setting limit parameter. This parameter can be set based on which preamble detector triggers (i.e., which of the received RF signals corresponding to the respective PHYs has a preamble detected for). The limit is used to keep the frequency setting within the specified range. Without this limit, the noise on the frequency offset estimate can cause the frequency setting to move outside of the valid range. As another example of an optimization or feature, in some embodiments, prior to preamble detection, both the RSSIa and the RSSIb correspond to the same received signal, therefore the values of the RSSIa and the RSSIb would be substantially (or nearly or nearly) the same. After the preamble detection, the bandwidth of the channel filter 85 can change and the AFC can be adjusted. These events may affect the RSSI signals, so in some embodiments the RSSI of the associated preamble detection is used for AGC purposes (i.e., aligning the LNA 15 and PGA 30 gains).

As another example of an optimization or feature, the FRC 315 may have a variety of features in some embodiments. Such features may include sync word timeout, sync word detection, PHY header decoding, dewhitening, FEC decoder, address filtering, frame checksum sequence check (FCS checking), etc., as desired . the FRC 315 may also process some or all of the medium access control functions (MAC functions) such as frame control, MAC address filtering, PAN ID filtering, security processing, information element handling, etc. For examples of these functions, see the IEEE 802.15.4-2015 standard for details. In various embodiments, FRC 315 may be configured (e.g., using one or more control signals (not shown) provided by controller 105) to process MAC functions. By using the control signals, the controller 105 can cause or control enabling, disabling, or configuring the MAC functions based on the pattern detection signals PDa and/or PDb. For example, in a multi-protocol receiver application, MAC functions can be chosen based on the pattern detection signals PDa and/or PDb. As another example, the receiver may simultaneously search for a Zigbee preamble and/or sync word and a Bluetooth Low Energy (BLE) preamble/access address. When a Zigbee signal is detected, the controller 105 may configure the FRC 315 to activate a Zigbee MAC or Zigbee MAC functionality. Conversely, upon detection of a BLE signal, the controller 105 can configure the FRC 315 to activate a BLE-MAC or a BLE-MAC functionality. To support the multi-protocol application, the settings and status of the supported protocols may be maintained in memory (such as, for example, non-volatile memory (not shown)). The controller 105 may use a memory controller to write the settings and status information from the FRC 315 to memory based on pattern detection results. In addition, the controller 105 may use a memory controller to read the settings and the status information back into the FRC 315 based on pattern detection results. Examples of such settings and status signals include, but are not limited to, PAN ID, source and destination addresses, supported PHY capabilities, frame control fields, etc. See the IEEE 802.15.4-2015 standard for more settings and status information.

As another example of an optimization or feature, the FRC 315 may have a variety of features in some embodiments. Such features may include sync word timeout, sync word detection, PHY header decoding, dewhitening, FEC decoder, Fra mechecksum sequence check (FCS check), etc.

14 FIG. 34 shows a flow chart 340 for simultaneous detection in an RF receiver according to an exemplary embodiment. The process may be implemented, for example, by the controller 105 described above. Referring again to 14 At 343, Demod_a and Demod_b (e.g., corresponding to demodulator 305 and demodulator 310, respectively) are activated. At 346 a check is made as to whether a preamble is detected. If not, the test continues at 346. However, if a preamble is detected, a check is made at 349 of the PDa and PDb signals to determine which of the demodulators detected the preamble. When Demod_a has detected the preamble (as indicated by PDa), at 352A the AFC limit for PHYa is set, the signal Freq_komp is based on FOEa, the channel filter bandwidth signal CHF_BW is set based on the channel bandwidth specifications for PHYa, and the gains of the LNA and the GA based on RSSIa. At 355A, the MUX 95 is controlled to provide the FRC 315 with the DATAa signals and the settings of the FRC 315 are adjusted to the parameters of PHYa (the PHY corresponding to the received signal for which the preamble was detected). . At 358A, the PHYa frame is received or extracted. If, on the other hand, Demod b has detected the preamble (as indicated by PDb), at 352B the AFC limit for PHYb is set, the signal Freq_komp is based on FOEb, the channel filter bandwidth signal CHF_BW is set based on the channel bandwidth specifications for PHYb and the gains of the LNA and the PGA based on RSSIb. At 355B, the MUX 95 is controlled to provide the FRC 315 with the DATAb signals and the settings of the FRC 315 are adjusted to the parameters of PHYB (the PHY corresponding to the received signal for which the preamble was detected). . At 358B, the PHYb frame is received or extracted.

15 12 shows how the bandwidth of the channel filter 85 is determined in RF receivers according to various embodiments. Waveform 361 corresponds to the modulation spectrum for the received signal corresponding to PHYa, while waveform 364 corresponds to the modulation spectrum for the received signal corresponding to PHYb. The waveforms are related to the frequency at the output of the digital mixer 75. Note that in the example shown both modulation spectra have a worst case frequency offset. Waveform 367 corresponds to the initial frequency response of channel filter 85. As mentioned above, the bandwidth of channel filter 85 is set to accommodate the modulation spectra of both PHYa and PHYb. In the example shown, waveform 370 shows the frequency response of channel filter 85 after a PDa trigger (ie, a preamble corresponding to PHYa was detected). Waveform 361 after AFC settling is superimposed on waveform 370 to show the programmed bandwidth of channel filter 85 compared to waveform 361 (the modulation spectrum for the received RF signal corresponding to PHYa). As the figure shows, the bandwidth of the channel filter 85 is slightly larger than the maximum spectrum width of the waveform 361 in order to properly accommodate the spectrum of the received RF signal corresponding to PHYa.

16 shows a circuit arrangement for an HF receiver 5 according to an exemplary embodiment. In this embodiment, SUN PHYs are used by way of example and not limitation. More specifically, in the Institute of Electrical and Electronics Engineers (IEEE) 802.15.4 standard, some PHYSs including SUN-FSK (frequency shift keying), SUN-OFDM (orthogonal frequency division multiplexing), and SUN-OQPSK (offset quadrature phase shift keying, offset quadrature phase shift keying). In some applications it might be desirable for a single device to support multiple SUN PHYs (eg Wi-SUN is considering adding SUN OFDM with backwards compatibility with SUN FSK). 16 shows an RF receiver that can support multiple SUN PHYs. For example, a transmitter may broadcast signals that conform to either SUN-FSK or SUN-OFDM. The receiver 5 has two demodulators 305 and 310, one (e.g. the demodulator 305) for demodulating the FSK, which (in relation to OFDM) is a narrowband signal, and one (e.g. the demodulator 310) for demodulating the OFDM, which is a broadband signal (in terms of FSK).

In this embodiment, the received OFDM signal demodulator 310 may use a long training field/short training field (LTF/STF) detector (similar to generating PDa described above), as will be appreciated by those of ordinary skill in the art will. Conversely, as described above and understood by those of ordinary skill in the art, the demodulator 305 may use a preamble detector and/or a synch word detector to generate the PDb signal. In this example, the spectrum corresponding to the SUN OFDM PHY can be considerably broader than the corresponding spectrum for the SUN FSK be PHY. In the exemplary embodiment shown, separate decimators and channel filters are used to accommodate spectrum disparity.

More specifically, on the signal path for the demodulator 305, the decimator 80 and the channel filter 85 are used. Conversely, on the signal path for the demodulator 310, the decimator 120 and the channel filter 115 are used. Note that two separate control signals, CCHF-BWa and CHF_BWb, are provided by controller 105 to program the bandwidths of channel filters 85 and 115, respectively. Note that depending on various factors, a single decimator and channel filter may be used, as will be appreciated by those of ordinary skill in the art. These factors include design specifications, performance specifications, cost, IC or device area, available technology (e.g. realizable bandwidth for a channel filter, semiconductor manufacturing technology, etc.), target markets, target end-users, and the like, as will be understood by those of ordinary skill in the art.

17 shows a circuit arrangement for an HF receiver 5 according to an exemplary embodiment. This embodiment offers simultaneous preamble detection on different frequency channels. More precisely, in Z-Wave, the PHY R1 signal is sent at 908.40 MHz, while that of PHY R3 is sent at 916 MHz. As an alternative method to strengthen the preamble detection window, the arrival of the signals from R1 and R3 can be detected simultaneously. 16 provides the architecture for an RF receiver to perform simultaneous detection. Note that an IF path is not limited to a single demodulator. Thus, as an example, IF path_a could be used for PHYs R1 and R2, while IF path_b could be used for PHY R3. In this design, PHYs R1, R2, and R3 could be searched for simultaneously. Since the transmitted signals corresponding to R1 and R3 use different frequencies, two NCOs are used, the NCO 80 for one PHY (e.g. R1), and the NCO 130 for the other PHY (e.g. R3). Similar to the embodiment in FIG 16 separate decimators and channel filters are used for the receive paths corresponding to the two PHYs. More specifically, the decimator 80 and channel filter 85 are used for the received signal path corresponding to one PHY (e.g., R1), and the decimator 120 and channel filter 115 are used for the received signal path corresponding to the other PHY (e.g., R3).

The controller 105 generates signals Freq_komp_a and Freq_komp_b that are used to set the output frequencies of the NCO 80 and NCO 130, respectively. In addition, the signals Freq_komp_a and Freq_komp_b are provided to the MUX 375 as input signals. In response to the selection signal provided by the controller 105 (PDa/PDb, i.e. from which of the demodulators 305 and 310 a preamble was detected), the MUX 375 provides the RF frequency synthesizer 25 with either Freq_comp_a or Freq_comp_b. Frequency synthesizer 25 uses the output of MUX 375 to set its output frequency (the LO signal used by mixer 20). Note that in the embodiments shown above, receivers for simultaneous detection of two preambles (e.g., RF receivers having two demodulators 305 and 310) are each shown. However, as will be appreciated by those of ordinary skill in the art, RF receivers according to other embodiments may be used for simultaneous detection of more than two preambles by making appropriate modifications (e.g., using more than two demodulators, decimators, channel filters, etc.) as desired. As will be understood by those of ordinary skill in the art, the choice of the number of preambles detected simultaneously depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technology such as semiconductor manufacturing technology, target markets, target end users, etc.

A network can use a PHY to initiate a switch to another PHY. For example, in BLE after a connection, the PHY is determined by examining the capabilities and configurations for both devices in a process known as the PHY update process. For more information, see the Bluetooth Specification Version 5.0, Vol. 6, Part B, Section 5.1.10. The simultaneous PHY detection capability of various embodiments would eliminate the need for the PHY update process. This attribute would reduce the latency and power consumption associated with the overhead of the PHY update process. For example, if link quality allows, a node may immediately decide to transmit using a higher rate PHY, and the receiver having simultaneous detection according to various embodiments would be able to use the higher rate PHY to recieve. To support simultaneous detection, nodes can share the simultaneous detection capability with other nodes by sending a PHY capability field to have the other Kno ths can benefit by using the simultaneous detection capability. Additionally, the PHYs that are part of the simultaneous detection may be included in the shared PHY capability field. In the IEEE 802.15.4 standard, the simultaneous detection capability can be conveyed using the PHY capability information element (IE) (see eg IEEE 802.15.4-2015, section 7.4.4.10). Additionally, the PHY capability IE may include the PHYs that are part of the simultaneous detection scheme or arrangement. By sharing the simultaneous detection capabilities, networks can have a migration path from a legacy method of PHY switching (eg, the PHY update process in BLE) to a more advantageous method of simultaneous detection.

It should be noted that in some embodiments, controller 105 may provide fewer control signals than shown in the figures, as desired and understood by those of ordinary skill in the art. For example, in some embodiments, the controller 105 may provide a single control signal, i.e., the bandwidth adjustment signal, i.e., the CHF_BW signal described above (which may contain multiple bits, or the CHF_BWa and CHF_BWb signals, etc., if two or more channel filters are used). . In some embodiments, other control signals, i.e. one or more of the PGA_Gain signal, the LNA_Gain signal, a control signal(s), the FRC 315 is (are) supplied, etc., as will be understood by those of ordinary skill in the art. The choice of the type and number of control signals depends on various factors, as will be understood by those of ordinary skill in the art. These factors include design specifications, performance specifications, cost, IC or device area, available technology, target markets, target end-users, and the like, as will be understood by those of ordinary skill in the art.

One aspect of the disclosure relates to RF communication systems that support multiple modulation schemes. The modulation scheme is the process of converting data into electrical signals suitable for transmission over a medium. Different modulation schemes are characterized by a different process or a different order of processes. A communication device according to example embodiments includes nodes that can communicate with other nodes in the system, as described below. The nodes may have receive (RX) and transmit (TX) capability, i.e., transceiver capability, as desired and described below. By way of example and not limitation, nodes, receivers, and transmitters according to various embodiments, such as the example embodiments described herein, may use one or more of the following modulation schemes: Frequency Shift Keying (FSK), M-ary FSK, M-ary PSK, Ein /off sampling (OOK), amplitude shift keying (ASK), quadrature phase shift keying (QPSK), offset quadrature phase shift keying (O-QPSK), binary phase shift keying (BPSK), 1/4π-QPSK, quadrature amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and chirp spread spectrum (CSS). The choice of modulation scheme used depends on a variety of factors such as design and performance specifications, application scenarios, cost, complexity, available technology, etc., as will be understood by those of ordinary skill in the art.

Emerging network protocols such as Wi-SUN and Amazon Sidewalk use nodes that strive to communicate over a relatively wide range of path loss and interference/multipath conditions. A number of modulation schemes may be used to support reliable communications, with each modulation scheme optimized for a specific use case. For example, an FSK modulation scheme may be used for relatively long distance communications and an OFDM modulation scheme may be used for relatively high throughput communications. In general, a high throughput modulation scheme is desirable because it benefits battery life or has lower power consumption and also benefits network service capacity (short media usage time). Conversely, long-distance transmission typically uses a modulation scheme optimized for lower data rates.

The wide variety of use cases, eg in the IoT space, use dedicated and optimized modulation schemes. The wide variety of use cases is the result of different cost structures in the nodes and different communication conditions. For example, the cost structure may depend on the application and various factors such as whether the node serves as a gateway device or as an end device, or whether it is powered by a coin cell, a lithium thionyl chloride battery, or mains power. The communication conditions may require communications over a relatively long distance reasonably high throughput, relatively severe multipath, or relatively severe interference. For example, it is known that an OFDM-based modulation scheme is suitable for relatively high throughput with a relatively severe multipath effect, while an FSK modulation scheme is suitable for relatively low-cost/low-power and relatively long-distance communication. A modulation scheme is characterized as having or using a unique modulation, eg FSK, OFDM, O-QPSK or chirp spread spectrum (CCS) are examples of modulation schemes according to this application. Note that OFDM with different Modulation and Coding Schemes (MCSs) is typically not considered a different modulation scheme, and O-QPSK or CSS with two different spreading factors is also not considered a different modulation scheme.

Conventional methods consume a relatively large amount of time and energy to facilitate the transition from one data rate to another, i.e. from one modulation scheme to another. As a result, trade-offs are made between RX sensitivity and latency, where sensitivity affects transmission range and latency affects throughput, power consumption and network capacity.

Example embodiments use apparatus and associated methods to transmit and receive packets between multiple nodes in an RF communication system using multiple modulation schemes for multiple data rates. The RF receivers in the nodes receive packets without any prior knowledge of which of the modulation schemes will be used for the transmission of the packets (e.g. by other nodes in the system). to dispose. Exemplary embodiments reduce cost and overhead in multi-PHY networks. They also simplify the communication protocols. These attributes favor power consumption, network service capacity, range, and throughput.

The disclosed concepts aim at reducing costs and overhead in networks with multiple PHYs. They also simplify the communication protocols. These attributes favor power consumption, network service capacity, range, and throughput. In exemplary embodiments, overhead is reduced by taking advantage of advances in receiver detection techniques. These detection techniques allow cost effective solutions to detect more than one modulation scheme simultaneously. As a result, it is possible to optimize modulation schemes for given or desired use cases. In addition, the modulation schemes and SHRs (synchronization fields) can be independently optimized to best serve given or desired use cases. For example, a relatively long range, relatively low rate PHY can be based on an O-QPSK Direct Sequence Spread Spectrum (DSSS) PHY with an SHR long enough for optimal sensitivity. be implemented. Such an SHR would limit the throughput of a modulation scheme with a relatively high data rate. However, in exemplary embodiments, the SHR can be separately optimized for relatively high throughput. As just one example, an OFDM modulation scheme can be used for a relatively high throughput use case, where the SHR (or STF+LTF, the synchronization field for SUN OFDM) can be of shorter duration than the SHR for a relatively long distance, so that throughput is optimized.

OFDM has the disadvantage that it uses a non-constant envelope. Information in the OFDM signal is embedded in both phase and amplitude. As a result, a linear power amplifier with sufficient linearity but higher power consumption is used. On the other hand, O-QPSK (sinusoidal), CSS and FSK have constant envelopes, which allows the use of non-linear power amplifiers. Non-linear power amplifiers can have higher power efficiency compared to linear power amplifiers. In general, constant envelope modulation schemes are preferred when low power consumption in transmit mode is desired. Battery powered devices can have a relatively limited power budget. Constant envelope modulation schemes are capable of producing higher output power than non-constant envelope modulation schemes. This attribute is desirable when communication over a relatively long distance is desired. The disclosed techniques as used in exemplary embodiments recognize that different types of modulation each have advantages and disadvantages. By allowing different modulation schemes to be used without using prior knowledge (prior knowledge) of the modulation scheme being used, apparatus and methods according to various embodiments allow for increased performance efficiency and higher figures of merit, as will be discussed in more detail below.

Continuing with the above example, by using the simultaneous detection techniques discussed above, a receiving node or an RF receiver in a node would be able to scan for these two modulation schemes without any prior knowledge of what modulation scheme is used to transmit the RF signals that the receiver is receiving. In other words, the RF receiver will find this out by looking for both SHRs at the same time. From the transmitting node's (or RF transmitter's) point of view, once it has an indication of the link quality, it can make the decision to choose an appropriate modulation scheme without first sending a mode switching packet or processing a PHY negotiation protocol. In this way, the PHY with a relatively high throughput is not compromised by also supporting a PHY with a relatively long distance. Conversely, the reception capability of the long-distance PHY is not affected by also supporting a PHY with a relatively high throughput.

In some embodiments, a simplification can be made by not allowing a node to receive more than one packet at a time. When multiple packets are allowed to be received simultaneously by a node, the responses to those packets, such as acknowledgments, can be relatively complicated. For example, when a packet is received, it may delay its transmission response since it may adversely affect the reception of another packet that is still being received. The node waiting for the response would listen longer due to the delayed response. The latency period would be a function of the lowest data rate and the longest packet length. If a node is prohibited from receiving more than one packet at a time, the replies can be well defined, which would save power in the nodes expecting a reply.

In some embodiments, further simplification can be made by sharing the Media Access Control (MAC) format of modulation schemes. This simplifies the MAC protocol, reduces costs and improves coexistence. The hardware and software or firmware used for a MAC can be more compact than when multiple MACs are used. In other words, sharing the MAC results in less hardware resources being used and less memory and processing power being used, resulting in lower overall costs. Packet traffic arbitration (PTA) may be an integral part of the MAC to deal with traditional MAC-to-MAC competition for bandwidth, and the PTA may not have all the data to make optimized transmission priority decisions. In other words, in a conventional approach, the number of successful and unsuccessful transmissions using a first MAC may not be available in a second MAC. With a single shared MAC, this data could be made available relatively easily, simplifying priority calls.

Some embodiments can be used in combination with conventional approaches, if desired. For example, a SUN OQPSK PHY can be combined with the SUN OFDM PHY. In this case, the nodes can be configured to look for a SUN-OQPSK-SHR and a SUN-OFDM-SHR at the same time. Once one of these SHRs has been detected, the note relies on the conventional scheme of using the PHR in the case of SUN-OQPSK to set the spreading factor, for example, or using the MCS in the case of SUN-OFDM. The PHR is the PHY header and is typically sent after the SHR. The PHR contains PHY information regarding the packet, e.g. packet length, rate mode or spreading factor, MCS, data whitening enabled/disabled, frame checksum (FCS) length, etc.

In some embodiments, the nodes may send packets including their PHY capability information element (IE). A node could use the IE to communicate which PHYs it can receive at the same time. In addition, IE could also indicate that it is able to act on mode change packets or a PHY negotiation protocol. By communicating a node's PHY capabilities, other nodes can choose a modulation scheme switching method supported by the node. For example, conventional devices that do not support simultaneous detection may support a conventional method. In the same network, more advanced nodes according to exemplary embodiments using a receiver with the simultaneous detection technology described above can be added. By signaling the modulation scheme change method(s) in the PHY capability IE, a network to be upgraded to use the disclosed concepts.

Example embodiments support a variety of use cases using different modulation schemes. For example, in one use case, the modulation schemes O-QPSK and OFDM or FSK, O-QPSK and OFDM may be supported. In initial communication, a node could use a modulation scheme that supports relatively long distance communications, e.g., O-QPSK. Once the initial connection is established, the node can collect signal quality metrics such as packet success rate, RSSI, signal-to-noise ratio EVM (the error vector magnitude), connection margin, and so on. Based on the signal quality index, a node can decide to change the modulation scheme; e.g., if the signal quality allows it, the node may switch to a modulation scheme with a relatively higher throughput or a relatively higher data rate such as OFDM. Given a certain amount of payload data, a higher data rate allows the transmission time to be reduced. Shorter transmission time can save energy and increase network capacity. Conversely, if the packet success rate falls below a threshold, a node may decide to switch to a relatively long distance modulation scheme such as O-QPSK. This could help maintain communication even when conditions deteriorate, such as when mobility lengthens the route or creates obstacles. It should be noted that the change to a new modulation scheme is not prematurely signaled to the RF receiver. This scheme allows for an optimized SHR. and STF/LTF design that supports relatively high figure of merit values for all supported data rates. Note that a simplification can be made in this use case by disallowing receipt of more than one packet at a time, as discussed above, allowing a single protocol stack or MAC that supports multiple modulation schemes.

It should also be noted that the figure of merit is related to the following performance goals: higher network capacity, lower energy or power consumption, and higher data throughput. Efficient networks use the majority of their energy to transmit data payloads (physical layer service data units, PSDU). A relatively small portion of the total power should be consumed for overhead such as synchronization and the PHY header. Conventional nodes spend a relatively long time on overhead, e.g., by sending a mode switching packet followed by a settling delay. The settling delay is used to give the receiving node time to process the mode change packet and prepare for the new modulation scheme. The actual data transmission is contained in the PSDU. In exemplary embodiments, the use of a mode change PLCP protocol data unit (PPDU) or PHY negotiation process is eliminated. A packet with a new modulation scheme can be sent without consuming power, time and spectrum for mode switching PPDU or PHY negotiation transactions. This attribute translates to improved battery life (or lower power or energy consumption), higher effective throughput, reduced latency, and improved network capacity. In addition, the PSDU typically includes addressing and is secured by encryption, which improves network security. Nodes according to exemplary embodiments spend relatively little time on overhead and more time on PSDU transmission. This attribute results in higher throughput, less wasted energy, and higher network capacity.

In some embodiments, the above use case can be extended by an OFDM PHY that supports MCS switching similar to the SUN OFDM modulation scheme. The modulation scheme for a relatively long distance can be yet another modulation scheme, e.g., O-QPSK. In such embodiments, it is not necessary to support the long distance in the OFDM modulation scheme. This attribute allows to skip the lower data rates in the OFDM modulation scheme and to optimize the LTF/STF and the PHR without using the relatively long distance schemes. Such embodiments may provide shorter STF, LTF and PHR durations and a higher figure of merit while still having the benefit of further increasing the data rate. These embodiments can be further extended by adding rate switching similar to the SUN-O QPSK modulation scheme, e.g., for a relatively long distance modulation scheme. Such embodiments may be viewed as a hybrid, combining the benefits of the use case discussed above with the benefits of rate mode switching and/or MCS switching.

A third use case may, in some embodiments, be as discussed above a single shared MAC can be used instead of multiple MACs. 18 FIG. 4 shows a network or protocol stack 400 with a common media access control (MAC) according to such embodiments. The rest of the protocol stack is known to those of ordinary skill in the art and will not be described further here. In the example shown, the shared MAC (labeled "IEEE 802.15.4 MAC layer") allows for reduced device complexity, improved coexistence, and lower maintenance costs (ie, fixing errors or bugs in a single stack rather than multiple MAC arrangements). ). In the example shown, the protocol stack supports four modulation schemes by using four respective PHYs, FSK, O-QPSK, OFDM and CSS. As will be understood by those of ordinary skill in the art, other protocol stacks supporting other modulation schemes are contemplated and may be used by making appropriate modifications as desired.

Further details regarding the operation of nodes and related methods according to exemplary embodiments are provided below. Typically, a packet consists of a preamble, a synchronization frame delimiter (SFD, also known as a sync word), a PHY header (PHR), and a PHY payload. Some modulation schemes can do without the SFD, e.g. like CSS/LoRa. In OFDM, the preamble and the SFD are replaced by a short training field (STF) and a long training field (LTF). A network using nodes according to example embodiments may employ more than one modulation scheme. For example, one node may be capable of transmitting an FSK RF signal while another node may be capable of transmitting an OFDM RF signal, or a node may be capable of transmitting an FSK signal while another node may be able to transmit either an FSK RF signal or an OFDM RF signal. For this purpose a node can have an FSK modulator or an OFDM modulator or both. The above examples are provided for illustrative purposes only, and other possibilities are envisaged and exist. Therefore, the nodes can also be capable of other modulation schemes (e.g. O-QPSK, BPSK, OOK, ASL, QAM, etc.). In general, networks using nodes according to example embodiments use at least two modulation schemes and a node should be able to transmit at least one modulation scheme. If a node is capable of transmitting more than one modulation scheme, a transmit controller (e.g., a finite state machine (TX-FSM)) can be used to choose the appropriate or desired modulation scheme. The choice may be based on previous transmissions. As an example, the technique described in the IEEE 802.15.4-2020 standard is referred to as a link margin information element (IE) (obtained from a previous transmission). Packet success rate, RSSI, etc. can be used as examples as desired.

RF receivers according to example embodiments use Modulation Scheme Detectors (MSDs), as described in detail below. When modulated using one of the several modulation schemes, the fields listed above have different characteristics determined by their phases, amplitudes and bit sequences. The MSDs use these attributes to detect the modulation scheme used among the multiple modulation schemes with relatively few false detections. In various embodiments, a FSM (RX-FSM) or controller controls the state transitions, configuring the receiving node (the RF receiver in the node), and receiving the packet.

19 shows a circuit arrangement for a network node 520 according to an exemplary embodiment. The network node 520 has both a reception function (via an HF receiver circuit arrangement 5) and a transmission function (via a transmitter circuit arrangement 515), ie forms an HF transceiver. Correspondingly, numbered blocks/circuits/elements are in 19 their above (e.g. in connection with 17 or other Figures) are similar to and/or operate in a similar manner to counterparts described. In the embodiment shown in 19 As shown, demodulator 305 demodulates received signals modulated using FSK modulation. Likewise, demodulator 310 demodulates received signals modulated using OFDM modulation. However, as will be appreciated by those of ordinary skill in the art, FSK and OFDM are merely examples and, such as discussed above, other modulation schemes are possible and contemplated. 19 also has two MSDs, an MSD_FSK 403 and an MSD_OFDM 406. The MSD_FSK 403 detects signals modulated by FSK and provides an indication of the detection via the MSD_FSK signal provided to the controller 105. Likewise, the MSD_OFDM 406 detects signals modulated by OFDM and provides an indication of the detection via the MSD OFDM signal provided to the controller 105 .

In exemplary embodiments, the MSDs such as the MSD_FSK 403 and the MSD_OFDM constitute signal detectors and can be provided using signal detectors in various ways as discussed above (eg, the DSA 90) and understood by those of ordinary skill in the art. Each filtered baseband (ie, the output of the channel filters) may have an MSD. Typically, each MSD is configured to detect the presence of a desired, specific, different modulation scheme in the signal received at the input. The FRC 315 (RC-FRC) provides the controller 105 with a packet received output when a packet is successfully received. Memory 409 is used by controller 105 to perform its functionality (e.g., program memory, working memory, holding network information, network status, etc.). The controller 105 provides an activation signal (RX_Activation) for activating the receiver 5 and RX configuration signals (RX_config) for configuring the RF receiver 5 .

The controller 105 provides a signal TX_Activation for activating the transmitter or the transmitter circuitry 515 . The controller 105 also provides TX configuration signals (TX_config) for configuring the transmitter 515. The TX-FRC 412 is the transmitter frame controller. It performs processing on the PSDU (i.e., the TX_PSDU received from the controller 105) such as insertion of a synchronization header (SHR), block encoding, forward error correction, frame checksum generation, data whitening, etc. to generate the TX PPDU signal, the provided to the modulator 415. The modulator 415 modulates the TX PPDU signal using a desired modulation scheme. Note that there is an alternative modulation scheme for FSK that uses the LO 25 as desired. The LO 25 provides the TX_LO signal to the DAC 418 . The DAC 418 converts the modulated output of the modulator 415 into an analog signal that it provides to the power amplifier (PA) 421 . PA 421 amplifies the signal from DAC 418 and transmits the amplified signal through RF switch 11 and antenna 10. In response to a control signal (e.g., from controller 105), RF switch 11 couples antenna 10 to either RF -Receiving operations with the HF receiver 5 or for HF transmission operations with the HF transmitter 515.

20 10 shows a controller 105R for the RF receiver 5 of FIG 19 . In various embodiments, controller 105R is part of controller 105 (see FIG 19 ), but it can be implemented separately as desired. Referring again to 20 controller 105R includes an application processor 430 that executes at least a portion of a protocol stack as well as at least a portion of the application layer. The application processor receives an event, such as a sensor input, processes the event (eg, by running an application), and provides a control output, such as an actuator signal. The application processor can initiate a receive through the MAC interface; for example, after sending a packet, a node may initiate a receive to receive an acknowledgment packet to indicate a successful transmission. In example embodiments, application processor 430 may load configuration data for RF receiver 5 into hardware registers, ie, shift registers 434 and 436 . Alternatively, the applications processor 430 may provide the configuration data directly to the hardware, but to aid in rapid configuration, the applications processor 430 may provide the configuration data stored in the memory 409 (eg, non-volatile memory) to the controller 105 upon power-up or boot-up. Then, when the configuration data is to be used, the controller 105 can load the configuration data from the registers in the controller 105 into the shift registers 434 and 436 relatively quickly. A fast configuration is desired to reduce latency to support relatively fast turnaround times between transmit and receive and vice versa.

The application processor 430 interfaces with the MAC processor 428 via a "MAC interface". The MAC processor 428 processes and delivers the MAC payload to the application processor. The MAC processor 428 provides the TX_PSDU signals (to the controller 105 to be provided to the transmitter circuitry 515 to be transmitted as RF signals, cf 19 and 23 ) and receives the RX-PSDU from the receiving circuitry 5. The MAC processor 428 provides the receiving FSM (RX_FSM) 425 with the receiver activation signal. The RX_FSM 425 receives the "Packet Received", "MSD FSK" and "MSDOFDM" signals described above from the circuitry in the controller 105. The RX_FSM 425 operates in conjunction with a timer 423 via an output signal "Timer Start" (to indicate a waiting period for packet reception) and a time-out input signal (to indicate that no packet has been received within a predetermined period of time counted by the timer 423). The RX_FSM 428 provides status output signals (labeled "Status Sx") to some other blocks or circuits. The states are described in detail below. the Latch 432 is provided with status output signals S0 and S1. The latch 432 latches an activation signal(s) from the RX_FSM 425. The state output signal S0 resets the latch 432, causing the receiver 5 to be in an idle state (not activated); ie, the signal RX_Activation has a binary value of 0. The status output signal S1 sets the latch, causing the receiver 5 to be activated; ie, the RX Enable signal has a binary value of 1. The state output signal S2 starts the shift register 434, which contains settings or configuration data for FSK reception (provided by the "configuration data" input to the shift register 434). The state output signal S3 starts the shift register 436, which contains settings or configuration data for OFDM reception (provided by the "configuration data" input into the shift register 434). The status output signal S6 provides the MAC processor 428 and the application processor 430 with a packet ready signal to process the received packet.

The state output signal S2/S3 (ie, depending on whether S2 is active or S3 is active) is used as the select signal for the MUX 438. In response to the select signal, MUX 438 provides at its output either the output of shift register 434 or the output of shift register 436 as the "RX_config" signals. The RX config signals configure the receiver to support the detected modulation schemes (FSK and OFDM in the example discussed). This configuration can change the channel filter bandwidths, the position of the MUX 95 (see 19 ), the demodulator settings (e.g. when using a demodulator that can be configured to support multiple modulation schemes), the settings for the automatic gain control (AGC) circuit (see 19 ) (e.g. to allow more headroom for a non-constant envelope modulation like OFDM when an OFDM modulation scheme is detected), the automatic frequency control (AFC) settings (e.g. using a frequency offset estimate associated with the detected modulation scheme, to, for example, the NCOa or the NCOb (see 19 ) provide frequency feedback to compensate for frequency offset) and/or the settings for the FRC 315 (e.g. to enable a particular block decoding scheme, forward error correction scheme, frame checksum polynomial, data de-whitening, etc.), but is not limited thereto.

21 FIG. 12 shows a control flow chart for the RF receiver 5 in the example embodiments shown in FIG 19 and 20 are shown. The annotations "Sx" (where "x" indicates a state number, e.g. S0 for state 0) next to parentheses indicate which parts of the flowchart correspond to a given state (see 20 and 22 ). For example, state S0 corresponds to 440 and 441 in the flowchart. At 440, the receiver is in the idle state. At 441, the receiver is activated, which activates the signal detectors (MSDs). At 442 a check is made as to whether a signal is detected. If not, control returns to 442 . Otherwise (ie, if a signal is detected), at 443 a check is made for the detected modulation scheme. If the modulation scheme is FSK (MSD_FSK=1), control proceeds to 444 . If the modulation scheme is OFDM (MSD_OFDM=1), control proceeds to 448 . In the case of FSK modulation, at 444 the timer (see 20 ) started. At 445, the receiver is configured for FSK packet reception. At 446, an FSK packet is received (or attempted to be received). At 447 a check is made for a timeout. If there is no timeout, control returns to 446 and if the packet has been received, control transfers to 452 to process the PSDU (e.g., by the MAC processor (see Fig 20 )). Otherwise, control returns to 442 to check for signal reception. As mentioned, if the modulation scheme is OFDM (MSD_OFDM = 1), then control passes to 448 where the timer (see 20 ) is started. At 449, the receiver is configured for OFDM packet reception. At 450, an OFDM packet is received (or attempted to be received). At 451 a check is made for a timeout. If there is no timeout, control returns to 450 and if the packet has been received, control transfers to 452 to process the PSDU (eg, by the MAC processor (see Fig 20 )). Otherwise, control returns to 442 to check for signal reception.

22 shows a control state diagram for the RX_FSM 425 (see 20 ) according to an exemplary embodiment. In other words, the RX_FSM 425 is implemented (eg, using flip-flops, latches, gates, etc., as will be understood by those of ordinary skill in the art) to include the 22 functionality shown implemented. The states show the in 20 shown status signals. Referring again to 22 operation begins at state S0 (sleep state). When the receiver is activated, the state transitions to S1. The controls stay the same long at S1 as MSD_FSK = MSD_OFDM = 0 (no detected signal). If MSD_FSK = 1 (FSK signal detected), the state transitions from S1 to S2, where the timer (see 20 ) is started and the configuration is carried out. When the Config signal, signaling completion of the configuration (see above), is asserted, the state transitions from S2 to S4. If no packet is received and no timeout occurs, control remains at S4. If a timeout occurs before the packet is received, control will pass from S4 to S1. However, once a packet is received, control makes a transition from S4 to S6. In state S6, the processor (see 20 ) (using the packet ready signal) that a packet has been received. The processor can process the packet as described above. OFDM packet reception follows a similar scheme. More precisely, if MSD_OFDM = 1 (OFDM signal detected) exists, the state passes from S1 to S3, where, as described above, the timer (see 20 ) is started and the configuration is carried out. When the ConfigDone signal is asserted, the state transitions from S3 to S5. If no packet is received and no timeout occurs, control remains at S5. If a timeout occurs before the packet is received, control will pass from S4 to S1. However, once a packet is received, control makes a transition from S5 to S6.

23 10 shows a controller 105T for an RF transmitter according to an exemplary embodiment. In various embodiments, controller 105T is part of controller 105 (see FIG 19 ), but it can be implemented separately as desired. Referring again to 23 the controller 105T has an application processor 430 (connected to the RX application processor in 20 can be shared) that executes at least part of a protocol stack as well as at least part of the application layer. The application processor receives an event, such as a sensor input, processes the event (eg, by running an application), and provides a control output, such as an actuator signal. The application processor can also respond to a previously received packet, eg prepare to send an acknowledgment. The modulation scheme as well as the turnaround time (the time between the end of the received packet and the beginning of the reply packet) may be based on the detected modulation scheme of the previously received packet. In example embodiments, application processor 430 may load configuration data for RF transmitter 515 into hardware registers, ie, shift registers 459 and 461 . Alternatively, the applications processor 430 may provide the configuration data directly to the hardware, but to aid in rapid configuration, the applications processor 430 may provide the configuration data stored in the memory 409 (eg, non-volatile memory) to the controller 105 upon power-up or boot-up. Then, when the configuration data is to be used, the controller 105 can load the configuration data from the registers in the controller 105 into the shift registers 459 and 461 relatively quickly. A fast configuration is desired to reduce latency to support relatively fast turnaround times between transmit and receive and vice versa.

The application processor 430 interfaces with the MAC processor 428 via a "MAC interface". The application processor processes the MAC payload and provides it to the MAC processor 428. The MAC processor 428 provides the TX_PSDU signals (to the controller 105 to be provided to the transmitter to be sent as RF signals). The MAC processor 428 provides the transmit FSM (the TX_FSM) 457 with the transmitter activation signal. The TX_FSM 457 receives the output of the comparator 455 (labeled "C _out "). The comparator 455 compares the link quality (labeled "Link Headroom") provided by the application processor to a threshold value (labeled "TH"). The TX FSM 457 provides status output signals (labeled "Status Sx") to some other blocks or circuits. The states are described in detail below. The state output signal S2 starts the shift register 459, which contains settings or configuration data for an FSK transmission (provided by the "configuration data" input into the shift register 459). The state output signal S3 starts the shift register 461, which contains settings or configuration data for an OFDM transmission (provided by the input "configuration data" into the shift register 461). The state signal S4 drives the activation circuit 463, which uses the signal "TX activation" to activate the transmitter 515 (see 19 ) as described above to transmit modulated RF signals.

The state output signal S2/S3 (ie, depending on whether S2 is active or S3 is active) is used as the select signal for the MUX 465. In response to the select signal, the MUX 465 provides at its output either the output of shift register 459 or the output of shift register 461 as the "TX config" signals. The TX config signals configure the transmitter to use the detected modulation schemes (at the discussed example FSK and OFDM). This configuration can shape the symbol in the modulator 415 (see 19 ) (e.g. shapes such as sine, raised cosine, Gaussian, etc.), adjusting the bandwidth of the DAW 418 (see 19 ), if a DAC-based IQ modulator is used, the bandwidth of the frequency synthesizer (LO) 25 (see 19 ), if eg FSK modulation with a relatively high data rate is used, the settings for the modulator 415 (eg if a modulator that can be configured to support multiple modulation schemes is used) and/or the settings for the FRC 412 (see 19 ) to enable, for example, a particular block decoding scheme, forward error correction scheme, frame checksum polynomial, data dewhitening, etc.), but is not limited thereto.

24 FIG. 5 shows a control flow diagram for the RF transmitter 515 in the example embodiments shown in FIG 19 and 23 are shown. The annotations "Sx" (where "x" indicates a state number, e.g. S0 for state 0) next to parentheses indicate which parts of the flowchart correspond to a given state (see 23 and 25 ). For example, state S0 corresponds to 465 in the flow chart. At 465 the transmitter is in the idle state. After the transmitter has been activated, a check is made at 467 as described above to determine whether the link margin is greater than a threshold TH. If not, at 469 the FSK modulation scheme is selected and at 471 the RF signal modulated using FSK is transmitted. However, if the link margin is greater than the threshold, at 473 the OFDM modulation scheme is selected and at 471 the RF signal modulated using the OFDM is transmitted.

25 shows a control state diagram for the TX_FSM 457 (see 23 ) according to an exemplary embodiment. In other words, the TX_FSM 457 is implemented (e.g., using flip-flops, latches, gates, etc., as will be understood by those of ordinary skill in the art) to include the in 25 functionality shown implemented. The states show the in 23 shown status signals. Referring again to 25 S0 represents an idle state and the transmitter is not activated. The application processor 428 can be accessed via the MAC interface (see 23 ) issue a transmitter activation signal, causing a transition from S0 to S1, based on one or more sensor inputs, one or more timers (not shown), one or more events, or a combination as desired. At S1, the output of the comparator (see 23 ), ie, C _from , read. The state transitions to S2 when C _out = 0; otherwise the state transitions to S3. At S2, the configuration data stored in the shift register 459 is loaded into the transmitter circuitry to support the FSK modulation scheme. When configuration is complete, a transition is made from S2 to state S4. Conversely, at S3, the configuration data stored in the shift register 461 is loaded into the transmitter circuitry to support the OFDM modulation scheme. When configuration is complete, a transition is made from S3 to S4. In the state S4, the transmitter 515 (see 19 ) activated by signal TX activation (see 19 and 23 ) is asserted, the PSDU (TX_PSDU, see 19 ) is supplied by the controller 105 to the transmitter 515 and the packet is sent using the chosen modulation scheme. When the transmission is complete, a transition is made to state S0.

It should be noted that MAC functions are implemented as desired by hardware (e.g. by the MAC processor 428 in 20 and 23 ) as well as software or firmware can be processed. In some embodiments, in addition to executing desired applications, the application processor 430 may also process link layer functions, network layer functions, MAC layer functions, or a combination thereof. In some embodiments, at least some of the MAC functions as described above may be shared between the supported modulation schemes. For example, both SUN-FSK and SUN-OFDM use the IEEE 802.15.4 MAC, which can be used together. In some embodiments, dedicated MAC functions (eg, MAC processors) dedicated to the supported modulation schemes are used. For example, an IEEE 802.15.4 MAC can be used when using a Zigbee modulation scheme (OQPSK), and a Bluetooth MAC can be used when using a Bluetooth modulation scheme (GFSK).

Receivers and transmitters according to example embodiments may be used in a variety of communication arrangements, systems, subsystems, networks, etc., as desired. 26 FIG. 5 shows a system 500 for radio communication according to an exemplary embodiment. The system has HF receivers 5 as described above. The system 500 includes a transmitter 515 coupled to an antenna 10A. Transmitter 515 transmits RF signals via antenna 10A. The RF signals can be received by the receiver 5 via an antenna 10B. Additionally or alternatively, a node or transceiver 520A and/or a node or transceiver 520B could receive the transmitted RF signals (via receiver 5).

In addition to receiving capability, node or transceiver 520A and node or transceiver 520B can also transmit RF signals. The transmitted RF signals could be received by a receiver 5 either in the stand-alone receiver or via the receiver circuitry of the non-transmitting node or transceiver. Other systems or subsystems with different configuration and/or different capabilities are also contemplated. For example, in some example embodiments, two or more nodes or transceivers (e.g., node 520A and node 520B) could form a network, such as an ad hoc network. As another example, in some example embodiments, node 520A and node 520B could form part of a network in conjunction with transmitter 515, for example.

RF receivers, such as the RF receiver 5 described above, may be used in a variety of circuits, blocks, subsystems, and/or systems. For example, in some embodiments, such RF receivers could be integrated into an IC, such as a microcontroller unit (MCU). 27 FIG. 5 is a block diagram of an IC 550 having an RF receiver 5 according to an exemplary embodiment. 28 is the embodiment of 27 similarly and shows an IC 550 which, in addition to the HF receiver 5, also has an HF transmitter 515. Thus, the embodiment in 28 has an RF transceiver capability and can serve as a node.

With reference to 27 IC 550 constitutes or includes an MCU. IC 550 includes a number of blocks (eg, processor(s) 565, data converter 605, I/O circuitry 585, etc.) that communicate with each other using interconnect 560. In exemplary embodiments, interconnect 560 may form a coupling mechanism such as a bus, set of conductors, or semiconductor elements (eg, traces, devices, etc.) to convey information such as data, commands, state information, and the like. The IC 550 may have a connection 560 coupled to one or more processors 565 , a clock circuit 575 , and a power management circuit or power management unit (PMU) 580 . In some embodiments, the processor(s) 565 may include circuitry or blocks for providing an information processing function (or a data processing or computational function), such as central processing units (CPUs), arithmetic logic units (ALUs), and the like. In some embodiments, processor(s) 565 may additionally or alternatively include one or more DSPs. The DSPs can provide a variety of signal processing functions such as arithmetic functions, filtering, delay blocks, and the like, as desired. Clock circuit 575 may generate one or more clock signals that facilitate or control the timing of the operations of one or more blocks in IC 550. Clock circuit 575 may also control the timing of activities using link 560 as desired. In some embodiments, clock circuit 575 may provide one or more clock signals to other blocks in IC 550 via connection 560 . In some embodiments, PMU 580 may reduce the clock speed of a device (e.g., IC 550), turn off a clock, reduce power, turn off power, disable (or shut down or enter a lower power state, or sleep) or inactive or hibernation), activation (or powering up or entering a higher power consumption state, or a normal or active state), or any combination thereof with respect to a portion of a circuit or all components of a circuit, such as one or more Make blocks in the IC 550. Further, in response to a transition from an inactive state to an active state (including, without limitation, the transition of a processor(s) 565 from a low-power state or from a sleep or sleep state to a normal operating state) turn on a clock, increase a clock rate, turn on the power, increase power, or any combination thereof.

Connection 560 may be coupled to one or more circuits 600 through a serial interface 595 . One or more circuits or blocks coupled to connection 560 can communicate with circuits 600 through serial interface 595 . As will be appreciated by those of ordinary skill in the art, circuitry 600 may communicate using one or more serial protocols, eg, SMBUS, I ² C, SPI, and the like. Connection 560 may communicate with one or more peripheral devices 590 through I/O circuitry 585 . Through the I/O circuitry 585, one or more peripheral devices 590 can communicate with the connection 560 and therefore communicate with one or more blocks coupled to link 560, eg, processor(s) 565, memory circuitry 625, and so forth. In exemplary embodiments, the peripherals 590 may include a variety of circuits, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, displays, storage devices, timers, sensors, etc.). Note that some of the peripheral devices 590 may be external to the IC 550 in some embodiments. Examples include keypads, speakers, and the like. In some embodiments, I/O circuitry 585 may be bypassed for some peripheral devices. In such embodiments, some peripheral devices 590 may couple to and communicate with link 560 without using I/O circuitry 585 . In some embodiments, such peripherals may be external to IC 550, as described above. Connection 560 may be coupled to analog circuitry 620 via data converter(s) 605 . Data converter 605 may include one or more ADCs 605A and one or more DACs 605B. ADC(s) 605A receives(receive) data signal(s) from analog circuitry 620 and convert(s) the data signal(s) to a digital format that applies to one or more blocks that coupled to link 560. Conversely, DAC(s) 605B receives data signal(s) from one or more blocks coupled to link 560 and converts the digital signal(s) to analog format, which they transmit to the analog circuitry 620. Analog circuitry 620 may include a wide variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as will be understood by those of ordinary skill in the art. In some embodiments, analog circuitry 620 may communicate with circuitry external to IC 550 to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks as desired.

A control circuit 570 is coupled to connection 560 . Control circuitry 570 may communicate with and/or control the operation of various blocks coupled to link 560 by providing control information or signals. In some embodiments, control circuitry 570 also receives status information or signals from various blocks coupled to link 560 . Additionally, in some embodiments, control circuitry 570 facilitates (or controls or monitors) communication or cooperation between various blocks coupled to link 560 . In some embodiments, control circuitry 570 may initiate or respond to a reset action or signal. The resetting action may cause resetting of one or more blocks coupled to interconnect 560, IC 550, etc., as will be understood by those of ordinary skill in the art. For example, the control circuit 570 may cause the PMU 580 and circuitry such as an RF receiver 5 or various blocks, circuits or components thereof to be reset to an initial or known state. In exemplary embodiments, control circuitry 570 may include a variety of circuit types and blocks. In some embodiments, control circuitry 570 may include logic circuitry, finite state machines (FSMs), or other circuitry to perform operations such as the operations described above. Communication circuitry 640 is coupled to interconnect 560 and also to circuitry or blocks (not shown) external to IC 550 . Communication circuitry 640 allows various blocks coupled to interconnect 560 (or IC 550 in general) to communicate with the external circuitry or blocks (not shown) via one or more communication protocols. Examples of communications include USB, Ethernet, and the like. In example embodiments, other communication protocols may be used depending on factors such as design or performance specifications for a given application, as will be appreciated by those of ordinary skill in the art.

As mentioned, memory circuit 625 is coupled to connection 560 . Thus, memory circuitry 625 may communicate with one or more blocks coupled to interconnection 560, such as processor(s) 565, control circuitry 570, I/O circuitry 585, and so forth. As will be appreciated by those of ordinary skill in the art, memory circuit 625 provides storage for various information or data within IC 550, such as operands, tags, data, instructions, and the like. The memory circuit 625 may support various protocols such as double data rate (DDR), DDR2, DDR3, DDR4, and the like, as desired. In some embodiments, memory read and/or write operations by memory circuit 625 involve the use of one or more blocks in IC 550 such as processor(s) 565 . A direct memory access arrangement (DMA arrangement) (not shown) allows for increased performance of storage operations in some situations. More specifically, DMA (not shown) provides a mechanism for performing memory reads and writes directly between the source or destination of the data and memory circuitry 625 rather than through blocks such as processor(s) 565. Memory circuitry 625 may be a Have a variety of memory circuits or blocks. In the embodiment shown, memory circuitry 625 includes non-volatile memory (NV) memory 635 . Additionally, or instead, memory circuitry 625 may include volatile memory (not shown), such as random access memory (RAM). NV memory 635 may be used to store information related to the performance, control, or configuration of one or more blocks in IC 550. For example, the NV memory 635 may store configuration information related to the operation of the RF receiver 5 (and/or the transmitter 515 in 28 ) such as configuration information for various blocks, circuits, components, etc. of the RF receiver 5 (and/or the transmitter 515 in 28 ) to save.

Various circuits and blocks, including digital and/or mixed-signal circuit arrangements, described above and used in exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, the digital and/or mixed-signal blocks, elements, components, or circuitry described in 19 , 20 , 23 and 26 until 28 may be implemented generally (or at least in part in the case of mixed-signal blocks) using digital circuitry. The digital circuitry may include circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs), or other types of programmable logic), arithmetic logic units (ALUs), standard cells, custom cells, custom analog cells, and so on. In addition, analog circuitry or mixed-signal circuitry, or both, may be included as desired, for example, power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), and the like. The analog circuitry may include, as desired and understood by those of ordinary skill in the art, biasing circuits, decoupling circuits, coupling circuits, supply circuits, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, converters, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, and the like. The mixed-signal circuitry may include, in addition to the analog circuitry and digital circuitry described above, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc., as will be appreciated by those of ordinary skill in the art. The choice of circuitry for a given implementation depends on a variety of factors, as will be appreciated by those of ordinary skill in the art. These factors include design specifications, performance specifications, cost, IC or device area, available technology such as semiconductor manufacturing technology, target markets, target end users, etc.

Various circuits and blocks, including the analog circuitry described above and used in example embodiments, may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, the LNA 15, the mixer 20, and the PGA 30 can generally be implemented using analog circuitry. The analog circuitry may include, as desired and understood by those of ordinary skill in the art, biasing circuits, decoupling circuits, coupling circuits, supply circuits, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), sensors or detectors, converters, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, and the like. Digital circuitry or mixed signal circuitry or both may also be included. The digital circuitry can be circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (eg, field programmable gate arrays (FPGAs), or other types as desired and understood by those of ordinary skill in the art of programmable logic), arithmetic logic units (ALUs), standard cells, custom cells, custom analog cells, and so on. The mixed-signal circuitry, in addition to analog circuitry and digital circuitry as described above, may include analog-to-digital converters (ADCs), digital/A analog converters (DACs), etc., as will be understood by those of ordinary skill in the art. The choice of circuitry for a given implementation depends on a variety of factors, as will be appreciated by those of ordinary skill in the art. These factors include design specifications, performance specifications, cost, IC or device area, available technology such as semiconductor manufacturing technology, target markets, target end users, etc.

Referring to the figures, those of ordinary skill in the art will recognize that the various blocks shown primarily represent the conceptual functions and signal flow. The actual implementation of the circuit may or may not include separately identifiable hardware for the various functional blocks, and may or may not use the particular circuitry shown. For example, one could combine the functionality of different blocks into one circuit block as desired. In addition, one can implement the functionality of a single block in multiple circuit blocks as desired. The choice of circuit implementation depends on various factors such as certain design and performance specifications for a given implementation. Modifications and alternative embodiments other than the embodiments in the disclosure will be apparent to those of ordinary skill in the art. Accordingly, the disclosure teaches those skilled in the art how to implement the disclosed concepts through exemplary embodiments and is to be considered illustrative only. As will be appreciated by those of ordinary skill in the art, the figures may or may not be drawn to scale where appropriate.

The particular shapes and embodiments shown and described are merely exemplary embodiments. Various changes in shape, size, and arrangement of parts can be made by those skilled in the art without departing from the scope of the disclosure. For example, those skilled in the art may substitute equivalent elements for elements shown and described. Moreover, those skilled in the art may use certain features of the disclosed concepts independently of using other features without departing from the scope of the disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US 17/138850 [0001]
• US 14/080405 [0015]
• US10061740 [0015]
• US 16/177373 [0015, 0056]
• US 15370693 [0015]
• US10389482 [0015]
• US 15/370674 [0056]
• US10469112 [0058]

Claims (20)

device comprising a radio frequency (RF) receiver for receiving RF signals, the RF receiver multiple modulation signal detectors (MSDs) to provide multiple detection signals generate when multiple RF signals modulated using multiple modulation schemes are detected; and a controller, responsive to the plurality of detection signals, for receiving which causes multiple RF signals having. device after claim 1 , wherein the multiple MSDs have multiple preamble detectors. device after claim 1 or 2 , wherein the plurality of MSDs comprises a plurality of sync word detectors (synch word detectors). Apparatus according to any preceding claim, wherein the multiple MSDs operate simultaneously to detect multiple different physical layers (PHYs). Apparatus according to any preceding claim, wherein the multiple MSDs operate simultaneously to detect the multiple RF signals modulated using multiple modulation schemes. Apparatus according to any preceding claim, wherein the controller uses multiple demodulators to cause reception of the multiple RF signals. Apparatus according to any preceding claim, wherein the controller configures the RF receiver based on the plurality of detection signals. Apparatus according to any preceding claim, wherein the controller comprises a media access control (MAC) processor shared to receive the plurality of RF signals modulated using the plurality of modulation schemes. Apparatus according to any preceding claim, wherein the plurality of modulation schemes are at least one of frequency shift keying (FSK), M-ary FSK, M-ary PSK, on/off sampling (OOK), amplitude shift keying (ASK), der quadrature phase shift keying (QPSK), offset quadrature phase shift keying (O-QPSK), binary phase shift keying (BPSK), 1/4π-QPSK, quadrature amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and chirp frequency spread (CSS). A device for communication using RF signals, the device: a transmitter for transmitting a modulated RF signal, the transmitted information being modulated onto the modulated RF signal using one of a plurality of modulation schemes; and a receiver for receiving packets of received modulated RF signals, the receiver having a plurality of modulation scheme detectors (MSDs) to generate a plurality of detection signals, wherein a packet is received by configuring the receiver based on a detection signal among the plurality of detection signals, the detection signal received from the package. device after claim 10 , comprising a controller to configure the receiver to receive signals modulated using the plurality of modulation schemes based on the plurality of detection signals. device after claim 10 or 11 wherein the plurality of MSDs detect the modulation schemes of received modulated RF signals during a preamble, a synchronization field, a start of a frame delimiter (SFD), a short training field (STF), or a long training field (LTF), or a combination thereof. Device according to any of the foregoing Claims 10 until 12 , further comprising a media access control (MAC) processor for processing shared MAC functions to receive packets from received modulated RF signals. Device according to one of the preceding Claims 10 until 13 wherein the plurality of modulation schemes are at least one of frequency shift keying (FSK), M-ary FSK, M-ary PSK, on/off sampling (OOK), amplitude shift keying (ASK), quadrature phase shift keying (QPSK), der offset quadrature phase shift keying (O-QPSK), binary phase shift keying (BPSK), 1/4π-QPSK, quadrature amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and chirp frequency spread (CSS). A method of operating a radio frequency (RF) receiver for receiving RF signals, the method generating multiple detection signals using multiple modulation signal detectors (MSDs) when multiple RF signals modulated using multiple modulation schemes are detected; and causing reception of the plurality of RF signals in response to the plurality of detection signals. procedure after claim 15 wherein using multiple MSDs includes using multiple preamble detectors or multiple sync word detectors (synch word detectors). procedure after claim 15 or 16 comprising operating the multiple MSDs concurrently to detect multiple different physical layers (PHYs). Method according to any of the preceding Claims 15 until 17 , comprising operating the multiple MSDs simultaneously to detect the multiple RF signals modulated using multiple modulation schemes. Method according to any of the preceding Claims 15 until 18 , comprising configuring the RF receiver to receive an RF signal among the plurality of RF signals based on a modulation scheme used to modulate the RF signal. Method according to any of the preceding Claims 15 until 19 , comprising sharing a media access control (MAC) processor to receive the plurality of RF signals modulated using the plurality of modulation schemes.

Images