DE102021002725A1 - Process for the production of capacitive synaptic components - Google Patents

Abstract

The present invention relates to a method for producing a capacitive synaptic component, which consists of a layer structure with a readout electrode, a buried insulation layer, a shielding layer, a storage dielectric and a gate electrode.

Description

The present invention relates to a method for producing a capacitive synaptic component, which consists of a layer structure with a readout electrode, a buried insulation layer, a shielding layer, a storage dielectric and a gate electrode.

A capacitive synaptic component is understood to mean a component for weighted multiplication in artificial neural networks, which component is based on a capacitive principle.

Artificial neural networks have gained increasing importance in image and object recognition and data processing in recent years and will have an important relevance in the implementation of artificial intelligence in the future.

In artificial neural networks, the outputs of artificial neurons are connected to inputs of other artificial neurons via synaptic connections. The synaptic connections effect a weighted multiplication with the output signals of the artificial pre-neurons.

For physical implementation, resistive components such as memristors ( US20180019011A1 ), phase change memory or floating gate transistors are used. Equally conceivable is the use of memcapacitive components ( US20120014170A1 , WO2011025495A1 , DE102014105639B3 , US5524092A1 , US2019303744A1 , Ventra et al.: Circuit elements with memory- memristors, memcapacitors, and meminductors, Proceedings of the IEEE), which have the advantage of lower static power consumption and dynamic losses can be largely eliminated with adiabatic charging.

In WO002018069359A1 a favorable arrangement for achieving a high lift ratio has already been described, which consists of a storage dielectric, a gate electrode, a shielding layer, a semiconductor, a buried insulator and a lower readout electrode. This matrix arrangement consists of many capacitive synaptic components at the crossing points.

In US6586284 and US6627519 manufacturing processes for the production of silicon-on-insulator substrates have already been presented.

Also known ( US4859617 , US20090004788A1 ) are manufacturing processes for the fabrication of thin-film transistors for displays using amorphous silicon or polycrystalline silicon.

The object of this invention was a manufacturing process for the WO002018069359A1 to develop the capacitive synaptic component described at the crossing points, thereby enabling simple integration into a CMOS process.

According to the invention, this object is achieved according to a method of claim 1. Embodiments of this are presented in dependent claims 2-11.

• - in einer ersten Ausführungsform ein beliebiges Substrat benutzt wird, und zunächst die rückseitige Ausleseelektrode entweder abgeschieden oder durch Ionenimplantation in einem Halbleiter generiert wird, als zweites eine vergrabene Isolatorschicht abgeschieden wird, als drittes die Abschirmschicht als amorpher, polykristalliner oder einkristalliner Halbleiter abgeschieden oder gebonded wird, als viertes das Speicherdielektrikum abgeschieden wird und als letztes die Gateelektrode,
• - in einer zweiten Ausführungsform, ein Silizium-auf-Isolator Substrat benutzt wird, und als erstes die rückseitige Ausleseelektrode mittels Ionenimplantation in das untere Siliziumsubtrat durchimplantiert wird, anschließend das Speicherdielektrikum abgeschieden wird und als letztes die Gateelektrode abgeschieden wird.

A method of the type mentioned is designed according to the invention in that

• - In a first embodiment, any substrate is used, and first the rear readout electrode is either deposited or generated by ion implantation in a semiconductor, secondly a buried insulator layer is deposited, thirdly the shielding layer is deposited or bonded as an amorphous, polycrystalline or monocrystalline semiconductor , the storage dielectric is deposited fourth and the gate electrode last,
• - In a second embodiment, a silicon-on-insulator substrate is used, and first the backside readout electrode is implanted through into the lower silicon substrate by means of ion implantation, then the storage dielectric is deposited and lastly the gate electrode is deposited.

Accordingly, the in WO002018069359A1 The layer structure described is either grown one after the other, whereby the shielding layer can also be bonded as a semiconductor, or an SOI (silicon-on-insulator) wafer is taken directly as the basis for generating the layer structure. In both cases, the readout electrode can be produced either in a semiconductor by doping (ion implantation) or by deposition of a conductive material.

In a further embodiment, the rear readout electrode is structured directly after the deposition or during the implantation, the shielding layer is structured together with the buried insulator layer and the gate electrode is structured last.

In a further embodiment, the layers are all deposited and at the end the gate electrode is first structured together with the storage dielectric and then the Shielding layer structured together with the buried insulator layer and the sense electrode, or in reverse order. This embodiment has the advantage that fewer masks are required to produce the component.

The buried insulation layer can either be deposited at high temperature by means of chemical vapor deposition and then annealed at 900° C. to 1100° C., or grown thermally. Deposition by means of chemical vapor deposition has the advantage that defects can be reduced in comparison to thermal growth.

The shielding layer can first be deposited as amorphous silicon at a maximum of 510° C. to 560° C. and then nucleation takes place at 450° C. to 650° C. and nucleus growth at 800° C. to 950° C. The advantage of this procedure is that the polycrystalline silicon has large grains and the roughness is kept low. Furthermore, twin dislocations are healed by the 800°C to 950°C step.

In a further embodiment, the buried insulator layer consists of a material with an increased dielectric constant, for example silicon nitride, hafnium dioxide or titanium dioxide. This ensures that the capacitive coupling can be increased. The materials described are all CMOS compatible.

In one embodiment, after the deposition and structuring of the gate electrode, lateral p- and n-doped regions are implanted into the shielding layer and the implantation mask ends in the middle of the gate electrode. The p- and n-areas on the side have the advantage of a further modulation possibility and enable a symmetrical control of the component. With the method described here, a self-aligning method can be used, as is customary in the manufacture of transistors, despite asymmetric doping.

In a further embodiment, the deposition, structuring of the gate electrode and the implantation of the lateral p and n regions take place in accordance with a CMOS part and with it at the same time. This ensures that the readout electrode, the buried insulation layer and the shielding layer are deposited before the CMOS transistors are manufactured, and that the p and n regions, the source and drain regions are designed accordingly. The gate electrodes of the CMOS part and the capacitive synaptic component have the same design. This process ensures a high level of CMOS compatibility despite front-end-of-line (FEOL) integration.

Another way to achieve CMOS compatibility is that the material is deposited after the high-temperature processes but before the metallization levels, and the amorphous silicon of the shielding layer is recrystallized and activated together with the doping at 450°C to 650°C at the end. The temperature is limited to a maximum of 650°C, which no longer affects the FEOL CMOS part. Since amorphous silicon is implanted, the activation of the dopants occurs together with the recrystallization of the amorphous silicon.

A complete back-end-of-line (BEOL) integration can be achieved by depositing the layers: readout electrode, buried insulator layer, shielding layer, storage dielectric and gate electrode using atomic layer deposition at low temperature (<400°C).

In one embodiment, the sense electrode and gate electrode are made of titanium nitride and the shielding layer is made of a semiconducting oxide, for example titanium dioxide, indium gallium zinc oxide or strontium titanate. With TiN, on the one hand, a very high conductivity is achieved, on the other hand, the material is very well compatible with CMOS, as well as with other oxides. Producing the shielding layer from semiconducting oxides has the advantage that, on the one hand, the deposition temperature is reduced and, on the other hand, greater endurance can be achieved with the storage material.

• 1: Ablaufschema der Abscheidungen und Strukturierung der Schichten auf einem beliebigen Substrat, wobei die Ausleseelektrode entweder implantiert oder abgeschieden wird.
• 2: Ablaufschema der Abscheidungen und Strukturierung der Schichten auf einem Silizium-auf-Isolator Substrat.
• 3: Abscheidung aller Schichten, und anschließende Strukturierung.
• 4: Generierung der seitlichen p- und n-dotierten Gebiete.
• 5: Integration mit dem CMOS Teil zusammen.

The invention will be explained in more detail below using several exemplary embodiments. The accompanying drawings show:

• 1 : Flow chart of the depositions and structuring of the layers on any substrate, whereby the readout electrode is either implanted or deposited.
• 2 : Flow chart of the deposition and structuring of the layers on a silicon-on-insulator substrate.
• 3 : Deposition of all layers, and subsequent structuring.
• 4 : Generation of the lateral p- and n-doped regions.
• 5 : Integration with the CMOS part together.

As in 1 shown, the manufacturing process is divided into two paths: either the readout electrode (2) is implanted in any substrate (1) or deposited. In this case, the readout electrode is connected directly to the implantation or structured after deposition. The further process consists of the deposition of the buried insulation layer (3) and the shielding layer (4), both being structured together. This is followed by the deposition of the storage dielectric (5) and the gate electrode (6), as well as the structuring in each case.

In 2 a production method in the case of a silicon-on-insulator substrate (7) is shown. In this case, the readout electrode (2) is implanted in the lower silicon substrate (8) and is also structured in the process. The shielding layer (4) and the buried insulating layer (3) are already present on the silicon-on-insulator substrate (7). In the further course, the storage dielectric (5) is deposited and all layers are structured. Finally, the gate electrode (6) follows.

In 3 the 5-mentioned layers are deposited first and then the storage dielectric (5) is structured together with the gate electrode (6). At the end, the shielding layer (4) is structured together with the buried insulation layer (3) and the readout electrode (2). The advantage of this procedure is that significantly fewer lithography steps are necessary.

In 4 lateral p (10) - and n (11) - areas in the shielding layer (4) through a resist mask (9), which ends in the middle of the gate, generated by implantation. In this way, a self-aligning process is possible despite asymmetric doping.

5 shows the integration of the component together with the CMOS part (12): Here, the readout electrode (2), the buried insulation layer (3) and the shielding layer (4) are deposited and structured in front of the CMOS part (12). If necessary, the trench insulation (swallow trench insulation) is created at the very beginning. The structuring and deposition of the gate electrode (6) takes place together with the CMOS part (12). The p(10) and n(11) regions are implanted together with the source/drain regions of the PMOS or NMOS transistor.

Reference List

1

any substrate

2

readout electrode

3

buried insulation layer

4

shielding layer

5

storage dielectric

6

gate electrode

7

silicon-on-insulator substrate

8th

lower silicon substrate

9

paint mask

10

p area

11

n area

12

CMOS part

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US20180019011A1 [0005]
• US20120014170A1[0005]
• WO 2011025495 A1 [0005]
• DE 102014105639 B3 [0005]
• US 5524092 A1 [0005]
• US2019303744A1 [0005]
• WO 002018069359 A1 [0006, 0009, 0012]
• US6586284 [0007]
• US6627519 [0007]
• US4859617 [0008]
• US20090004788A1 [0008]

Claims (11)

Method for producing a capacitive synaptic component, characterized in that - in a first embodiment, any desired substrate (1) is used, and first the rear readout electrode (2) is either deposited or generated by ion implantation in a semiconductor, secondly a buried insulator layer (3) is deposited, thirdly the shielding layer (4) is deposited or bonded as an amorphous, polycrystalline or monocrystalline semiconductor, fourthly the storage dielectric (5) is deposited and finally the gate electrode (6), - in a second embodiment a silicon -on-insulator substrate (7) is used, and first the rear readout electrode (2) is implanted through into the lower silicon substrate (8) by means of ion implantation, then the storage dielectric (5) is deposited and finally the gate electrode (6) is deposited . procedure after claim 1 , characterized in that the rear readout electrode (2) is structured directly after the deposition or during the implantation, the shielding layer (3) is structured together with the buried insulator layer (4) and the gate electrode (6) is structured last. procedure after claim 1 , characterized in that the layers are all deposited and at the end first the gate electrode (6) is structured together with the storage dielectric (5) and then the shielding layer (4) is structured together with the buried insulator layer (3) and the readout electrode (2). will, or in reverse order. procedure after claim 1 , characterized in that the buried insulator layer (3) is either deposited at high temperature by means of chemical vapor deposition and then annealed at 900°C to 1100°C, or is grown thermally. procedure after claim 1 , characterized in that the shielding layer (4) is first deposited as amorphous silicon at a maximum of 510°C to 560°C and then nucleation takes place at 450°C to 650°C and nucleus growth at 800°C to 950°C. procedure after claim 1 , characterized in that the buried insulator layer (3) consists of a material with an increased dielectric constant, for example silicon nitride, hafnium dioxide or titanium dioxide. procedure after claim 1 , characterized in that after the deposition and structuring of the gate electrode (6), lateral p- (10) and n- (11) doped areas are implanted in the shielding layer (4) and the implantation mask (9) on the gate electrode (6) middle ends. procedure after claim 1 and 7 , characterized in that the deposition, structuring of the gate electrode (6) and the implantation of the lateral p- (10) and n- (11) regions is carried out in accordance with a CMOS part (12) and takes place simultaneously with it. procedure after claim 1 , characterized in that the material is deposited after the high-temperature processes but before the metallization levels, and the amorphous silicon of the shielding layer (3) is recrystallized and activated together with the doping at 450°C to 650°C at the end. procedure after claim 1 , characterized in that the layers: readout electrode (2), buried insulator layer (3), shielding layer (4), storage dielectric (5) and gate electrode (6) are deposited by means of atomic layer deposition at low temperature (<400°C). procedure after claim 1 , characterized in that the readout electrode (2) and gate electrode (6) consists of titanium nitride and the shielding layer (4) consists of a semiconducting oxide, for example titanium dioxide, indium gallium zinc oxide or strontium titanate.

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