DE102017117801B4 - METHOD FOR DESIGNING A LAYOUT FOR A SEMICONDUCTOR DEVICE, MACHINE READABLE MEDIA WITH MACHINE READABLE INSTRUCTIONS FOR PERFORMING A METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Google Patents

Abstract

A method of designing, for a semiconductor device, a layout having spare unprogrammed standard cells, comprising the steps of:
generating (602), based on a first grid spacing (P _STRAP ) of bridge lines of a metallization layer, a set of possible values for a second grid spacing (P _SPARE ) of unprogrammed spare standard cells;
choosing (604) a member of the set of possible values as the second grid spacing (P _SPARE );
placing (606) unprogrammed spare standard cells in a logic area (904) of the layout corresponding to the second pitch (P _SPARE ), and reserving (608), in each spare standard cell, a reserved portion over which one or more bridge lines are fabricated with each reserved part passing over the reserve standard cell; wherein at least one of creating, selecting and placing is performed by a processor of a computer.

Description

Background of the Invention

An integrated circuit (IC) includes a number of electronic components. One way to represent the IC is with a layout diagram (hereafter "layout"). A layout is hierarchical and broken down into modules that perform high-level functions required by IC design specifications. In an SCD project (SCD: semicustom design; universal design), the modules may be broken down into macro cells, standard cells and customer-specific cells.

For a given SCD project, a custom cell is designed with an arrangement specific to the given SCD project to provide (in operation) a high level logical function specific to the SCD project. In contrast, a library of standard cells is designed without regard to a particular project, and includes standard cells that provide (in use) common ancillary logic functions. In terms of footprint in a layout, custom cells are larger (usually much larger) than standard cells. In addition, for a given library, all standard cells have at least one dimension that is the same size (usually the size being a multiple of a library-specific fixed dimension) to facilitate placement of the standard cells in a layout. As such, standard cells are referred to as cells that are predefined for a given SCD project. Custom cells may or may not have at least one dimension that is the same size as the corresponding standard cell dimension.

A method according to for designing a layout for a semiconductor device having reserve standard cells is known from US Pat U.S. 2010/0162187 A1 known. Another method is from US 2002/0005699 A1 known.

Summary of the Invention

The present invention relates to a method according to claim 1 for designing, for a semiconductor device, a layout that has unprogrammed spare standard cells, a machine-readable medium according to claim 9 with machine-readable instructions for executing a method for designing a semiconductor device and a semiconductor device according to claim 14. Preferred embodiments are given in the dependent claims.

character list

• 1A ist ein Layout, für ein Halbleiter-Bauelement, von ECO-Basiszellen (ECO: technische Änderungsanweisung) in Bezug zu Leitungssegmenten, gemäß einigen Ausführungsformen.
• 1B ist ein Layout, das dem Layout von 1A entspricht, der Zuweisung von Metallisierungssegmenten zu entsprechenden Maskierungsstrukturen/-farben, gemäß einigen Ausführungsformen.
• 1C ist ein Layout, das dem Layout von 1A entspricht, von reservierten Bereichen in den ECO-Basiszellen, gemäß einigen Ausführungsformen.
• 2 ist ein Layout, für ein Halbleiter-Bauelement, von reservierten Bereichen in den ECO-Basiszellen, gemäß einigen Ausführungsformen.
• 3A ist ein weiteres Layout, für ein Halbleiter-Bauelement, von reservierten Bereichen in den ECO-Basiszellen, gemäß einigen Ausführungsformen.
• 3B ist eine vereinfachte Variante des Layouts von 3A, gemäß einigen Ausführungsformen.
• 3C ist eine weitere vereinfachte Variante des Layouts von 3A, gemäß einigen Ausführungsformen.
• 4A ist ein Layout, für ein Halbleiter-Bauelement, von ECO-Basiszellen in Bezug zu Leitungssegmenten, gemäß einigen Ausführungsformen.
• 4B ist eine vereinfachte Variante des Layouts von 4A, gemäß einigen Ausführungsformen.
• 4C ist eine weitere vereinfachte Variante des Layouts von 4A, gemäß einigen Ausführungsformen.
• 5A ist ein Layout, für ein Halbleiter-Bauelement, von ECO-Basiszellen in Bezug zu Leitungssegmenten, gemäß einigen Ausführungsformen.
• 5B ist eine vereinfachte Variante des Layouts von 5A, gemäß einigen Ausführungsformen.
• 5C ist eine weitere vereinfachte Variante des Layouts von 5A, gemäß einigen Ausführungsformen.
• 6A ist ein Ablaufdiagramm eines Verfahrens zum Entwerfen, für ein Halbleiter-Bauelement, eines Layouts, gemäß einigen Ausführungsformen.
• 6B ist eine detaillierte Darstellung eines Blocks in dem Ablaufdiagramm von 6A, gemäß einigen Ausführungsformen.
• 6C ist eine detaillierte Darstellung eines weiteren Blocks in dem Ablaufdiagramm von 6A, gemäß einigen Ausführungsformen.
• 6D ist eine detaillierte Darstellung eines weiteren Blocks in dem Ablaufdiagramm von 6A, gemäß einigen Ausführungsformen.
• 7A ist ein Ablaufdiagramm eines Verfahrens zum Entwerfen, für ein Halbleiter-Bauelement, eines Layouts, gemäß einigen Ausführungsformen.
• 7B ist eine detaillierte Darstellung eines Blocks in dem Ablaufdiagramm von 7A, gemäß einigen Ausführungsformen.
• 7C ist eine detaillierte Darstellung eines weiteren Blocks in dem Ablaufdiagramm von 7A, gemäß einigen Ausführungsformen.
• 8 ist ein Ablaufdiagramm eines Verfahrens zum Entwerfen, für ein Halbleiter-Bauelement, eines Layouts, gemäß einigen Ausführungsformen.
• 9A ist eine schematische Darstellung eines Halbleiter-Bauelements, gemäß einigen Ausführungsformen.
• 9B ist eine schematische Darstellung des Halbleiter-Bauelements von 9A, das mit einer oder mehreren programmierten ECO-Zellen abgeändert ist, gemäß einigen Ausführungsformen.
• 10 ist ein Ablaufdiagramm eines Verfahrens zur Herstellung eines Halbleiter-Bauelements, gemäß einigen Ausführungsformen.
• 11 ist ein Blockdiagramm eines EDA-Systems gemäß einigen Ausführungsformen.

Aspects of the present invention are best understood by considering the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

• 1A 14 is a layout, for a semiconductor device, of basic ECO cells (ECO: technical change instruction) in relation to line segments, according to some embodiments.
• 1B is a layout similar to the layout of 1A corresponds to the assignment of metallization segments to corresponding masking patterns/colors, according to some embodiments.
• 1C is a layout similar to the layout of 1A corresponds to reserved areas in the ECO basic cells, according to some embodiments.
• 2 12 is a layout, for a semiconductor device, of reserved areas in the ECO basic cells, according to some embodiments.
• 3A 12 is another layout, for a semiconductor device, of reserved areas in the ECO basic cells, according to some embodiments.
• 3B is a simplified variant of the layout of 3A , according to some embodiments.
• 3C is another simplified variant of the layout of 3A , according to some embodiments.
• 4A 14 is a layout, for a semiconductor device, of basic ECO cells in relation to line segments, according to some embodiments.
• 4B is a simplified variant of the layout of 4A , according to some embodiments.
• 4C is another simplified variant of the layout of 4A , according to some embodiments.
• 5A 14 is a layout, for a semiconductor device, of basic ECO cells in relation to line segments, according to some embodiments.
• 5B is a simplified variant of the layout of 5A , according to some embodiments.
• 5C is another simplified variant of the layout of 5A , according to some embodiments.
• 6A 12 is a flow diagram of a method for designing a layout for a semiconductor device, according to some embodiments.
• 6B FIG. 12 is a detailed representation of a block in the flow chart of FIG 6A , according to some embodiments.
• 6C FIG. 12 is a detailed representation of another block in the flow chart of FIG 6A , according to some embodiments.
• 6D FIG. 12 is a detailed representation of another block in the flow chart of FIG 6A , according to some embodiments.
• 7A 12 is a flow diagram of a method for designing a layout for a semiconductor device, according to some embodiments.
• 7B FIG. 12 is a detailed representation of a block in the flow chart of FIG 7A , according to some embodiments.
• 7C FIG. 12 is a detailed representation of another block in the flow chart of FIG 7A , according to some embodiments.
• 8th 12 is a flow diagram of a method for designing a layout for a semiconductor device, according to some embodiments.
• 9A 1 is a schematic representation of a semiconductor device, according to some embodiments.
• 9B 12 is a schematic representation of the semiconductor device of FIG 9A , modified with one or more programmed ECO cells, according to some embodiments.
• 10 FIG. 12 is a flow chart of a method of manufacturing a semiconductor device, according to some embodiments.
• 11 12 is a block diagram of an EDA system, according to some embodiments.

Detailed description

The description below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, processes, configurations, or the like are described below in order to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are also contemplated. For example, the fabrication of a first member over or on a second member in the description below may include embodiments where the first and second members are formed in direct contact, and may also include embodiments where additional members are formed between the first and the second element can be formed such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numbers and/or letters may be repeated in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of reference describing the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative descriptors used herein interpreted accordingly as well.

When placing ECO basic cells in a row of a layout, by minimizing gaps between adjacent ECO basic cells, useless space is reduced and density (expressed as the number of devices per cell) is increased. In addition, the placement of ECO basic cells in a row of a layout is simplified if the ECO basic cells have not only a fixed height but also a fixed width. In some embodiments, the gaps are reduced and the placement of ECO basic cells in a row is simplified by using a pitch P _ECOB (or P _SPARE ) of ECO basic cells that is evenly spaced into a pitch P _M1-STRAP of M1 bridges can be subdivided. In some embodiments, a bridge includes one or more segments in a metallization layer, the one Conduct operating voltage, e.g. B. VDD, VSS or the like. The first metallization layer is referred to as M1. Thus, a bridge in the M1 layer is an M1 bridge. In order to eliminate the gaps between adjacent ECO basic cells (to achieve contiguity) when placing ECO basic cells in a row, in some embodiments the pitch P _ECOB of the ECO basic cells is chosen to correspond to the even/odd -Status (parity status) of the number CLR of masking structures/colors matches.

In addition to standard cells and customer-specific cells, macro cells can also be used within an SCD project (SCD: Universal Design). Similar to custom cells, macro cells offer higher function than standard cells. However, similar to standard cells, macro cells are designed without any special project in mind. Therefore, macrocells are designed with an arrangement that provides an overriding function that is common, e.g. B. RAM, ROM, serial port, ALE processor core or the like. Macro cells, which have a higher function, take up a larger connection area. Therefore, macro cells have a much larger footprint than standard cells. Some macro cells are arrays of standard cells.

Also similar to custom cells, macro cells do not have at least one dimension that is the same size as the corresponding dimension of standard cells. For this reason, macro cells and custom cells are referred to as non-standard cells.

There are two types of standard cells, functional standard cells and reserve standard cells, the latter being referred to as ECO cells (ECO: Technical Change Instruction). Functional standard cells are defined with specific internal arrangements of components to provide (in use) corresponding common ancillary functions, e.g. B. Logic functions that include an inverter, NAND, NOR, XOR, D-Latch, decoupling capacitor (DeCap), AND-OR-Invert (AOI), OR-AND-Invert (OAI), multiplexer, flip-flop or the like.

ECO cells include ECO basic cells and programmed ECO cells. A programmed ECO cell refers to a basic ECO cell that has been programmed. Similar to a functional cell, a basic ECO cell is defined with a specific internal arrangement of components. Unlike a functional cell, a basic ECO cell is not set up to provide a specific function. Unlike standard cells that work (are operational), a basic ECO cell (which has not yet been programmed) does not work (it is not operational).

Bearing in mind that basic ECO cells are reserve cells, the placement of a basic ECO cell is sufficient as it can be “programmed” (transformed) when needed to operate and provide any of the same common ancillary functions as those provided by a corresponding functional standard cell can be provided. In some embodiments, the arrangement of an ECO basic cell is sufficient to be able to "program" (transform) it to operate and provide any of the logic functions that are an inverter, NAND, NOR, XOR, D-latch, decoupling capacitor ( DeCap), AND-OR-Invert (AOI), OR-AND-Invert (OAI), multiplexer, flip-flop or the like. In some embodiments, a basic ECO cell is programmed (transformed) into a programmed ECO cell by making one or more connections in at least one basic ECO cell (internal basic ECO cell connections), such as metal-silicon contacts and metal-polysilicon -Contacts are changed or other metal layer changes are made with appropriate vias or contacts.

In an SCD project, EDA (Electronic Systems Design Automation) tools are used to select functional standard cells from standard cell libraries and to place the functional standard cells (if any) along with non-standard cells in a first layout. EDA tools are also used to perform the routing that connects the functional standard cells and the non-standard cells using one or more metal layers and corresponding vias and contacts. EDA tools are also used to verify the route. Depending on the test results, the selection, placement and routing of the standard and non-standard cells are revised. In at least some embodiments, the entire selection, placement, routing, and verification (SPRT) process is iterative. Eventually, the SPRT process iterations converge into a completed layout.

For various reasons (e.g., because of a design change, an unacceptable timing issue, an unacceptable electromigration issue, or the like), a near-completed layout (or a layout that would otherwise have been considered a final layout) usually needs to undergo a rework. in anticipation of circumstances, where the revision would be relatively small in scope, and as a safeguard (or safeguard) against having to restart (start again) the iterative SPRT process, EDA tools are also used to place one or more ECO base cells into the first layout used.

Since the ECO basic cells are not working, they are not connected to functional cells. When the nearly completed layout is to be revised, one or more ECO base cells undergo "programming" in which the one or more ECO base cells are converted into one or more "programmed" ECO cells. Then the programmed ECO cell is traced in such a way that it is functionally connected to one or more functional standard cells. In some embodiments, ECO base cells correspond to the ECO base cells disclosed in US patent issued November 14, 2006 U.S. 7,137,094 B2 are described. In some embodiments, ECO base cells correspond to the ECO base cells described in US patent issued November 25, 2008 U.S. 7,458,051 B2 are described.

1A FIG. 100A is a layout 100A, for a semiconductor device, of basic ECO cells in relation to line segments in an i-th metallization layer M(i), according to some embodiments.

In some embodiments, the M(i) layer is M1. In the 1A until 1C is M(i) M1.

In 1A the layout 100A is a layout of a semiconductor device having an IC fabricated on a substrate 102 . The substrate 102 has a logic area 104 in which functional standard cells (not shown) and standard ECO basic cells are fabricated. As shown, logic area 104 includes basic ECO cells 106A-106F, 108A, 110A-110F, 112A, 114A-114F, and 116A. Other numbers of ECO base cells are also contemplated. For the sake of simplicity, an ECO basic cell is in 1A represented by their borders. For simplicity of illustration, components and internal ECO base cell connections of each ECO base cell are not shown.

As discussed above, for a given library, all standard cells have at least one dimension that is the same fixed size to aid in the placement of the standard cells in a layout. In some embodiments, the fixed size is a multiple of a library-specific fixed dimension. In some embodiments, the fixed size is a multiple of the minimum spacing P _POLY between polysilicon features.

In some embodiments, the standard cells (which include functional cells and ECO cells) are polygons. In some embodiments, the default cells are rectangular polygons. In some embodiments, from a top view perspective, the x-axis is horizontal and the y-axis is vertical, such that the horizontal and vertical dimensions of a standard rectangular cell are referred to as the cell's corresponding width and height, respectively. In some embodiments, the layout is arranged in rows and the height of all standard cells is the same to help place the standard cells in the rows of the layout.

We come to 1A 106A to 106F and 108A are arranged in the horizontal direction and placed in a first row 118A. The ECO basic cells 110A to 110F and 112A are arranged in the horizontal direction and are placed in a second row 118B. The ECO basic cells 114A to 114F and 116A are arranged in the horizontal direction and are placed in a third row 118C. All of the ECO basic cells 106A to 106F, 108A, 110A to 110F, 112A, 114A to 114F and 116A have the same size in the vertical direction (the same height). However, other configurations are within the scope of the present invention. In the first row 118A, adjacent ones of the ECO basic cells 106A to 106F and 108A horizontally adjoin each other. In particular, in the first row 118A, ECO basic cell 106A borders ECO basic cell 106B, ECO basic cell 106B borders ECO basic cell 106C, and so on. In the second row 118B, adjacent ones of the ECO basic cells 110A to 110F and 112A horizontally adjoin each other. In particular, basic ECO cell 110A borders basic ECO cell 110B, basic ECO cell 110B borders basic ECO cell 110C, and so on. In the third row 118C, adjacent ones of the ECO basic cells 114A to 114F and 116A horizontally adjoin each other. In particular, ECO base cell 114A is adjacent to ECO base cell 114B, ECO base cell 114B is adjacent to ECO base cell 114C, and so on.

To enable connections between cells, a layout comprises a stack of planar "metallization" layers interspersed with planar interlayer dielectric (ILD) structures. A given "metallization" layer has parallel conductive line segments. In some embodiments, the conductive line segments are made of metal. In some embodiments, the parallel line segments are in sequential metallization layers perpendicular to each other. In some embodiments, the parallel line segments in an i th metallization layer [M(i)] run in a first direction, the parallel line segments in an (i+1) th metallization layer [M(i+1)] run in a second direction which is perpendicular to the first direction, the parallel line segments in an (i+2)th metallization layer [M(i+2)] run in the first direction, the parallel line segments in an (i+3)th metallization layer [ M(i+3)] run in the second direction, and so on. In some embodiments, the first direction is parallel to the x-axis and the second direction is parallel to the y-axis.

In some embodiments, the segments of the i th metallization layer M(i) are regularly spaced from each other, referred to as the pitch P _MET-SEG (i) of the metallization segments. In some embodiments, the pitch P _MET-SEG (i) is a multiple of the minimum pitch P _POLY between polysilicon features.

An ILD structure enables a separation between a metallization layer fabricated on the ILD structure and another structure on which the ILD structure is fabricated. In some embodiments, the other structure is another layer of metallization. In some embodiments, the other structure is a silicon substrate, e.g. B. transistor components or the like. Therefore, a large part of an ILD structure is a dielectric material. If the ILD structure is fabricated under an M(i+1) layer, it is referred to as an ith ILD structure [ILD(i)].

To establish a connection between an M(i+1) segment (running in the first direction) in the M(i+1) layer and an M(i) segment (running in the second direction) in the M (i) layer, when the ILD(i) is sandwiched between the M(i+1) and M(i) layers, the ILD(i) also has contact/via structures that are formed in a third direction that is perpendicular to the first and the second direction. Similarly, when i=1, the ILDo is sandwiched between the M1 layer and the substrate. In order to establish a connection between an M1 segment and a component in the substrate, e.g. a transistor component or the like, the ILDo also has contact structures running in the third direction. In some embodiments, the third direction is parallel to the z-axis. In some embodiments, the M(i) layer is M1. In 1A is M(i) M1.

As discussed above, the basic ECO cells in the layout 100A of FIG 1A placed in relation to line segments in the M1 layer. Therefore shows 1A Mi line segments (M1 segments) as parallel rectangles 120A, 120B, 122A, 122B, and 124. For context, gate structures in layout 100A of FIG 1A shown as parallel rectangles 130A, 130B, and 132 interspersed with Mi segments 120A, 120B, 122A, 122B, and 124, respectively.

Note that not all of the Mi segments 120A, 120B, 122A, 122B, and 124, the multiple instances of the M1 segment 124, the gate structures 130A and 130B, and the multiple instances of the gate structure 132 are not necessarily preserved after the ECO base cells have been manufactured and/or after one or more of the ECO base cells have been programmed. For example, each of the Mi segments 120A, 120B, 122A and 122B and the gate structures 130A and 130B, each of the multiple instances of the M1 segment 124 and each of the multiple instances of the gate structure 132 has the potential, after fabrication of the ECO basic cells to remain. Therefore, it is contemplated that a given ECO base cell could have a different set of Mi segments and/or a different set of gate structures.

In some embodiments, the ECO base cells are first fabricated using a cut-last method, which involves fabricating all possible gate structures, removing (slicing) all or part of selected gate structures, fabricating all possible Mi-segments, and includes removing (clipping) all or part of selected Mi segments such that less than all of the multiple instances of M1 segment 124 and less than all of the multiple instances of gate structure 132 remain. In some embodiments, the ECO base cells are first fabricated using a cut-last method, which involves fabricating all possible Mi segments, removing (cutting) all or part of selected M1 segments, fabricating all possible gate structures, and includes removing (clipping) all or part of selected gate structures such that less than all of the multiple instances of M1 segment 124 and less than all of the multiple instances of gate structure 132 remain. In some embodiments, when programming an ECO base cell, one or more of the remaining multiple instances of M1 segment 124 are truncated, leaving even fewer instances of M1 segment 124.

The Mi segments 120A, 120B, 122A, 122B and 124 each have a shorter dimension parallel to the x-axis and a longer dimension parallel to the y-axis. Therefore, the longitudinal axis of each of Mi segments 120A, 120B, 122A, 122B, and 124 is considered to be an axis that intersects a corresponding one or more of rows 118A through 118C. Mi segments 120A, 120B, 122A, and 122B are each of sufficient length to span (perpendicularly) rows 118A through 118C. In contrast, each Mi segment 124 has a shorter length than Mi segments 120A, 120B, 122A and 122B. Corresponding Mi segments in the first line 118A, in the second line 118B and in the third line 118C are aligned in the vertical direction as represented by the phantom rectangle 126. FIG. Other horizontal dimensions and/or vertical dimensions for Mi segments 120A, 120B, 122A and 122B are also contemplated.

In some embodiments, each Mi segment 124 is of such a short length that it does not extend beyond a corresponding bottom and/or top edge of one or more of ECO base cells 106A-106F, 108A, 110A-110F, 112A, 114A-114F, and 116A in the vertical direction. In some embodiments, all Mi segments 124 are placed such that an imaginary horizontal reference line bisecting each Mi segment 124 is collinear with an imaginary reference line corresponding to one or more of the ECO base cells 106A-106F, 108A, 110A-110A 110F, 112A, 114A to 114F and 116A bisected. Other vertical positions for the Mi segments 124 with respect to one or more corresponding ECO base cells 106A-106F, 108A, 110A-110F, 112A, 114A-114F, and 116A are also contemplated. Other horizontal dimensions and/or vertical dimensions for the Mi segments 124 are also contemplated.

For context, gate structures 130A, 130B, and 132 in layout 100A of FIG 1A shown as parallel rectangles 130A, 130B and 132. Gate structures 130A, 130B and 132 each have a shorter dimension parallel to the x-axis and a longer dimension parallel to the y-axis. Therefore, the longitudinal axis of each of gate structures 130A, 130B, and 132 is considered to be an axis that intersects a corresponding one or more of rows 118A-118C. Gate structures 130A, 130B, and 132 are each of sufficient length to span (perpendicularly) rows 118A through 118C. In contrast, each gate structure 132 has a shorter length than gate structures 130A and 130B. Other vertical positions for the gate structures 132 with respect to one or more corresponding ECO base cells 106A-106F, 108A, 110A-110F, 112A, 114A-114F, and 116A are also contemplated. Other horizontal dimensions and/or vertical dimensions for the Mi segments 124 are also contemplated. Corresponding gate structures 132 in the first row 118A, the second row 118B, and the third row 118C are aligned in the vertical direction, as represented by a phantom rectangle 134. FIG.

In some embodiments, each Mi segment 124 has such a short length that it does not span one or more corresponding ECO base cells 106A-106F, 108A, 110A-110F, 112A, 114A-114F, and 116A in the vertical direction. In some embodiments, all Mi segments 124 are placed such that an imaginary horizontal reference line bisecting each Mi segment 124 is collinear with an imaginary reference line corresponding to one or more of the ECO base cells 106A-106F, 108A, 110A-110A 110F, 112A, 114A to 114F and 116A bisected. Other horizontal dimensions and/or vertical dimensions for gate structures 130A, 130B and 132 are also contemplated.

In some embodiments, when one or more ECO basic cells are programmed (transformed), the result is one or more correspondingly programmed ECO basic cells. Also as a result, the one or more internal ECO base cell connections that are altered as a result include at least one connection to a corresponding metallization segment in the M1 layer. In some embodiments, when a programmed ECO base cell is traced, one or more intercell connections are made between the programmed ECO base cell and one or more functional standard cells. At least one of the intercell connections is a connection to a Mi segment.

During global mapping, some of the line segments in the M1 layer are designated for use as bridges (M1 bridges). In some embodiments, some of the Mi bridges are connected to the power supply VDD. In some embodiments, some of the Mi bridges are connected to the common ground VSS. In some embodiments, the bridge segments span multiple rows in the layout.

In some embodiments, in a logic region of the layout, the Mi-Bridges are regularly spaced from each other, referred to as the Mi-Bridge _{pitch PM1-STRAP} . In some embodiments, the pitch P _M1-STRAP of the M1 bridge is a multiple of the pitch P _MET - _SEG of the metallization segments ment. In 1A For example, in logic area 104, Mi segments 120A, 120B, 122A, and 122B are provided for use as bridge segments. Therefore, Mi segments 120A and 120B represent a first bridge in M1 layer, and Mi segments 122A and 122B represent a second bridge in M1 layer 1A until 1C each bridge comprises two Mi segments, e.g. e.g., the first bridge includes Mi segments 120A and 120B, the second bridge includes Mi segments 122A and 122B, and the like. In some embodiments, other amounts of Mi segments are contemplated for use as bridge segments. In some embodiments, the first M1 bridge is connected to the line voltage VDD and the second M1 bridge is connected to the operational ground VSS.

In contrast, the multiple instances of the M1 segment 124 are intended for use as non-bridge segments. Recall that a bridge comprises one or more segments in a metallization layer that carry an operating voltage, e.g. B. VDD, VSS or the like. Thus, in some embodiments, a non-bridge segment in a metallization layer is a segment that is not directly connected to a bridge segment. Therefore, a non-bridge segment carries no operating voltage, e.g. B. VDD, VSS or the like. In some embodiments, M1 non-bridge segments are used to connect components in a given basic ECO cell or to make connections between the given basic ECO cell and one or more other basic cells. The one or more internal ECO base cell connections that are altered during programming include at least one connection to one or more corresponding instances of the M1 non-bridge segment 124. In some embodiments, when a programmed ECO base cell is traced to establish one or more intercell connections between the programmed ECO base cell and one or more functional standard cells, at least one of the intercell connections is a connection to an instance of the M1 non-bridge segment 124.

In order to produce feature sizes of the semiconductor device that are smaller than those that can be produced with a photolithographic single exposure, the method of photolithographic multiple exposure (OLE multiple exposure) is used. Typically, a double photolithographic exposure will produce feature sizes smaller than a single photolithographic exposure, a triple photolithographic exposure will produce feature sizes smaller than a double photolithographic exposure, and so on. The number of photolithographic exposures is generally referred to as the number of mask (or mask) features (or mask colors). Here the number of masking structures/colors is denoted as CLR, where CLR is a positive integer.

In some embodiments, the layout 100A is created using a multiple photolithographic exposure. In some embodiments, layout 100A is generated with a multiple photolithographic exposure where CLR is an odd number. In some embodiments, the layout 100A is created with a triple exposure photolithographic where CLR=3. In some embodiments, layout 100A is created with a multiple photolithographic exposure where CLR is an even number. In some embodiments, the layout 100A is created with a photolithographic double exposure where CLR=2. It should be noted that in 1A the case is assumed that a photolithographic double exposure is used, i.e. CLR = 2.

1B 10 is a layout 100B that corresponds to layout 100A and shows the assignment of each metallization segment to one or more corresponding masking patterns/colors, according to some embodiments.

Layout 100B is a simplified variation of layout 100A in FIG 1A . As in 1A is also in 1B CLR=2. Thus, in layout 100B, each of Mi-segments 120A, 120B, 122A, and 122B and each of the multiple instances of Mi-segment 124 has been assigned a corresponding one of two masking textures/colors, namely a red texture/color and a green structure/color. The red structure/color includes, but is not limited to, the M1 bridge segments 120A and 122A. The green structure/color includes the Mi bridge segments 120B and 122B, among others.

Except 1B only shows 5C masking structures/colors. The other figures do not show any masking structures/colors.

We come to 1A return. When ECO basic cells are placed in a row of a layout, the gaps between adjacent ECO basic cells should be reduced. These gaps represent wasted space. An adverse consequence of wasted space is, for example, that the transistor density of a semiconductor device is reduced. In addition, the placement of ECO basic cells in a row of a layout is simplified if the ECO basic cells have not only a fixed height but also a fixed width. In some embodiments, a library of standard cells includes sub-libraries of basic ECO cells, each sub-library having basic ECO cells of the same width and height.

wobei {θ} = Θ ist, P_M1-STRAP und P_ECOB positive ganze Zahlen sind und 2 < θ < P_M1-STRAP ist und somit P_ECOB < P_M1-STRAP ist. Es ist zu beachten, dass eine ECO-Basiszelle mit P_ECOB = 3 die Mindestbreite hat, die ausreicht, um einen Transistor herzustellen, wenn die ECO-Basiszelle programmiert wird.In some embodiments, a pitch P _ECOB (or P _SPARE ) of the ECO basic cells can be evenly divided into the pitch P _M1-STRAP (or more generally: P _STRAP ) of the Mi-bridges such that the pitch P _ECOB consists of a set Θ of positive integer values θ is chosen and $${\text{P}}_{\text{ECOB}}\in \left\{\mathrm{\theta }\right\},\text{where o}={\text{P}}_{\text{M1}-\text{STRAP}}\text{model}\mathrm{\theta }\text{is}\text{,}$$

where {θ} = θ, P _M1-STRAP and P _{ECOB are} positive integers and 2 < θ < P _M1-STRAP and hence P _ECOB < P _M1-STRAP . Note that an ECO base cell with P _ECOB = 3 has the minimum width sufficient to make a transistor when the ECO base cell is programmed.

In some embodiments, the grid spacing P _ECOB of the ECO basic cells is chosen to be the smallest element of the set Θ, i.e. the smallest value of θ such that: $${\text{P}}_{\text{ECOB}}=\text{at least}\left\{\mathrm{\theta }\right\}$$

In 1A For ease of illustration, the grid spacing P _M1-STRAP = 36, the grid spacing P _ECOB is equal to 6, and there are 6 ECO basic cells between adjacent M1 bridges (the M1 segment pairs 120A & 120B and 122A & 122B) is with six (6) shown. In particular, the pitch P _M1-STRAP = 36 indicates that there are 36 Mi segments in the gap between the start of one bridge and the start of the next bridge. For example, if you move along the horizontal direction from left to right in 1A counting, there are a total of 36 Mi segments from Mi segment 120A up to and including the rightmost instance of M1 segment 124 in e.g. B. the ECO basic cell 106F. The pitch P _ECOB = 6 indicates that there are 6 Mi-segments in the space between the start of one basic ECO cell and the start of the next basic ECO cell. For example, if you move along the horizontal direction from left to right in 1A counting, there are a total of 6 Mi segments in each of ECO basic cells 106A to 106F, 108A, 110A to 110F, 112A, 114A to 114F and 116A, and counting from left to right in ECO basic cell 106A, for example , then there are six instances of the M1 segment 124. The possible values for θ that satisfy equation (1), i.e. the possible values for θ that equally divide the grid spacing P _ECOB into the grid spacing P _M1-STRAP are 1 , 2, 3, 4, 6, 9, 12, 18 and 36, where the possible values are denoted as the set Θ, where each element of the set Θ is represented by the symbol θ and the set Θ in set notation as Θ = {θ} and in particular Θ = {θ} = {1, 2, 3, 4, 6, 9, 12, 18, 36} if P _ECOB = θ = 6 for 1A has been chosen. Other values for the grid spacing P _M1-STRAP and/or the grid spacing P _ECOB are also contemplated, and therefore other numbers of ECO basic cells between adjacent M1 bridges are also contemplated.

EXAMPLE: - As an example, assume that _PM1-STRAP =30. In particular, the grid spacing P _M1-STRAP = 30 indicates that there are 30 Mi segments along the horizontal direction in the gap between the start of one bridge and the start of the next bridge. The possible values for θ that satisfy equation (1), i.e. the possible values for θ that equally divide the grid spacing P _ECOB into the grid spacing P _M1-STRAP are {θ} = {1, 2, 3, 5, 6, 10, 15, 30}. Bearing in mind that 2<θ<P _M1-STRAP , θ=1, θ=2 and θ=30 must be deleted. Thus, in the example given, P _ECOB = θ = 3. The grid spacing P _ECOB = 3 indicates that there are 3 Mi segments along the horizontal direction in the space between the start of one basic ECO cell and the start of the next ECO cell. basic cell there.

In some embodiments, a reference edge of an ECO base cell is aligned with a selected one of the masking patterns/colors. In some embodiments, the reference edge of each ECO base cell is aligned to a center of the chosen masking pattern/color. For example, is in 1B the reference edge of the ECO basic cells is the left edge, and the left edge is aligned with a center of a corresponding part with the red mask color. In order to achieve contiguity when placing ECO basic cells in a row of a layout and thereby avoid gaps between adjacent ECO basic cells, in some embodiments the pitch P _ECOB of the ECO basic cells is chosen such that it corresponds to the even/odd -Status (parity status) of the number CLR of masking structures/colors matches. Hereinafter, the parity status match distance is denoted by PM _ECOB . If CLR is even, ie if 0 = CLR mod 2, then the value chosen for PM _ECOB should be even. If CLR is odd, ie if 1 = CLR mod 2, then the value chosen for PM _ECOB should be odd. In the 1A and 1B the raster spacing P _{ECOB is} even (P _ECOB = 6) and CLR is even (CLR = 2), as set out above; the left edge of each ECO base cell is chosen as the reference edge become; and the red structure has been chosen to align with the reference edge of each ECO base cell. Since the pitch P _{ECOB is} even (P _ECOB = 6) and CLR is even (CLR = 2) and not odd, there are no gaps between adjacent ECO basic cells in the 1A and 1B . In contrast, the 5A until 5C (to be discussed later) Gaps between adjacent ECO basic cells.

$$\left\{\text{d}\right\}=\begin{array}{c}\text{o}={\text{P}}_{\text{M1-STRAP}}\text{ mod d}\\ \left(\text{ UND }\right)\\ \text{o}=\text{d mod CLR}\end{array}$$

wobei 2 < d < P_M1-STRAP ist.The values for θ that can satisfy the additional requirement of matching the parity status of CLR are a subset of the set θ, ie a subset of {θ}. To distinguish the subset from {θ}, the subset is denoted as the set Δ of positive integer values d, where Δ ⊂ Θ , ie {d} ⊂ {θ}. is. Therefore the pitch PM _{ECOB is} : $${\text{p.m}}_{\text{ECOB}}\in \Delta ,\text{whereby}\Delta =\left\{\text{i.e}\right\}\text{is}\text{,}$$

$$\left\{\text{i.e}\right\}=\begin{array}{c}\text{O}={\text{P}}_{\text{M1 STRAP}}\text{mod d}\\ \left(\text{AND}\right)\\ \text{O}=\text{d mod CLR}\end{array}$$

where 2 < d < P _M1-STRAP .

In some embodiments, the pitch PM _ECOB is chosen to be the smallest element of the set Δ that corresponds to the parity status of CLR, ie the smallest value of d that corresponds to the parity status of CLR such that $${\text{p.m}}_{\text{ECOB}}=\text{at least}\left\{\text{i.e}\right\}\text{is}$$

EXAMPLE: As a variant of the above example, assume not only that P _M1-STRAP = 30, but also that the photolithographic exposure process chosen is a double exposure process such as that in FIGS 1A and 1B method illustrated, is such that CLR=2. Regardless of the parity status of CLR, the possible values for θ that satisfy equation (1), i.e. the possible values for θ that equally divide the grid spacing P _ECOB into the grid spacing P _M1-STRAP , are 1, 2, 3, 5 , 6, 10, 15 and 30, where the possible values are denoted as the set Θ, where each element of the set Θ is represented by the symbol θ and the set Θ in set notation as Θ = {θ} and in particular as Θ = { θ} = {1, 2, 3, 5, 6, 10, 15, 30}. Here, however, the parity status of the CLR is taken into account. Here CLR=2, and thus the parity status of CLR is even since 0=CLR mod 2=2 mod 2. Hence the subset of {Θ}, i.e. {d}, which satisfies equation (4), i.e. for which all elements correspond to the parity status of CLR (where CLR is even here), {d} = {2, 6, 10 , 30}. Using equation (5) and remembering that 2 < d < P _M1STRAP , d=2 and d=30 must be deleted. Thus, in the example given, PM _ECOB = 6.

EXAMPLE: As a variant of the first example above, assume not only that _PM1-STRAP =30, but also that the photolithographic exposure process chosen is a triple exposure process, so CLR=3. Regardless of the parity status of CLR, the possible values for θ that satisfy equation (2), i.e. the possible values for θ that equally divide the grid spacing P _ECOB into the grid spacing P _M1-STRAP , are {θ} = {1, 2, 3, 5, 6, 10, 15, 30}. Here, however, the parity status of the CLR is taken into account. Here CLR=3, and thus the parity status of CLR is odd since 1=CLR mod 2=3 mod 2. Hence the subset of {θ}, i.e. {d}, that satisfies equation (4), i.e. for which all elements correspond to the parity status of CLR (where CLR is odd here), {d} = {1, 3, 5 , 15}. Using equation (5) and remembering that 2<d<P _M1-STRAP , d=1 must be deleted. Thus, in the example given, PM _ECOB = 3.

1C 10 is a layout 100C corresponding to layout 100A showing reserved areas in the ECO basic cells according to some embodiments.

If a given set of Mi-segments in an ECO basic cell is reserved for a special purpose, the given set of Mi-segments can be used for the special purpose. For example, reserving the given set of Mi segments in a basic ECO cell for a bridge indicates that the given set of Mi segments is used for a bridge.

When an area in an ECO basic cell is reserved for a special purpose, the Mi segments in the reserved area can be used for the special purpose. For example, the reservation of an area in an ECO basic cell for a bridge indicates that the Mi segments in the reserved area are used for a bridge. In some embodiments, one and the same area in each ECO base cell is reserved for the same purpose.

The layout 100C is a simplified variant of the layout 100A of FIG 1A , although a variant in which a reserved area and a non-reserved area have been designated in each ECO basic cell. In some embodiments, with respect to the M1 layer, all ECO basic cells in a library of standard cells are arranged to have the same number of one or more Mi segments as Ver reserve the turn as M1 bridge segments. Although not every ECO base cell has an M1 bridge traced through the ECO base cell, reserving the same number of Mi segments in each ECO base cell simplifies the placement of a given ECO base cell in a row of a layout.

In some embodiments, in addition to reserving the same number of Mi segments, each basic ECO cell in a library of standard cells designates the same area in the cell as the area in which the reserved number of Mi segments resides. Reserving the same area in each ECO basic cell for Mi-segments further simplifies the placement of a given ECO basic cell in a row of a layout, since it e.g. B. Eliminates the possible conflict that might otherwise arise when Mi segments intended for purposes other than bridges are then also required to be used as bridge segments.

In 1C the reserved areas are aligned to the left edge. In particular, reserved areas are 140A, 140B, 140C, 140D, 140E and 140F (140A to 140F), 144A, 150A to 150F, 154A, 160A to 160F and 164A in corresponding ECO basic cells 106A to 106F, 108A, 120A to 110A to 110F , 114A to 114F and 116A. Left edges of reserved areas 140A, 140B, 140C, 140D, 140E and 140F (140A to 140F), 144A, 150A to 150F, 154A, 160A to 160F and 164A are to left edges of the corresponding ECO basic cells 106A to 106F, 108A, 110A to 110F, 112A, 114A to 114F and 116A. The Mi segments in the reserved areas 140A to 140F, 144A, 150A to 150F, 154A, 160A to 160F and 166A are intended for use as M1 bridge segments.

Also, in the ECO basic cells 106A to 106F, 108A, 110A to 110F, 112A, 114A to 114F and 116A, corresponding areas 142A to 142F, 146A, 152A to 152F, 156A, 162A to 162F and 166A are non-reserved areas. None of the non-reserved areas 142A to 142F, 146A, 152A to 152F, 156A, 162A to 162F and 166A are divided into two parts by corresponding reserved areas 140A to 140F, 144A, 150A to 150F, 154A, 160A to 160F and 164A.

The Mi segments in the non-reserved areas 142A-142F, 146A, 152A-152F, 156A, 162A-162F, and 166A are intended for use as M1 non-bridge segments. In 1C are corresponding ones of the multiple instances of M1 segment 124 (in 1C not shown, but see the 1A and 1B ) are located in the non-reserved areas 142A to 142F, 146A, 152A to 152F, 156A, 162A to 162F and 166A.

2 FIG. 2 is a layout 200 for a semiconductor device showing reserved areas in the ECO basic cells according to some embodiments.

The layout 200 is a variant of the layout 100C of FIG 1C . In some embodiments, the M(i) layer is M1. In 2 is M(i) M1. Similar to the 1A until 1C is in 2 (as an example) the grid spacing P _M1-STRAP = 36, the grid spacing P _ECOB = 6, CLR = 2, and there are 6 ECO basic cells between adjacent M1 bridges (the M1 segment pairs 120A & 120B and 122A & 122B) shown.

In 2 the reserved areas are aligned to the right edge, while 1C shows an alignment to the left edge. In particular, in 2 reserved areas 240A to 240F, 244A, 250A to 250F, 254A, 260A to 260F and 264A are located in respective ECO basic cells 206A to 206F, 208A, 210A to 210F, 212A, 214A to 214F and 216A. Right edges of reserved areas 240A to 240F, 244A, 250A to 250F, 254A, 260A to 260F and 264A are aligned with right edges of corresponding ECO basic cells 206A to 206F, 208A, 210A to 210F, 212A, 214A to 214F and 216A. The Mi segments in the reserved areas 240A to 240F, 244A, 250A to 250F, 254A, 260A to 260F and 266A are intended for use as M1 bridge segments.

In 2 For example, Mi bridge segments 220A and 220B constitute a first M1 bridge and are located in reserved areas 240A, 250A and 260A. Mi bridge segments 222A and 222B represent a second M1 bridge and are located in reserved areas 244A, 254A and 264A. In some embodiments, the first M1 bridge (represented by M1 bridge segments 220A and 220B) is connected to the power supply VDD and the second M1 bridge (represented by Mi bridge segments 222A and 222B) is connected to the Operating voltage VSS connected.

Also, in the ECO basic cells 206A to 206F, 208A, 210A to 210F, 212A, 214A to 214F and 216A, corresponding areas 242A to 242F, 246A, 252A to 252F, 256A, 262A to 262F and 266A are non-reserved areas. None of the non-reserved areas 242A to 242F, 246A, 252A to 252F, 256A, 262A to 262F and 266A are divided into two parts by corresponding reserved areas 240A to 240F, 244A, 250A to 250F, 254A, 260A to 260F and 264A. The Mi segments in the non-reserved areas 242A to 242F, 246A, 252A through 252F, 256A, 262A through 262F, and 266A are for use as M1 non-bridge segments.

3A FIG. 3 is a layout 300 for a semiconductor device showing reserved areas in the ECO basic cells according to some embodiments. 3B FIG. 3 is a simplified variation of the layout 300 in which the reserved and non-reserved areas are not shown, according to some embodiments. 3C FIG. 3 is a simplified variation of the layout 300 in which the basic ECO cells are not shown, according to some embodiments.

In some embodiments, the M(i) layer is M1. In the 3A until 3C is M(i) M1. Similar to the 1A until 1C is in 3 (as an example) the grid spacing P _M1-STRAP = 36, the grid spacing P _ECOB = 6, CLR = 2, and there are 6 ECO basic cells between adjacent M1 bridges (the M1 segment pairs 120A & 120B and 122A & 122B) shown.

The layout 300 is a variant of the layout 100C of FIG 1C . in the 3A until 3C are the reserved areas centered in the ECO base cells, while 1A shows an alignment to the left edge and 2 shows an alignment to the right edge. In particular, reserved areas 340A-340F, 344A, 350A-350F, 354A, 360A-360F, and 364A are horizontally centered in corresponding ECO base cells 306A-306F, 308A, 310A-310F, 312A, 314A-314F, and 316A. The Mi segments in reserved areas 340A through 340F, 344A, 350A through 350F, 354A, 360A through 360F, and 366A are intended for use as M1 bridge segments.

In the 3A until 3C For example, M1 bridge segments 320A and 320B constitute a first M1 bridge and are located in reserved areas 340A, 350A and 360A. Mi bridge segments 322A and 322B represent a second M1 bridge and are located in reserved areas 344A, 354A and 364A. In some embodiments, the first M1 bridge (represented by M1 bridge segments 320A and 320B) is connected to the power supply VDD and the second M1 bridge (represented by Mi bridge segments 322A and 322B) is connected to the Operating voltage VSS connected.

As a result of the centering, each ECO base cell in the 3A until 3C two non-reserved areas, namely a left non-reserved area and a right non-reserved area. In the ECO basic cells 306A to 306F, 308A, 310A to 310F, 312A, 314A to 314F and 316A there are corresponding left areas 342A to 342F, 346A, 352A to 352F, 356A, 362A to 362F and 366A, the non-reserved areas and corresponding right areas 343A to 343F, 347A, 353A to 353F, 357A, 363A to 363F and 367A which are non-reserved areas. The Mi segments in the non-reserved areas 342A to 342F, 343A to 343F, 346A, 347A, 352A to 352F, 353A to 353F, 356A, 357A, 362A to 362F, 363A to 363F, 366A and 367A are for use as M1 non-bridge segments determined.

4A 4 shows a layout 400, for a semiconductor device, of basic ECO cells in relation to line segments in an i-th metallization layer M(i), according to some embodiments. 4B FIG. 4 is a simplified variation of the layout 400 in which the reserved and non-reserved areas are not shown, according to some embodiments. 4C FIG. 4 is a simplified variant of the layout 400 in which the basic ECO cells are not shown, according to some embodiments.

In some embodiments, the M(i) layer is M1. In the 4A until 4C is M(i) M1.

the 4A until 4C show a different grid spacing P _ECOB in relation to the grid spacing P _M1-STRAP than e.g. Tie 1A until 1C . The layout 400 is a variant of the layout 100A of FIG 1A . In the 4A until 4C 3 ECO basic cells are shown between adjacent M1 bridges. In some embodiments, in the 4A until 4C the grid spacing P _M1-STRAP = 36, the grid spacing P _ECOB = 10, and CLR = 2. Specifically, the grid spacing P _M1-STRAP = 36 indicates that there are 36 Mi segments along the horizontal direction in the space between the beginning of the one bridge and the start of the next bridge there. For the sake of simplicity are in the 4A until 4C while Mi segments 435A and 435B, 436A and 436B, 437A and 437B, and 438A and 438B are shown, other Mi segments are not shown. The pitch P _ECOB = 10 indicates that there are 10 Mi segments along the horizontal direction in the space between the start of one ECO basic cell and the start of the next ECO basic cell.

Similar to in 1A are the reserved areas in the 4A and 4C aligned to the left edge. Specifically, reserved areas are 440A through 440C, 444A through 444C, 448A through 448C, 452A through 452C, 460A through 460C, 464A through 464C, 468A through 468C, 472A through 472C, 480A through 480C, 484A through 48C4C, and through 48284C through 492C in corresponding ECO basic cells 406A to 406C, 408A to 408C, 410A to 410C, 412A to 412C, 416A to 416C, 418A to 418C, 420A to 420C, 422A to 422C, 424A to 424C, 426A to 426C, 428A to 428C and 430A to 430C.

Left edges of reserved areas 440A through 440C, 444A through 444C, 448A through 448C, 452A through 452C, 460A through 460C, 464A through 464C, 468A through 468C, 472A through 472C, 480A through 480C, 484A through 472C, and 4 through 4884C through 984C through thru 492C are to left edges in respective ECO base cells 406A through 406C, 408A through 408C, 410A through 410C, 412A through 412C, 416A through 416C, 418A through 418C, 420A through 420C, 422A through 422C, 424A through 426C through 4264C through , 428A to 428C and 430A to 430C. The Mi segments in the reserved areas 440A to 440C, 444A to 444C, 448A to 448C, 452A to 452C, 460A to 460C, 464A to 464C, 468A to 468C, 472A to 472C, 480A to 480C, 484C to 484C, to 484C 488C and 492A through 492C are for use as M1 bridge segments.

Also in the ECO basic cells 406A to 406C, 408A to 408C, 410A to 410C, 412A to 412C, 416A to 416C, 418A to 418C, 420A to 420C, 422A to 422C, 424A to 424C, 426A to 428C, 428C to 428C, and 430A to 430C corresponding areas 442A to 442C, 446A to 446C, 450A to 450C, 454A to 454C, 462A to 462C, 466A to 46C, 470A to 470C, 474A to 474C, 482A to 482C, 4, 906A to 4, 486A to 4, 486A to 4, 486C to 4 494A to 494C non-reserved areas.

The Mi segments in reserved areas 440A, 460A and 480A are intended for use as corresponding Mi bridge segments 435A through 435B. The Mi bridge segments in reserved areas 444A, 464A and 484A are intended for use as corresponding Mi bridge segments 436A and 436B. The Mi segments in reserved areas 448A, 468A and 488A are intended for use as corresponding Mi bridge segments 437A and 437B. The Mi segments in reserved areas 452A, 472A and 492A are intended for use as corresponding Mi bridge segments 438A and 438B.

5A 500A is a layout 500A, for a semiconductor device, of basic ECO cells in relation to line segments in an i-th metallization layer M(i) according to some embodiments. 5B 5 is a layout 500B that is a simplified variation of the layout 500A, although it also shows unnecessary space, according to some embodiments.

5C 5 is a layout 500C that is a simplified variation of the layout 500A, although it also shows unnecessary spacing and the assignment of each metallization segment to a corresponding masking pattern/color, according to some embodiments. Except 5C only shows 1B masking structures/colors. The other figures do not show any masking structures/colors.

In some embodiments, the M(i) layer is M1. In the 5A until 5C is M(i) M1. The layout 500 is a variant of the layout 100 of 1A . In the 5A until 5C For example, reserved areas (not shown) are aligned with left edges of basic ECO cells 506A-506D, 508A, 510A-510D, 512A, 514A-514D, and 516A.

In some embodiments, a layout 500A is created using a multiple exposure photolithographic process. In some embodiments, layout 500A is created using a multiple exposure photolithographic process where CLR is an even number. In some embodiments, the layout 500A is created using a double exposure photolithographic process where CLR=2. In some embodiments, layout 500A is created using a multiple exposure photolithographic process where CLR is an odd number. In some embodiments, the layout 500A is created using a triple exposure photolithographic process where CLR=3. It should be noted that in the 5A until 5C the case is assumed that a triple exposure photolithographic process is used, i.e. CLR = 3.

In the 5A until 5C For ease of illustration, grid spacing P _M1-STRAP = 36, grid spacing P _ECOB = 4, and 6 basic ECO cells are shown between adjacent M1 bridges. In particular, the pitch P _M1-STRAP = 36 indicates that there are 36 M1 segments along the horizontal direction in the space between the start of one bridge and the start of the next bridge. The pitch P _ECOB = 4 indicates that there are 4 Mi segments along the horizontal direction in the space between the start of one ECO basic cell and the start of the next ECO basic cell. The possible values for θ that satisfy equation (1), i.e. the possible values for θ that allow a uniform subdivision in P _M1-STRAP are {θ} = {1, 2, 3, 4, 6, 9, 12, 18, 36}, where P _ECOB = θ = 4 for the 5A until 5C has been chosen. Bearing in mind that 2<θ<P _M1-STRAP , θ=1, θ=2 and θ=36 must be deleted. Other values for grid spacing P _M1-STRAP , grid spacing P _ECOB and/or CLR are also contemplated and therefore other numbers of ECO basic cells between adjacent M1 bridges are also contemplated. In the 5A until 5C is the Grid spacing P _ECOB even (P _ECOB = 4), CLR is odd (CLR = 3), the left edge of each ECO basic cell has been chosen as the reference edge, and the red structure ( 5C ) has been chosen to align with the reference edge of each ECO base cell. The possible values for d that satisfy equation (4), i.e. the possible values for d that allow an even subdivision in P _M1-STRAP AND that are evenly divisible by CLR (CLR = 3) are {d} = { 3, 6, 9, 12, 18, 36}. Bearing in mind that 2<d<P _M1-STRAP , d=36 must be deleted. While θ=4 for equation (1), d≠4 for equation (4) since θ=d mod CLR does NOT hold, ie θ≠4 mod 3, rather than 1=4 mod 3. Due to the parity mismatch , ie, since the grid spacing P _ECOB is even (P _ECOB = 4) and CLR is odd (CLR = 3), the 5B and 5C The following: a gap 551A between the ECO basic cells 506A, 510A and 514A and the corresponding ECO basic cells 506B, 510B and 514B; a gap 551B between ECO basic cells 506B, 510B and 514B and corresponding ECO basic cells 506C, 510C and 514C; a gap 551C between ECO basic cells 506C, 510C and 514C and corresponding ECO basic cells 506D, 510D and 514D; a gap 551D between ECO basic cells 506D, 510D and 514D and corresponding ECO basic cells 506E, 510E and 514E; a gap 551E between ECO basic cells 506E, 510E and 514E and corresponding ECO basic cells 506F, 510F and 514F; and a gap 551F between ECO basic cells 506F, 510F and 514F and corresponding ECO basic cells 508A, 512A and 516A.

6A 6 is a flow diagram of a method 600 for designing, for a semiconductor device, a layout having spare standard cells, according to some embodiments.

In 6A In a block 602, a set of possible values for a pitch P _SPARE of spare standard cells based on the pitch P _STRAP of bridge lines of a metallization layer M(i) in a layout for a semiconductor device is generated. In some embodiments, M(i) is M1. Details of block 602 are provided with reference to FIG 6B explained. From block 602 flow proceeds to block 604 . In block 604, one member of the set of possible values is chosen as the grid spacing P _SPARE . Details of block 604 are provided with reference to FIG 6C explained. From block 604 flow proceeds to block 606 . In block 606, spare standard cells are placed in a logical area of the layout corresponding to grid spacing P _SPARE . From block 606 flow proceeds to block 608 .

In block 608, a portion is reserved/selected as a reserved portion in each spare cell, and one or more of the bridge lines may be established across the reserved portion. In some embodiments, each reserved portion extends across the spare cell. Details of block 608 are provided with reference to FIG 6D explained. From block 608 flow proceeds to block 610 . In block 610, one or more masks for the layout are generated based on the grid spacing P _STRAP and the grid spacing P _SPARE . From block 610 flow proceeds to block 612 . At block 612, a semiconductor device is fabricated using the one or more masks.

6B 6 is a more detailed representation of block 602 in method 600, according to some embodiments.

In 6B the block 602 includes a block 618. In the block 618 the set of possible values for the grid spacing P _{SPARE is} also generated based on a number of CLR masks that have been chosen for the production of the metallization layer. Details of block 618 are discussed with reference to blocks 620-624.

Block 618 includes blocks 620-624. In block 620, a first set of candidate positive integers is calculated, where each element of the first set is a positive integer that can be evenly partitioned into the grid spacing P _STRAP . From block 620 flow proceeds to block 622 . In block 622, a second set of candidate positive integers is computed, each element of the second set being evenly divisible by the number of masks CLR. From block 622 flow proceeds to block 624 . In block 624, the first and second groups are divided to generate a third group of candidate positive integers. The third group represents the set of possible values for a pitch P _SPARE of reserve standard cells.

6C 6 is further detailed representation of block 604 in method 600, according to some embodiments.

In 6C In a block 630, the smallest element of the set of possible values for a grid spacing P _SPARE is chosen as the grid spacing P _SPARE . In some embodiments, 2 < PSPARE. By choosing the smallest element, gaps between adjacent ECO basic cells are reduced, reducing wasted space and increasing the density (which is defined as the number of devices expressed per cell) is increased.

6D 6 is a more detailed representation of block 608 in method 600, according to some embodiments.

In 6D the block 608 has a block 640 . In block 640, each reserved part is arranged/placed such that a remaining part of the spare cell is not divided into parts.

7A 7 is a flow chart of a method 700 for designing, for a semiconductor device, a layout having functional base cells and spare base cells, according to some embodiments.

In 7A In a block 702, functional standard cells are placed/arranged to partially fill a logic area of a layout according to at least one corresponding schematic design, leaving an unfilled spare area in the logic area. From block 702 flow proceeds to block 704 . In block 704, a pitch P _STRAP of bridge lines for a metallization layer M(i) is determined. In some embodiments, M(i) is M1. From block 704 flow proceeds to block 706 . In block 706, a set of possible values for a grid spacing P _SPARE of spare cells based on the grid spacing P _STRAP is generated. Details of block 706 are provided with reference to FIG 7B explained. From block 706 flow proceeds to block 708 . In block 708, one member of the set of possible values is chosen as the grid spacing P _SPARE . Details of block 708 are provided with reference to FIG 7C explained. From block 708 flow proceeds to block 710 . In block 710, spare standard cells are arranged/placed in the spare area according to the grid spacing P _SPARE . From block 710 flow proceeds to block 712 .

In block 712, a portion is reserved/selected as a reserved portion in each spare cell, and one or more bridge lines may be established across the reserved portion. In some embodiments, each reserved portion extends across the spare cell. From block 712 flow proceeds to block 714 . In block 714, each reserved part is arranged/placed such that a remaining part of the spare cell is not divided into parts. From block 714 flow proceeds to block 716 . In block 716, one or more masks are generated for the layout based on the grid spacing P _STRAP and the grid spacing P _SPARE . From block 716 flow proceeds to block 718 . At block 718, a semiconductor device is fabricated using the one or more masks.

7B 7 is a more detailed representation of block 706 in method 700, according to some embodiments.

In 7B For example, block 706 includes blocks 720 and 722. At block 720, a value for CLR is received, where CLR represents a number of masks chosen to fabricate the metallization layer. From block 720 flow proceeds to block 722 . In block 722, a set Δ of candidate positive integers d, Δ={d}, is calculated. Each candidate positive integer d is evenly divisible into the grid spacing P _STRAP , and each candidate positive integer d matches a parity state of CLR such that: $$\left\{\text{i.e}\right\}=\begin{array}{c}\text{O}={\text{P}}_{\text{M1 STRAP}}\text{mod d}\\ \left(\text{AND}\right)\\ \text{O}=\text{d mod CLR}\end{array}$$

7C 7 is a more detailed representation of block 708 in method 700, according to some embodiments.

In 7C the block 708 has a block 724 . In block 724, a smallest element of the set Δ={d} is chosen as the grid spacing P _{SPARE such} that $${\text{P}}_{\text{SAVE}}=\text{at least}\left\{\text{i.e}\right\}.$$

8th 8 is a flow diagram of a method 800 for designing, for a semiconductor device, a layout having spare standard cells, according to some embodiments.

In 8th In a block 802 for a layout for a semiconductor device, a pitch P _STRAP of bridge lines of a metallization layer M(i) and a pitch P _SPARE of spare standard cells are received at an input device of a computer. In some embodiments, M(i) is M1. From block 802 flow proceeds to block 804 . In block 804, a portion is reserved/selected as a reserved portion in each spare cell, and one or more of the bridge lines may be established across the reserved portion. In some embodiments, each reserved portion extends across the spare cell. From block 804 flow proceeds to block 806 . In block 806, each reserved part is arranged/placed such that a remaining part of the spare cell is not divided into parts. From block 806 flow proceeds to block 808 . At block 808, in a spare area of a logic area, spare cells are arranged/placed according to a grid spacing P _SPARE . From block 808 flow proceeds to block 810 . In block 810, one or more masks for the layout are generated based on the grid spacing P _STRAP and the grid spacing P _SPARE . From block 810 flow proceeds to block 812 . At block 812, a semiconductor device is fabricated using the one or more masks.

9A 9 is a schematic representation of a semiconductor device 900 according to some embodiments.

The device 900 includes an IC fabricated on a substrate 921 . The device 900 has a logic area 904 . In some embodiments, logic portion 904 is configured to provide high-level functionality of device 900 . In some embodiments, logic area 904 represents one or more circuits. In some embodiments, logic area 904 includes an array 970 of ECO cells and one or more non-standard cells 951 (one or more custom cells and/or one or more macro cells). . In some embodiments, logic area 904 includes matrix 970 of ECO cells and one or more functional standard cells 955 organized in one or more arrays that provide corresponding one or more higher-level functions. The non-standard cells 951 comprise a group of one or more non-standard cells 953. The functional standard cells 955 comprise a group of one or more functional standard cells 957. The ECO cells in the matrix 970 comprise a group 971 of one or more ECO- cells and a group 975 of one or more ECO cells. Initially, all ECO cells in the array 970 are basic ECO cells since none of the ECO cells have yet been programmed (transformed) into a programmed ECO cell. 9A 12 illustrates an initial state of device 900 in which none of the ECO cells in matrix 970 are connected to (or are traced to) non-standard cells 951 or functional standard cells 955. FIG.

9B FIG. 9 is a schematic representation of the semiconductor device 900 with one or more programmed ECO cells and one or more basic ECO cells according to some embodiments.

9B FIG. 12 illustrates a modified state of the device 900. In particular, FIG 9B that group 971 of one or more ECO basic cells and group 975 of one or more ECO basic cells have been programmed such that groups 971 and 975 have been transformed into corresponding groups 972 and 976 of one or more programmed ECO cells . In some embodiments mirrors 9B reflects the assumption that group 953 has failed. Accordingly, wire run 974 represents connections made between group 972 of programmed ECO cells and logic area 904 so that group 972 can serve (in effect) as a replacement for failed group 953. In some embodiments mirrors 9B reflects the assumption that Group 957 has failed. Accordingly, a line run 978 represents connections made between the set 976 of programmed ECO cells and the logic area 904 so that the set 976 can (in effect) serve as a replacement for the failed set 958.

10 10 is a flow diagram of a method 1000 for designing or manufacturing a semiconductor device, according to some embodiments. Below is the procedure of 10 with reference to the 9A and 9B described.

In 10 , in a block 1005 a semiconductor device is designed or manufactured. In some embodiments, the device in block 1005 is semiconductor device 900, which is shown in FIG 9A is shown. From block 1005 flow proceeds to block 1015 . At block 1015, device 900 (designed or manufactured) is tested. In some embodiments, the logic area 904 of the device 900, e.g. B. by one or more simulations, and is compared to a variety of design rules and / or the target specification of the device 900. In at least one embodiment, a test version of the device 900 is manufactured based on the initial design, and then the manufactured test version of the device 900 is tested. Based on the test results of the designed device 900 and/or the manufactured test version of the device 900, a decision is made to revise the design, e.g. B. because of an unacceptable timing problem, an unacceptable electromigration problem or the like. From block 1015 flow proceeds to block 1025 . In certain circumstances, a change to the design is requested even though the test results do not indicate a revision of the design. Under these circumstances, the change in design is received and flow proceeds from block 1015 to block 1025. In some other cases, in addition to the test results, the occasion give to a draft revision also receive a draft change. In these cases, flow proceeds from block 1015 to block 1025 as well.

At block 1025, one or more ECO base cells are programmed in array 970 if test results indicate that the design should be revised and/or a design change has been received. For example, if the design is to be revised to include the failed Group 953 and/or the failed Group 957 (which are included in 9A shown), one or more ECO basic cells in the array 970, e.g. B. Group 971 and/or Group 975 (which in 9A shown), programmed to provide the equivalent function of the corresponding failed groups 953 and/or 957. By programming groups 971 and/or 975, the one or more basic ECO cells in groups 971 and/or 975 are transformed into corresponding groups 972 and/or 976 of one or more programmed ECO cells. From block 1025 flow proceeds to block 1035 . In block 1035, one or more programmed ECO cells in groups 972 and/or 976 are traced to (electrically connected to) one or more corresponding functional standard cells in logic area 904, thereby (effectively) replacing failed groups 954 and/or or 957 can be replaced.

In at least one embodiment, one or more ECO base cells in matrix 970 are programmed and mapped so that in logic area 904 one or more cells (not shown) (which are not necessarily failed) are modified rather than replaced. In at least one embodiment, one or more ECO base cells in matrix 970 are programmed and mapped to add new functionality to logic area 904 . In some embodiments, the revised IC design and/or an IC manufactured from the revised design is reviewed to determine whether further revisions should be made. In at least one embodiment, the process is repeated until it is determined that the IC should be redesigned or that the revised IC design is sufficient for mass production.

The above methods include example steps, but they do not necessarily have to be performed in the order presented. Steps may be added, substituted, changed in order, and/or omitted according to the spirit and scope of embodiments of the invention. Embodiments combining different features and/or different embodiments are within the scope of the invention and should become apparent to one of ordinary skill in the art after reviewing this invention.

In some embodiments, one or more steps of method 1000 are performed with one or more computing systems. For example, one or more of designing an IC, simulating a design of the IC, programming basic ECO cells, and tracing the programmed ECO cells to a circuit of the IC are performed with one or more computer systems.

11 11 is a block diagram of an EDA system 1100 (EDA: Design Automation of Electronic Systems) according to some embodiments.

In some embodiments, the EDA system 1100 is a general purpose computing device that includes a hardware processor 1102 and a non-transitory machine-readable storage medium 1104 . Storage medium 1104 is encoded with (ie, stores, among other things) computer program code 1106, where computer program code 1106 is a set of executable instructions. According to one or more embodiments, the execution of instructions 1106 is performed by the hardware processor 1102 (at least in part) with an EDA tool that implements part or all of the following processes: selection of the functional standard cells, placement, routing, checking and /or the entire SPRT process and the processes that e.g. B. in at least one of the methods of 6A until 6D , 7A until 7C , 8th and 10 (hereinafter referred to as "the foregoing PROCESSES AND/OR PROCEDURES").

The processor 1102 is electrically connected to the machine-readable storage medium 1104 via a bus 1108 . The processor 1102 is also electrically connected to an I/O interface 1110 through the bus 1108 . A network interface 1112 is also electrically connected to processor 1102 via bus 1108 . The network interface 1112 is connected to a network 1114 so that the processor 1102 and the machine-readable storage medium 1104 can connect external elements via the network 1114 . Processor 1102 is configured to execute computer program code (instructions) 1106 encoded on machine-readable storage medium 1104 to enable system 1100 to perform some or all of the foregoing PROCESSES AND/OR METHODS. In one or more embodiments, processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or other suitable processing unit.

In one or more embodiments, the machine-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or component). Machine-readable storage medium 1104 includes, for example, semiconductor or solid state memory, magnetic tape, removable disk, random access memory (RAM), read only memory (ROM), rigid magnetic disk, and/or optical disk. In one or more embodiments using optical disks, the machine-readable storage medium 1104 is a Compact Disc Read-Only Memory (CD-ROM), a Compact Disc Read/Write (CD-R/W), and/or a digital video disk (DVD).

In one or more embodiments, storage medium 1104 stores computer program code 1106 configured to enable system 1100 to perform some or all of the foregoing PROCESSES AND/OR METHODS [whereby execution (at least in part) using the EDA tool done]. In one or more embodiments, storage medium 1104 also stores information that enables execution of some or all of the foregoing PROCESSES AND/OR METHODS. In one or more embodiments, the storage medium 1104 stores a library 1107 of standard cells, including functional standard cells and standard ECO basic cells.

The EDA system 1100 has the I/O interface 1110 . The I/O interface 1110 is connected to external circuits. In one or more embodiments, I/O interface 1110 includes a keyboard, mouse, trackball, touchpad, touch screen, and/or cursor directional keys for communicating information and commands to processor 1102.

The EDA system 1100 also has a network interface 1112 that is connected to the processor 1102 . Network interface 1112 allows system 1100 to communicate with network 1114 to which one or more computer systems are connected. Network interface 1112 includes wireless network interfaces such as Bluetooth, Wifi, Wimax, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB or IEEE-1364. In one or more embodiments, some or all of the foregoing PROCESSES AND/OR METHODS are implemented in two or more systems 1100 .

The system 1100 is configured to receive information via the I/O interface 1110 . The information received via I/O interface 1110 includes commands, data, design rules, standard cell libraries, and/or other parameters for processing by processor 1102. The information is sent to processor 1102 via bus 1108 . The EDA system 1100 is configured to receive user interface (UI) information via the I/O interface 1110 . The information is stored in machine-readable medium 1104 as UI 1142 .

In some embodiments, part or all of the foregoing PROCESSES AND/OR METHODS are implemented as an independent software application for execution by a processor. In some embodiments, part or all of the foregoing PROCESSES AND/OR METHODS are implemented as a software application that is part of another software application. In some embodiments, part or all of the foregoing PROCESSES AND/OR METHODS are implemented as a plug-in to a software application. In some embodiments, at least one of the foregoing PROCESSES AND/OR METHODS is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the foregoing PROCESSES AND/OR METHODS are implemented as a software application used by EDA system 1100 . In some embodiments, a layout comprising standard cells plus basic ECO cells and/or programmed ECO cells is generated using a tool such as Virtuoso®, available from Cadence Design Systems, Inc., or other suitable layout generation tools generated.

Claims (17)

A method of designing, for a semiconductor device, a layout comprising unprogrammed spare standard cells, comprising the steps of: generating (602), based on a first pitch (P _STRAP ) of bridge lines of a metallization layer, a set of possible values for a second pitch (P _SPARE ) of unprogrammed spare standard cells; Choosing (604) an element of the set of pos common values as the second grid spacing (P _SPARE ); placing (606) unprogrammed spare standard cells in a logic area (904) of the layout corresponding to the second pitch (P _SPARE ), and reserving (608), in each spare standard cell, a reserved portion over which one or more bridge lines are fabricated with each reserved part passing over the reserve standard cell; wherein at least one of creating, selecting and placing is performed by a processor of a computer. procedure after claim 1 wherein generating (602) the set of possible values for the second pitch (P _SPARE ) is also based on a number (CLR) of masks chosen to fabricate the metallization layer. procedure after claim 2 , wherein generating (602) the set of possible values for the second grid spacing (P _SPARE ) comprises: calculating (620) a first set of candidate positive integers, each candidate positive integer evenly divided into the first grid spacing (P _STRAP ) is divisible; calculating (622) a second group of candidate positive integers, each candidate positive integer being evenly divisible by the number (CLR) of masks; and dividing (624) the first and second groups of candidate positive integers to produce a third group of candidate positive integers, the third group being the set of possible values for the second grid spacing (P _SPARE ) represents. procedure after claim 3 wherein selecting (604) possible values as the second grid spacing (P _STRAP ) comprises: selecting (630) a smallest element of the third group as the second grid spacing (P _SPARE ), where the first grid spacing P _SPARE 2 < P _SPARE Fulfills. The method of any preceding claim, further comprising: generating (610) one or more masks for the layout based on the first grid spacing (P _STRAP ) and the second grid spacing (P _SPARE ). procedure after claim 5 , further comprising: fabricating (612) a semiconductor device using the one or more masks. A method according to any one of the preceding claims, wherein the reserving comprises: arranging (640) each reserved portion such that a remaining portion of the reserve standard cell is not subdivided. A method according to any one of the preceding claims, wherein the metallization layer is M1. A machine-readable medium containing machine-readable instructions for performing a method for designing a semiconductor device, the method comprising the steps of: placing (702) functional standard cells such that they partially fill a logic region (904) of a layout according to at least one corresponding schematic design such that a spare area is left unfilled in the logic area; determining (704) a first pitch (P _STRAP ) of bridge lines for a metallization layer in the spare area; generating (706) a set of possible values for a second grid spacing (P _SPARE ) of spare standard cells based on the first grid spacing (P _STRAP ); choosing (708) a member of the set of possible values as the second grid spacing (P _SPARE ); placing (710) spare unprogrammed standard cells in the spare area corresponding to the second pitch (P _SPARE ), reserving (712), in each spare unprogrammed standard cell, a reserved portion over which one or more bridge lines can be fabricated, each reserved Part runs across a reserve standard cell; and arranging (714) each reserved part so that a remaining part of the spare standard cell is not divided; wherein at least one of placing, determining, generating, selecting and arranging is performed by a processor of a computer. machine-readable medium claim 9 wherein generating (706) the set of possible values for the second grid spacing (P _SPARE ) comprises: receiving (720) a value, CLR, representing a number of masks chosen to fabricate the metallization layer; calculating (722) a set Δ of candidate positive integers d, Δ = {d}, where each candidate positive integer d is evenly divisible into the first grid spacing P _STRAP and corresponds to a parity status of the value, CLR, which represents the number of CLR masks such that $$\left\{\text{i.e}\right\}=\begin{array}{c}\text{O}={\text{P}}_{\text{M1 STRAP}}\text{mod d}\\ \left(\text{AND}\right)\\ \text{O}=\text{d mod CLR}\end{array};$$

and choosing (708) an element from the set Δ = {d} as the second grid spacing (P _SPARE ). machine-readable medium claim 10 , wherein choosing (708) an element of the set Δ = {d} as the second grid spacing (P _SPARE ) comprises: choosing (724) a smallest element of the set Δ = {d} as the second grid spacing P _{SPARE such} that $${\text{P}}_{\text{SAVE}}=\text{at least}\left\{\text{i.e}\right\}.$$

Machine-readable medium according to any of claims 9 until 11 wherein the metallization layer is M1, and the method further comprises: generating (716) one or more masks for the layout based on the first pitch and the second pitch. machine-readable medium claim 12 , the method further comprising: fabricating (718) a semiconductor device using the one or more masks. A semiconductor device (900) comprising: functional standard cells (955) arranged in a logic area (904); unprogrammed spare standard cells (970) arranged in a spare area of the logic area (904); and a metallization layer over the spare standard cells (970), the metallization layer comprising bridge lines (970), a pitch (P _SPARE ) of the spare standard cells being based on a pitch (P _STRAP ) of the bridge lines, each spare standard cell (970 ) has a reserved portion, the reserved portion extending across the spare standard cell (970), the bridge lines across the reserved portion being formed in one or more of the spare standard cells (970); and each reserved part is arranged such that a remaining part of the reserve standard cell (970) is not divided. semiconductor device Claim 14 , where the pitch (P _SPARE ) of the spare standard cells is a positive integer (d) evenly divisible into the pitch (P _STRAP ) of the bridge lines. semiconductor device claim 15 , where the pitch (P _SPARE ) of the reserve standard cells is a smallest positive integer (d) evenly divisible into the pitch (P _STRAP ) of the bridge lines, where the pitch P _SPARE of the reserve standard cells satisfies 2 < P _SPARE . Semiconductor device according to one of Claims 14 until 16 , where the metallization layer is M1.

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