DE102013213007A1 - Semiconductor device, trench field effect transistor, method for producing a trench field effect transistor and method for producing a semiconductor device - Google Patents

Abstract

In embodiments of semiconductor devices, dopant reservoirs are introduced into a substrate (300) and distributed by subsequent thermally induced diffusion in a region (200) to be doped. The shape and / or location of a region doped after the diffusion and thus, for example, the location of the avalanche breakdown of a trench FET can be controlled if the substrate (300) comprises a delimiting structure (100) which is at least two parallel, into the substrate ( 300) includes embedded confinement layers (110, 120) having a substantially lower dopant diffusivity than the substrate (300), wherein at least a portion of the doped region (200) is disposed between and adjacent to the parallel confinement layers (110, 120).

Description

The present invention relates to a semiconductor device and a trench field effect transistor and to methods for their production.

State of the art

Semiconductor devices, for example, power transistors are used today in a variety of applications. An example of power transistors are so-called trench field effect transistors, in short trench FETs. Trench FETs include a trench, also called a trench, in which the gate of the trench FET, the so-called trench gate, is arranged. The channel of trench FETs runs in a vertical direction along this trench gate. Trench FETs may be formed as so-called field plate trench FETs which, in addition to the trench gate, comprise one or more trench field plates disposed in the trench below the trench gate. The trench field plates are usually vertical, ie arranged parallel to the trench.

When shutting off trench FETs, in particular field-plate trench FETs, and other similar electrical or electronic components realized in semiconductors, they can transition into the state of so-called avalanche breakdown, an avalanche-like breakthrough of charge carriers in place or in places highest field strength. The location or locations of the breakthrough lie respectively at the lower end of the trench or in areas which are located laterally of the trench. Whether an avalanche breakdown occurs depends on the inductance in the so-called commutation circuit and the resulting field strength peaks.

In the case of an avalanche breakthrough, the spatial proximity of the gate or field oxides to the maximum of the impact ionization or to the holes generated during this impact ionization can lead to damage or to an incorporation of the mentioned charge carriers into the gate or field oxides. The incorporation of the charge carriers into the oxides is also referred to as "charge trapping". For frequently recurring breakthrough events, these can cause a degradation of the reverse voltage of the transistor and eventually lead to a failure of the device. For applications in which repeated breakdown events occur, therefore, components are advantageous in which corresponding charge carriers are not generated in the immediate vicinity of the oxides.

In order to control the location at which corresponding charge carriers are generated, according to the prior art a correspondingly doped dopant reservoir can be arranged in the substrate below the trench, from which dopant diffuses out in at least one subsequent thermal process step, so that a correspondingly doped region is formed in the substrate.

In other embodiments of semiconductor components, dopant reservoirs are introduced into a substrate and distributed by subsequent thermally induced diffusion in a region to be doped.

Disclosure of the invention

The inventors of the present invention have found that the shape and / or location of the diffusion-doped region, and thus, for example, the location of the avalanche breakdown, can be controlled even better if the substrate comprises a boundary structure which is at least two parallel, into the substrate comprises embedded confinement layers having a substantially lower dopant diffusivity than the substrate, wherein at least a portion of the doped region is disposed between and adjacent to the parallel confinement layers.

Therefore, a semiconductor device according to claim 1 is proposed according to the invention. In this case, the semiconductor component comprises a substrate having a doped region, wherein the doped region partly adjoins a limiting structure embedded in the substrate and is otherwise surrounded by a surrounding region in the substrate which is opposite or undoped. In this case, the limiting structure has a substantially lower dopant diffusivity than the substrate and comprises at least two parallel boundary layers embedded in the substrate. The semiconductor device according to the invention is characterized in that at least a part of the doped region is arranged between the parallel boundary layers and adjoins them in a direction parallel to a normal of the parallel boundary layers.

According to the invention, a trench field effect transistor according to claim 5 is further presented. In this case, a trench of the trench field effect transistor is arranged in a semiconductor component according to the invention such that the doped region lies directly below the trench, the limiting structure being adjacent to a gate oxide of the field effect transistor.

According to the invention, a semiconductor component according to claim 6 with inventive trench field effect transistors is presented. In this case, between each two adjacent trench field effect transistors according to the invention at least one arranged further trench field effect transistor having no doped region directly below the trench.

The confinement structure confines the doped region so that the on-resistance through the doped region is only slightly increased. In particular, the confinement structure allows the doped region to be generated by means of thermally induced dopant diffusion out of a dopant reservoir with said boundary.

In an embodiment, the delimiting structure may further comprise a delimiting element embedded in the substrate and connecting the parallel delimiting layers, wherein the part of the doped region is adjacent to the connecting delimiting element in another direction perpendicular to the normal. The connecting boundary element may be a horizontal boundary layer or have a U-shape or a V-shape.

This limits the doped region in the wider direction, thus limiting the on-resistance increase.

A remainder of the doped region may adjoin the part and at least ends of the parallel confinement layers in the further direction.

Then, the dopant reservoir can be completely formed between the parallel boundary layers. Thermally induced dopant diffusion then causes the doped region to form with a portion between the parallel confinement layers and remainder located outside the confinement structure.

At each of the first ends of the two parallel boundary layers, a further boundary element may be arranged, which extends away from the other parallel boundary layer along the normal, the rest of the doped area also being adjacent to the further boundary elements in the further direction.

This causes a particularly advantageous form of the doped region.

According to the invention, a method according to claim 7 for producing a semiconductor component and a method according to claim 10 for producing a trench field effect transistor are further provided.

The method proposed according to the invention for producing a semiconductor component comprises the step of forming a delimiting structure at least on walls of a trench in a substrate, wherein the limiting structure has a substantially lower dopant diffusivity than the substrate. Furthermore, the delimiting structure comprises at least two parallel boundary layers on walls of the trench. The method proposed according to the invention for producing a semiconductor component further comprises the steps of arranging a doped dopant reservoir in the trench between the parallel confinement layers, and performing at least one subsequent thermal process step causing diffusion of dopant from the dopant reservoir to form a doped region, wherein at least one Part of the doped region laterally adjacent to the limiting structure.

In one embodiment of the method, the boundary structure may be an oxide that is also formed at a bottom of the trench. Then, the method may further comprise the following method step: placing an oppositely doped material on the doped dopant reservoir so that the trench is filled.

Furthermore, the surface of the substrate can also be oxidized. Then, disposing the doped dopant reservoir in the oxidized trench may include the steps of: depositing a doped layer that fills the oxidized trench and covers the oxidized substrate surface; Reducing the doped layer and the oxide by abrading or etching and back etching the substrate and the doped layer to form the dopant reservoir.

In particular, placing the doped dopant reservoir in the oxidized trench may include further steps performed prior to placing the oppositely doped material in the oxidized trench on the dopant reservoir. These further steps are depositing a doped layer which fills the oxidized trench and covers the oxidized substrate surface and reducing the doped layer by selective back etching to form the dopant reservoir. Here, then, placing the oppositely doped material in the oxidized trench includes the steps of depositing an oppositely doped layer that fills the oxidized trench and covers the oxidized substrate surface, back etching the oppositely doped layer, and selectively etching the oxide.

The method proposed according to the invention for producing a trench field effect transistor comprises the following method steps: arranging an at least partially doped dopant reservoir in a trench in a substrate, wherein walls of the trench are each provided with a vertical Spacer layer are covered, forming a substantially horizontal insulating layer on the dopant reservoir by oxidation of the dopant reservoir and performing at least one subsequent thermal process step, which causes a diffusion of dopant from the dopant reservoir, so that a doped region is formed, wherein at least a portion of the doped region of the Boundary structure laterally adjacent to the vertical spacer layers and vertically to the horizontal insulation layer.

In embodiments of the method, the dopant reservoir is a selectively epitaxially deposited layer or polysilicon.

drawings

Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:

1 A first embodiment of a limiting structure for a dopant reservoir and a resulting doped region,

2 A second embodiment of a limiting structure for a dopant reservoir and a resulting doped region,

3 A third embodiment of a limiting structure for a dopant reservoir and a resulting doped region,

4 A fourth embodiment of a limiting structure for a dopant reservoir and a resulting doped region,

5 A fifth exemplary embodiment of a limiting structure for dopant reservoirs and doped regions resulting therefrom immediately below components,

6 Intermediates of a first exemplary manufacturing process of the delimiting structure according to the fifth embodiment,

7 Intermediates of a second exemplary manufacturing process of the delimiting structure according to the fifth embodiment,

8th an exemplary implantation of a dopant reservoir into a donor bottom,

9 Intermediates of a first exemplary manufacturing process of the delimiting structure according to a sixth embodiment,

10 exemplary etching of a trench spacer by means of a photoresist mask,

11 Intermediates of a second exemplary manufacturing process of the delimiting structure according to a seventh embodiment,

12 Intermediate and end product of a first variant of the first exemplary manufacturing process of the delimiting structure according to the sixth embodiment,

13 Intermediate and end products of a second variant of the first exemplary manufacturing process of the delimiting structure according to the sixth embodiment,

14 Intermediates of a first variant of the second exemplary manufacturing process of the delimiting structure according to the sixth embodiment,

15 Intermediates of a third variant of the first exemplary manufacturing process of the delimiting structure according to the sixth embodiment,

16 Intermediates of a first variant of the second exemplary manufacturing process of the delimiting structure according to the sixth embodiment,

17 Result of an exemplary epoxidation,

18 Intermediates of a Third Exemplary Production Process of the Limiting Structure According to the Sixth Embodiment

19 an exemplary arrangement of a dopant reservoir under each second trench FET of a device with multiple trench FET, and

20 Intermediates of a fourth exemplary manufacturing process of the limiting structure according to the sixth embodiment.

Embodiments of the invention

1 shows a first embodiment of a limiting structure 100 for a dopant reservoir and a resulting doped region 200 within a substrate 300 , The boundary structure 100 has two parallel boundary layers 110 . 120 on, passing through a delimiter 130 connected so that the boundary structure 100 on average appears U-shaped. The boundary structure 100 comprises a material with significantly lower dopant diffusivity than the substrate 300 , For example, the dopant diffusivity of an oxide is substantially less than the dopant diffusivity of the substrate 300 , The substratum 300 may be undoped or oppositely doped. For example, the doped region 200 p-doped and the substrate n-doped.

The endowed area 200 is partially between the parallel boundary layers 110 . 120 arranged, which form the legs of the U. Another part 210 of the doped area 200 formed by dopant diffusion from a dopant reservoir, for example, connects to between the parallel confinement layers 110 . 120 arranged portion of the area and "swells" in a sense from the boundary structure 100 out.

In 2 are the parallel boundary layers 110 . 120 unconnected, so the doped area 200 two more parts 210 . 220 which respectively emerge at the ends of the parallel boundary layers.

In 3 It is shown how, by choosing the location and the size of the dopant reservoir, it can be determined whether and on which sides of the parallel confinement layers 210 . 220 the doped area 200 emerges.

4 shows a boundary structure 200 in which the limiting element 130 one to a normal of the parallel boundary layers 110 . 120 parallel further boundary layer is. The boundary element 130 in 4 connects first ends of the parallel boundary layers 110 . 120 , At each unconnected end of the parallel boundary layers 110 . 120 is ever another, parallel to the normal boundary element arranged, which is flat and extends away from the other parallel boundary layer away.

5 shows a fifth embodiment of limiting structures 200 for dopant reservoirs and doped subsections that result directly below components 210 , In the 5 shown boundary structures 200 each comprise a limiting element 130 , one to the normal of the parallel boundary layers 110 . 120 parallel further boundary layer is. The boundary element 130 in 5 connects first ends of the parallel boundary layers 110 . 120 ,

6 shows intermediates of a first exemplary manufacturing process of the limiting element according to the fifth embodiment.

After trenches 500 in an n-doped substrate 300 were introduced, for example by etching, an oxide at least on trench walls 510 . 520 the trenches 500 educated. Im in 6 As shown, the oxide is also on trench bottoms 530 and on a substrate surface 310 educated. Then in the trenches 500 and on the oxidized substrate surface 310 a p-doped material 700 deposited or applied. The p-doped material 700 and the oxide is then ground back or etched back so that in the trenches 500 the oxide 600 as a boundary structure 100 with parallel layers 110 . 120 at the moat walls 510 . 520 and connecting limiting element 130 at the bottom of the ditch 530 remains and the trenches with trenched p-doped material 710 stay completely filled. Now become the substrate 300 and the trenched p-type material 710 partly etched back. In the trenches 500 then remains a dopant reservoir 800 back.

Subsequently, n-doped material is deposited so that the trenches 500 in a bottom area with the dopant reservoir 800 are partially filled and on the Dotierstoffreservoir 800 n-doped material is arranged, that a remaining part of the trenches 500 filled.

Subsequent process steps with a thermal budget then lead to a diffusion of the dopant from the dopant reservoir 800 , The direction of diffusion is determined by the boundary structure 100 certainly. The parallel boundary layers 110 . 120 cause the diffusion substantially perpendicular to the normal of the parallel confinement layers 110 . 120 he follows. Only when the dopant has spread so far due to the diffusion that also dopant partially outside the boundary structure 100 is located, a diffusion takes place, which is substantially uniform in all directions.

7 shows intermediates of a second exemplary manufacturing process of the limiting element according to the fifth embodiment.

After trenches 500 in an n-doped substrate 300 were introduced, for example by etching, an oxide at least on trench walls 510 . 520 the trenches 500 educated. Im in 7 As shown, the oxide is also on trench bottoms 130 and on a substrate surface 310 educated. Then in the trenches 500 and on the oxidized substrate surface 310 a p-doped material 700 deposited or applied.

In the second exemplary manufacturing process, the p-doped material is now 700 selectively etched back. In the trenches 500 then remains a dopant reservoir 800 back.

Subsequently, n-doped material is deposited so that the trenches 500 in one Ground area with the dopant reservoir 800 are partially filled and on the Dotierstoffreservoir 800 n-doped material is arranged, that a remaining part of the trenches 500 filled. The n-doped material further covers that on the substrate surface 310 formed part of the oxide 600 , The n-doped material is etched back to the on the substrate surface 310 formed part of the oxide 600 exposed. Subsequently, the on the substrate surface 310 formed part of the oxide 600 etched selectively so that the substrate surface 310 again exposed. The trenches 500 are then in a bottom area with the dopant reservoir 800 partially filled and on the dopant reservoir 800 is arranged n-doped material, that a remaining part of the trenches 500 filled.

Subsequently, again n-doped material is deposited, so that the boundary structure 100 including the contained dopant reservoir 800 completely surrounded by n-doped material.

Subsequent process steps with a thermal budget then lead, as in the first exemplary embodiment of a production process, to a diffusion of the dopant from the dopant reservoir 800 , The direction of diffusion is determined by the boundary structure 100 certainly. The parallel boundary layers 110 . 120 cause the diffusion substantially perpendicular to the normal of the parallel confinement layers 110 . 120 he follows. Only when the dopant has spread so far due to the diffusion that also dopant partially outside the boundary structure 100 is located, a diffusion takes place, which is substantially uniform in all directions.

8th shows an exemplary implantation of a dopant reservoir into a trench bottom.

9 shows intermediates of a first exemplary manufacturing process of the boundary structure 100 according to a sixth embodiment. After etching a trench 500 becomes a trench spacer 600 , For example, an oxide, at least on trench walls 510 . 520 the trenches 500 educated. Im in 9 The example shown is the oxide 600 also on trench bottoms 130 and on a substrate surface 310 educated. The spacer 600 is opened on the ground so that two parallel and unconnected boundary layers 110 . 120 at the moat walls 510 . 520 arise and the substrate 300 on the ground 530 of the trench 500 is exposed again. Each of the parallel boundary layers 110 . 120 has at its upper end a further limiting element. The further limiting element 140 is parallel to the normal of the parallel boundary layers 110 . 120 and extends from the respective other parallel boundary layer 110 . 120 path. Finally, a dopant reservoir 800 selectively epitaxially on the ground 530 of the trench 500 exposed substrate 300 deposited.

Opening the spacer 600 at the bottom of the ditch 530 can, for example, as in 10 shown by etching with the aid of a photoresist mask 900 happen. The photoresist mask protects the part of the oxide 600 that is on the substrate surface 310 and at the moat walls 510 . 520 is arranged, before the etching.

11 shows intermediates of a second exemplary manufacturing process of the limiting structure according to a seventh embodiment. To produce a thicker oxide 600 an implantation is performed in an implantation direction that is neither parallel nor perpendicular to the normal of the parallel trench walls 510 . 520 of the trench 500 is. For example, the angle between the direction of implantation and the normal may be between 30 and 60 degrees, with 360 degrees corresponding to the full circle. For example, the angle between the direction of implantation and the normal can be 45 degrees. When the moat walls 510 . 520 perpendicular to the substrate surface is then an angle between the implantation direction and a normal to the substrate surface also 45 degrees.

The oblique implantation causes damage to the substrate or introduction of oxygen, which at the substrate surface 310 and at upper ends of the parallel trench walls 510 . 520 which is an opening of the trench 500 form more pronounced than at the trench bottom 530 , Subsequent thermal oxidation then leads to correspondingly different thicknesses of the oxide 600 on the substrate surface 310 and at the bottom of the ditch 530 , Now if the oxide 600 etched without photoresist mask until the trench bottom 530 Once again, the thickness of the oxide is reduced 600 on the substrate surface 310 but there remains a residue of the oxide 600 on the substrate surface.

12 shows intermediate and end product of a first variant of the first exemplary manufacturing process of the limiting structure according to the sixth embodiment. On the re-exposed trench ground 530 becomes a dopant reservoir 800 epitaxially in the ditch 500 deposited so that the trench bottom of the dopant reservoir 800 is covered. Laterally adjoins the dopant reservoir 800 to the parallel boundary layers 110 . 120 at. Subsequently, a surface of the Dotierstoffreservoirs 800 oxidized, leaving a limiting element 130 is formed, which the parallel boundary layers 110 . 120 combines. This step and / or subsequent process steps with thermal budget then lead to a Diffusion of the dopant from the dopant reservoir 800 , The resulting structure can be used, for example, for realizing a trench FET, as shown in FIG 12 is shown. Then, the limiting structure adjoins a gate oxide of the trench FET. Above the boundary element 130 is then in the ditch 500 a substantially rectangular field plate 910 arranged. The field plate 910 is through another oxide layer 150 from a gate arranged above it 920 the trench FET separated, which is also arranged in the trench. Lateral next to the gate 920 is located on the example n-doped substrate a p-doped layer 930 in which the channel of the trench FET can form. Above the boundary element 130 is then in the ditch 500 a field plate arranged. The field plate 910 is through another oxide layer 150 from a gate arranged above it 920 the trench FET separated, which is also arranged in the trench. Lateral next to the gate 920 is located on the example n-doped substrate 300 a highly p-doped layer 930 (p ^- layer), which may be epitaxially grown or implanted and serves as a source terminal. On a part of the p ^- layer 930 is a highly n-doped layer 940 arranged (n ⁺ source), which may be epitaxially grown or implanted and. In addition to the n ⁺ source 940 is a p ⁺ terminal 950 (p ⁺ -plug) into the p ^- layer 930 implanted, leaving a top of the p ⁺ -plug 950 a top of the n ⁺ source 940 surmounted and the p ⁺ -plug 950 can serve to define the channel potential.

13 shows intermediate and end products of a second variant of the first exemplary manufacturing process of the limiting structure according to the sixth embodiment. In the second variant, the oxide is after epitaxial deposition of the dopant reservoir 800 away. Then, a surface of the dopant reservoir 800 and the trench walls oxidized, so that the parallel boundary layers 110 . 120 and the connecting delimiter 130 be formed. The resulting structure can be used, for example, for realizing a trench FET, as shown in FIG 13 is shown.

The exemplary manufacturing steps from the 12 and 13 can also be combined. This in 14 shown. On the re-exposed trench ground 530 becomes a dopant reservoir 800 epitaxially in the ditch 500 deposited so that the trench bottom of the dopant reservoir 800 is covered. Laterally adjoins the dopant reservoir 800 to the oxide 600 at. Subsequently, a surface of the Dotierstoffreservoirs 800 oxidized. This is a first thermal budget process step that involves diffusion of dopant from the dopant reservoir 800 in the substrate 300 causes. The oxide 600 on the trench walls and on the surface of the dopant reservoir 800 is then removed again. This is a second thermal budget process step that involves further diffusion of dopant into the substrate 300 causes.

When the ditch 500 has a width that is significantly larger than a width of the dopant reservoir 800 is because on the parallel trench walls 510 . 520 a thick layer of the oxide 600 is present, then the removal of the oxide 600 to that too the trench bottom 530 is partially exposed. Subsequent re-oxidation will then cause the parallel confinement layers 110 . 120 not to the parallel trench walls 510 . 520 adjoin. Rather, the parallel boundary layers 110 . 120 with oxide to the parallel trench walls 510 . 520 by oxide on the partially exposed trench bottom 530 connected. On both sides of the through the parallel boundary layers 110 . 120 limited dopant reservoir 800 there are depressions. This allows the arrangement of a field plate 910 in horseshoe shape or U-shape. These are thighs 911 the field plate 910 laterally next to the through the parallel boundary layers 110 . 120 limited p-doped area 200 , which by diffusion from the Dotierstoffreservoir 800 originated, positioned. That's the thighs 911 connecting element of the field plate is then above the connecting boundary element 130 , which in turn is above the p-doped region 200 located.

16 shows intermediates of a first variant of the second exemplary manufacturing process of the limiting structure according to the sixth embodiment. A ditch 500 is in a substrate 300 created and then an oxide 600 on trench walls 510 . 520 , Trench bottom 530 and substrate surface 310 educated. The oxide 600 on the substrate surface 310 and the trench bottom 530 will be removed again. Then, selectively epitaxially becomes p-doped material 700 on the substrate surface 310 and the trench bottom 530 deposited. Subsequently, this is done on the substrate surface 310 deposited p-doped material 700 ground back until the substrate surface 310 again exposed. The one on the ditch floor 530 deposited part of the p-doped material 700 remains and forms the dopant reservoir 800 ,

Subsequently, for example, an oxidation of the substrate surface 310 (EPI surface) and a surface of the dopant reservoir 800 take place, which is a diffusion of dopant from the reservoir into the substrate 300 and forming a delimiter 130 causes. This is exemplary in 17 shown.

18 shows intermediates of a third exemplary manufacturing process of the limiting structure according to the sixth embodiment. A ditch 500 is in a substrate 300 created and then an oxide 600 on trench walls 510 . 520 , Trench bottom 530 and substrate surface 310 educated. The oxide 600 on the ditch floor 530 will be removed again. Then, polysilicon on the oxidized substrate surface and the exposed trench bottom 530 deposited. Subsequently, the polysilicon on the oxidized substrate surface 310 completely etched back in the trench so that some of the deposited polysilicon on the trench bottom 530 remains and the dopant reservoir 800 can form.

For devices comprising multiple trench FETs, it may be sufficient for every second trench FET to have a p-doped region 200 below the gate 920 having. This is exemplary in 19 shown.

Additionally or alternatively, structuring along a longitudinal direction of the trench can also take place. This can be achieved, for example, via a lacquer mask which is only partially opened above the trench. Then the oxide at the bottom of the trench 530 longitudinally removed only in the opened sections. Between the sections where the oxide is removed, oxide remains at the bottom of the trench 530 ,

Now a layer on the trench bottom 530 grown selectively epitaxially, the layer thickness is greater than the thickness of the remaining oxide, it may partially come to overgrowth of the oxide. This can be prevented, for example, by the fact that the oxide is a deposited oxide, on which no epitaxial growth is possible. For example, in the trench first an oxide is formed on trench walls and trench bottom, and then the trench is completely filled up with deposited oxide. Then the deposited oxide is etched back. The remaining oxide is masked in sections by means of a resist mask and the unmasked portions are anisotropically etched until the trench bottom is exposed in the corresponding sections. Now the resist mask is removed and selectively deposited epitaxially p-doped material. After removal of the resist mask and the oxide remain in the longitudinal direction spaced apart dopant reservoirs 800 ,

In order to produce a semiconductor component, for example a trench FET, in a substrate which is also referred to as a semiconductor material, a trench may, for example, be formed within the semiconductor material, which is subsequently lined over the whole area with an insulator layer, for example an oxide, which is also referred to as a spacer. Then, a limiting structure may be formed in a lower portion of the semiconductor device. In this case, the limiting structure is designed to limit diffusion of dopant laterally or to completely prevent it. Finally, at least one dopant can be introduced into the limiting structure.

In particular, the delimiting structure can be formed by creating an opening in the insulator layer at the trench bottom. The dopant may, for example, be introduced by selectively applying the at least one dopant into the opening in the insulator layer on the trench bottom. In particular, the application can be carried out selectively epitaxially. The opening in the spacer can take place with the aid of a structured photoresist mask with the aid of which the insulator layer is etched.

Claims (12)

Semiconductor device comprising a substrate ( 300 ) with a doped area ( 200 ), the doped area ( 200 ) partially to one in the substrate ( 300 ) embedded bounding structure ( 100 ) and otherwise from a surrounding area in the substrate ( 300 ), which is opposite or undoped, and wherein the boundary structure ( 100 ) has a much lower dopant diffusivity than the substrate ( 300 ), the boundary structure ( 100 ) at least two parallel into the substrate ( 300 ) embedded boundary layers ( 110 . 120 ), characterized in that at least a part of the doped region ( 200 ) between the parallel boundary layers ( 110 . 120 ) and in a direction parallel to a normal of the parallel boundary layers ( 110 . 120 ) adjacent to them. Semiconductor component according to Claim 1, the limiting structure ( 100 ) further into the substrate ( 300 ) embedded and the parallel boundary layers ( 110 . 120 ) connecting boundary element ( 130 ), the part of the doped region ( 200 ) in a further, perpendicular to the normal direction of the connecting boundary element ( 130 ) borders. A semiconductor device according to claim 1 or 2, wherein a remainder of the doped region ( 200 ) in an extension direction of the parallel boundary layers (FIG. 110 . 120 ) to the first part and at least at the ends of the parallel boundary layers ( 110 . 120 ) adjoins. A semiconductor device according to claim 3, wherein at first ends of the two parallel confinement layers ( 110 . 120 ) each one to Normal parallel boundary element ( 140 ), which extends from the other parallel boundary layer ( 110 . 120 ), the remainder of the doped region ( 200 ) in the further direction also to the other limiting elements ( 140 ) adjoins. Trench field effect transistor, wherein a trench ( 500 ) of the trench field effect transistor is arranged in a semiconductor component according to one of the preceding claims such that the doped region ( 200 ) directly below the trench ( 500 ), and wherein the boundary structure ( 100 ) is adjacent to a gate oxide of the field effect transistor. Semiconductor device with trench field effect transistors according to claim 5, wherein between each two adjacent trench field effect transistors according to claim 5, at least one further trench field effect transistor is arranged, the no doped region ( 200 ) directly below the trench ( 500 ) having. Method for producing a semiconductor component, the method comprising the following method steps: - forming a limiting structure ( 100 ) at least on walls of a trench ( 500 ) in a substrate ( 300 ), the boundary structure ( 100 ) has a much lower dopant diffusivity than the substrate ( 300 ) and the boundary structure ( 100 ) at least two parallel in the substrate ( 300 ) boundary layers ( 110 . 120 ) on walls ( 510 . 520 ) of the trench ( 500 ); Arranging a doped dopant reservoir ( 800 ) in the ditch ( 500 ) between the parallel boundary layers ( 110 . 120 ), and - performing at least one subsequent thermal process step, which is a diffusion of dopant from the dopant reservoir ( 800 ), so that a doped area ( 200 ), whereby at least a part of the doped region ( 200 ) to the boundary structure ( 100 ) laterally adjoins. Method according to claim 7, wherein the boundary structure ( 100 ) from an oxide ( 600 ) and also on a floor ( 530 ) of the trench ( 500 ) and the method further comprises the following method steps: arranging (S5) an oppositely doped material on the doped dopant reservoir ( 800 ), so that the trench ( 500 ) is filled. Method according to claim 7, wherein the boundary structure ( 100 ) from an oxide ( 600 ) and wherein also a surface of the substrate ( 300 ) is oxidized and arranging the doped Dotierstoffreservoirs ( 800 ) in the oxidized trench ( 500 ) comprises the following steps: deposition of doped material ( 700 ), the oxidized trench ( 500 ) and the oxidized substrate surface ( 310 covered); Reduction of the doped material ( 700 ) and the oxide ( 600 by abrasion or etching and etching back of the substrate ( 300 ) and the doped material ( 700 ) for forming the dopant reservoir ( 800 ). Method according to claim 8, wherein also a substrate surface ( 310 ) is oxidized and arranging the doped Dotierstoffreservoirs ( 800 ) in the oxidized trench ( 500 ) comprises the steps of prior to placing (S5) the oppositely doped material in the oxidized trench ( 500 ) on the dopant reservoir ( 800 ): - deposition of doped material ( 700 ), the oxidized trench ( 500 ) and the oxidized substrate surface ( 310 ) and reducing the doped material ( 700 ) by selective etching back to form the dopant reservoir ( 800 ); - placing the oppositely doped material in the oxidized trench ( 500 ) comprises the steps of: depositing an oppositely doped layer comprising the oxidized trench ( 500 ) and the oxidized substrate surface ( 310 covered); - back etching of the oppositely doped layer and - selective etching of the oxide ( 600 ). Method for producing a trench field effect transistor, the method comprising the following method steps: arranging an at least partially doped dopant reservoir ( 800 ) in a ditch ( 500 ) in a substrate ( 300 ), where walls ( 510 . 520 ) of the trench ( 500 ) each with a vertical spacer layer ( 110 . 120 ), - forming a substantially horizontal insulating layer ( 130 ) on the dopant reservoir ( 800 ) by oxidation of the dopant reservoir ( 800 ) and - performing at least one subsequent thermal process step, which is a diffusion of dopant from the dopant reservoir ( 800 ), so that a doped area ( 200 ), whereby at least a part of the doped region ( 200 ) to the boundary structure ( 100 ) laterally to the vertical spacer layers ( 110 . 120 ) and vertically to the horizontal insulation layer ( 130 ) adjoins. A method according to claim 11, wherein the dopant reservoir ( 800 ) is applied selectively epitaxially or is a polysilicon.

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