DE102013107244B4 - Stacked fan-out semiconductor chip - Google Patents

Abstract

Semiconductor component, comprising:• a base layer (101, 601, 701) with a first semiconductor chip (105), the first semiconductor chip (105) having at least one electrically conductive contact (106) on a first side (107) of the first semiconductor chip (105) has;• a first electrically insulating layer (109) on the base layer (101, 601, 701);• a first redistribution layer (111) which contacts the at least one electrically conductive contact (106) of the first semiconductor chip (105), wherein the first redistribution layer (111) extends beyond the boundaries of the first semiconductor chip (105) and is arranged over the first electrically insulating layer (109);• a second semiconductor chip (114) having a first side (115) and a second side (116) , wherein the second semiconductor chip (114) has at least one electrically conductive contact (106) on the first side (115) of the second semiconductor chip (114);• a structured adhesive layer (113) arranged z wiping the first side (107) of the first semiconductor chip (105) and the second side (116) of the second semiconductor chip (114), the second semiconductor chip (114) being arranged directly on the adhesive layer (113) and the adhesive layer (113) is at least partially arranged directly on the first redistribution layer (111) and the first electrically insulating layer (109);• an additional electrically insulating layer (119) arranged at least partially over the first side (115) of the second semiconductor chip (114), wherein the additional electrically insulating layer (119) has at least one via (123), so that the first redistribution layer (111) is exposed; and• a second redistribution layer (127) which contacts at least one electrically conductive contact (106) of the second semiconductor chip (114), wherein the second redistribution layer (127) is electrically connected to the first redistribution layer (111) by means of the at least one via (123 ).

Description

In various embodiments, a stacked, fan-out semiconductor chip (also referred to as a fan-out semiconductor chip) and a method of manufacturing a stacked, fan-out semiconductor chip are provided.

Various solutions for stacking semiconductor chips are known. For this purpose, reference is made to U.S. 2008/0 174 008 A1 , the U.S. 7,321,164 B2 , the DE 10 2004 049 356 A1 , the U.S. 7,858,440 B2 and the U.S. 2011/0 084 402 A1 .

In a wirebond stack, one chip can be stacked on top of another chip, with the electrical contacts between the two chips being made by wire bonding. Such wire bond stacks can have large dimensions and limited electrical performance. In a flip chip wirebond stack, solder balls can be placed on top of a chip and the chip can be flipped over so that the top (with the solder balls) can contact electrical contacts positioned on a substrate. A wire bonded chip can then be attached to the bottom of a flip chip, forming a stack. Other chips stacked on the package require wire bonding, resulting in large package size and limited electrical performance. In through silicon via (TSV) chip stacks, vias may extend (from the active side of a chip) through the chip to form an electrical connection to the inactive side of the chip. However, TSV technology is expensive and the supply chain for TSV chips is still evolving. What is needed is chip stacking technology that is potentially less expensive and results in a chip assembly that can be relatively small and has improved electrical performance.

The resulting problem is solved by the subject matter of independent claims 1 and 10.

According to the invention, a semiconductor device that is or will be formed using chip stacking technology has a plurality of layers: a base layer with a first semiconductor chip, the first semiconductor chip having at least one electrically conductive contact on a first side of the first semiconductor chip; a first electrically insulating layer on the base layer, a first redistribution layer contacting the at least one electrically conductive contact of the first semiconductor chip, the first redistribution layer being able to extend beyond the boundaries of the first semiconductor chip; and disposed over the first electrically insulating layer is a second semiconductor chip having a first side and a second side, the second semiconductor chip having at least one electrically conductive contact on the first side of the second semiconductor chip; and a patterned adhesive layer arranged between the first side of the first semiconductor chip and the second side of the second semiconductor chip, wherein the second semiconductor chip is arranged directly on the adhesive layer and wherein the adhesive layer is at least partially directly on the first redistribution layer and the first electrically insulating layer is arranged.

The semiconductor device further includes: an electrically insulating layer at least partially disposed over the first side of the second semiconductor die, wherein the electrically insulating layer may include at least one via such that the first redistribution layer is exposed; and a second redistribution layer contacting at least one electrically conductive contact of the second semiconductor chip, wherein the second redistribution layer may be electrically connected to the first redistribution layer by means of the at least one via. At least one solder ball can contact the second redistribution layer.

The semiconductor component can have multiple layers. For example, the semiconductor device may include: a third semiconductor chip having a first side and a second side, the third semiconductor chip having at least one electrically conductive contact on the first side of the third semiconductor chip; a second adhesive layer disposed between the first side of the second semiconductor die and the second side of the third semiconductor die, wherein the third semiconductor die may be disposed directly on the second adhesive layer; a second electrically insulating layer disposed at least partially over the first side of the third semiconductor die, wherein the second electrically insulating layer may include at least one via such that the second redistribution layer is exposed; and a third redistribution layer contacting the at least one electrically conductive contact of the third semiconductor chip, wherein the third redistribution layer may be electrically connected to the second redistribution layer by means of the at least one via of the second electrically insulating layer.

In various aspects, the base layer may be a reconstituted wafer and the first semiconductor die incorporated into the reconstituted wafer be bedded A plurality of semiconductor chips can also be embedded in the reconstituted wafer. The plurality of semiconductor chips can have at least one passive semiconductor chip and at least one active semiconductor chip.

The first semiconductor chip and the second semiconductor chip may form a single integrated circuit package. In various aspects, the second semiconductor die may be non-detachable from the single integrated circuit package without damaging the package.

In further aspects, the adhesive layer can be at least partially arranged on the first redistribution layer. The first semiconductor chip and the second semiconductor chip can be integrated circuits.

In further aspects, the semiconductor device may include: at least one wire electrically connecting the at least one electrically conductive contact of the second semiconductor chip to the first redistribution layer; and an electrically insulating layer disposed at least partially over the first side of the second semiconductor chip and the at least one wire, wherein the electrically insulating layer may include at least one via such that the first redistribution layer is exposed.

Also described herein as a comparative example is a semiconductor device comprising: a base layer including a first semiconductor chip, the first semiconductor chip having at least one electrically conductive contact on a first side of the first semiconductor chip; a first redistribution layer contacting the at least one electrically conductive contact of the first semiconductor chip, wherein the first redistribution layer may extend beyond the boundaries of the first semiconductor chip; and a semiconductor flip chip having a first side and a second side, the semiconductor flip chip having at least one electrically conductive contact on the first side of the semiconductor flip chip. The first side of the first semiconductor chip may face the first side of the semiconductor flip chip. The semiconductor device may further include: an electrically insulating layer disposed at least partially over the second side of the semiconductor flip chip, wherein the electrically insulating layer may include at least one via such that the first redistribution layer is exposed; and a second redistribution layer electrically contacting the at least one electrically conductive contact of the semiconductor flip chip through the at least one via and the first redistribution layer.

A method of manufacturing a semiconductor device is also described herein. According to the invention, the method has: forming a first redistribution layer over a first electrically insulating layer on a surface of a base layer with a first semiconductor chip, the first semiconductor chip having at least one electrically conductive contact on a first side of the first semiconductor chip, the first redistribution layer having the can contact at least one electrically conductive contact of the first semiconductor chip; applying a patterned adhesive layer at least partially directly to a surface of the first redistribution layer and the first electrically insulating layer; arranging a second semiconductor chip directly on the adhesive layer; applying a polymer layer around the second semiconductor chip; forming at least one via through the polymer layer, wherein the at least one via may expose the first redistribution layer; and forming a second redistribution layer on a surface of the polymer layer. The second semiconductor chip may include at least one electrically conductive contact on a first side of the second semiconductor chip, wherein arranging the second semiconductor chip may include arranging a second side of the second semiconductor chip on the adhesive layer, the second side being different from the first side. The method may further include: forming an electrically insulating layer at least partially on the first side of the second semiconductor chip; and forming at least one via through the electrically insulating layer, wherein the at least one via can expose the first redistribution layer.

In various aspects, the method may further include forming a second redistribution layer on the electrically insulating layer, wherein the second redistribution layer may electrically connect the at least one electrically conductive contact of the second semiconductor chip to the first redistribution layer by means of the at least one via. The method may further include placing at least one solder ball on the second redistribution layer.

The method may include: applying a second adhesive layer at least partially on a surface of the second redistribution layer; placing a third semiconductor chip on the second adhesive layer; forming a second electrically insulating layer at least partially on the third semiconductor chip; forming at least one via through the second electrically insulating layer, wherein the at least one via of the second electrically insulating layer exposes the second redistribution layer; and forming a third redistribution layer on the second electrically insulating layer, wherein the third redistribution layer may electrically connect at least one electrically conductive contact of the third semiconductor chip to the second redistribution layer via the at least one via of the second electrically insulating layer.

The procedure may include: sanding the base layer to remove excess material. In various aspects, the base layer can be a reconstituted wafer and the first semiconductor die embedded in the reconstituted wafer. The method may further include: electrically connecting at least one electrically conductive contact of the second semiconductor chip to the first redistribution layer by means of a wire before the polymer layer is or will be applied.

These and other aspects of the disclosure are illustrated in light of the following detailed description.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific aspects in which the invention may be practiced. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

• 1a-k Beispiele seitlicher Querschnittsansichten eines Halbleiterbauelementes (oder Teilen davon) und/oder ein Beispiel für ein Verfahren zum Herstellen eines Halbleiterbauelementes gemäß einem oder mehreren beschriebenen Aspekten;
• 2 ein weiteres Beispiel einer seitlichen Querschnittsansicht eines Halbleiterbauelementes (oder eines Teils davon) gemäß einem oder mehreren beschriebenen Aspekten;
• 3 ein weiteres Beispiel einer seitlichen Querschnittsansicht eines Halbleiterbauelementes (oder eines Teils davon) gemäß einem oder mehreren beschriebenen Aspekten;
• 4a-e Vergleichsbeispiele seitlicher Querschnittsansichten eines Halbleiterbauelementes (oder Teilen davon) mit einer Flip-Chip-Anordnung und/oder ein Beispiel für ein Verfahren zum Herstellen eines Halbleiterbauelementes mit einer Flip-Chip-Anordnung, in denen sich auch einige der hierin beschriebenen Aspekte wiederfinden;
• 5a-d Beispiele seitlicher Querschnittsansichten eines Halbleiterbauelementes (oder Teilen davon) mit Drähten und/oder ein Beispiel für ein Verfahren zum Herstellen eines Halbleiterbauelementes mit Drähten gemäß einem oder mehreren beschriebenen Aspekten;
• 6a-c Vergleichsbeispiele seitlicher Querschnittsansichten eines Halbleiterbauelementes (oder Teilen davon) mit aktiven und/oder passiven Komponenten und/oder ein Beispiel für ein Verfahren zum Herstellen eines Halbleiterbauelementes mit aktiven und/oder passiven Komponenten gemäß einem oder mehreren beschriebenen Aspekten; und
• 7 ein weiteres Vergleichsbeispiel einer seitlichen Querschnittsansicht eines Halbleiterbauelementes (oder einem Teil davon) mit aktiven und/oder passiven Komponenten, in dem sich auch einige der hierin beschriebenen Aspekte wiederfinden.

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• 1a-k Examples of side cross-sectional views of a semiconductor device (or parts thereof) and/or an example of a method for manufacturing a semiconductor device according to one or more aspects described;
• 2 another example of a side cross-sectional view of a semiconductor device (or a part thereof) according to one or more described aspects;
• 3 another example of a side cross-sectional view of a semiconductor device (or a part thereof) according to one or more described aspects;
• 4a-e Comparative examples of side cross-sectional views of a semiconductor device (or parts thereof) with a flip-chip structure and/or an example of a method for manufacturing a semiconductor device with a flip-chip structure, which also reflect some of the aspects described herein;
• 5a-d Examples of side cross-sectional views of a semiconductor device (or parts thereof) with wires and/or an example of a method for producing a semiconductor device with wires according to one or more described aspects;
• 6a-c Comparative examples of side cross-sectional views of a semiconductor device (or parts thereof) with active and/or passive components and/or an example of a method for manufacturing a semiconductor device with active and/or passive components according to one or more described aspects; and
• 7 a further comparative example of a side cross-sectional view of a semiconductor device (or a part thereof) with active and/or passive components, which also reflects some of the aspects described herein.

It is understood that one or more figures are not necessarily drawn to scale.

1a-k 12 show examples of side cross-sectional views of a semiconductor device (or parts thereof) and/or an example of a method for manufacturing a semiconductor device according to one or more described aspects. In 1a a base layer 101 (substrate) is provided. The base layer 101 may be a reconstituted wafer, such as a reconstituted wafer with a fan-out region (also referred to as a fan-out region) (e.g., a wafer level ball (WLB) or an embedded wafer level ball (WLB)) . The reconstituted wafer may be formed by means of selecting a plurality of semiconductor devices 105, which may be represented for example as chips 105-1 and 105-2, which are known to be good and/or which have been tested as good (e.g functioning). The semiconductor devices 105 can be taken from a wafer on which the chips 105 have been formed (e.g. by dicing the silicon wafer) and arranged on a carrier by means of an adhesive film. The chips 105 can be face up (the active side of the chips 105 with electrically conductive (e.g. metal) contacts 106 facing up) on the carrier or face down (e.g. the active side of the chips with electrically conductive contacts 106 pointing downwards) to form a first layer of semiconductor chips 105 . The density of the chips 105 can be greater in the original silicon wafer than the intended density of the chips 105 on the reconstituted wafer 101, for example if the distance between the chips 105 in the original silicon wafer is smaller than the distance between the chips 105 in the base layer 101 The chips 105 removed from the original silicon wafer may be or will be placed on the carrier at a greater distance from each other than the chips 105 were placed on the original silicon wafer. A fan-out region may be formed by spreading the chips 105, as will be described in more detail in the examples below.

An electrically insulating layer 103, for example a molding compound, can be formed around the chips 105 or can be used to form a base layer 101. For example, the base layer may be formed by compression molding to produce a round wafer, a rectangular wafer, or any other shaped wafer. Thus, the semiconductor chips 105 can be at least partially embedded in the base layer 101 by means of the molding method. The electrically conductive contacts 106 may be exposed using any conventional method available to one skilled in the art. For example, the contacts 106 can be exposed using grinding, laser removal, and/or a combination of grinding and laser removal of the insulating layer 103. The base layer 101 can be used as a starting point for a stack and additional layers and/or chips. This makes an additional carrier system for semiconductor chips optional.

Semiconductor chips 105 embedded in the reconstituted wafer may have a first side 107 with a plurality of electrically conductive contacts 106 . The first side 107 may also be referred to as the top, regardless of actual orientations with respect to gravity or the rest of the device. The contacts can be made by applying one electrically conductive material, for example polycrystalline silicon and/or metal, for example aluminum; be or will be formed on a semiconductor chip 105 . Contacts 106 may also be of a metal structure such as copper as a cylinder, column, or other structure; be fully or partially covered. An exemplary metal structure may be 7 to 20 μm thick, for example. The metal structure can protect the contacts 106 during the removal of layers and/or material from the semiconductor die, for example during laser drilling. Some layers and/or material removal methods, such as photolithography, do not require metal structures to protect the contacts 106. Therefore, metal structures need the contacts 106 if the electrically insulating layer 109 is patterned using photolithography, as will be described in more detail in examples below. Each of the chip contacts described below may similarly include metal structures to cover the contacts and protect them during layer and/or material removal. The contacts may have been formed as part of the process of forming the original silicon wafer. In various configurations, the bare contacts 106 may not be solderable because the redistribution layers, passive layers, solder stops, and/or solder balls were not formed on the reconstituted wafer 101 . Semiconductor chips 105 may also have a second opposite side 108, for example a "bottom side"), which does not have electrical contacts.

In 1b An electrically insulating layer 109 (e.g., a dielectric layer) may be formed on a reconstituted wafer 101 . The contacts 106 may be exposed, for example by using photolithography and/or a laser process. Metallization extensions 110 formed of copper or other conductive material may be or will be formed on the exposed contacts 106. FIG. A first redistribution layer 111 may be formed over the dielectric 109 . The first redistribution layer 111 may include a plurality of redistribution lines, at least a portion of which extend across the boundaries of a plurality of semiconductor chips and form a fan-out region in the region between the chips 105 . By fanning out the contacts 106 outside of the package footprint of each chip 105, the contacts 106 may be more easily accessible, for example to other semiconductor chips and/or other types of components, contacts, etc. Redistribution layers may be or are formed using various thin film and/or Printed circuit board (PCB) deposition processes, including sputtering and plating, electroless nucleated layer deposition, electroplating, printing and/or other deposition processes.

In 1c An adhesion layer 113 may be formed over the first semiconductor chip 105 layer (e.g. by means of printing, lamination, dispensing, etc.), as well as on the dielectric 109 and/or the first redistribution layer 111. Parts of the first redistribution layer 111 may be left exposed in order to to enable chip stacking. For example, adhesives pick-and-place areas of the second layer of semiconductor chips, as will be described in more detail in the examples below. Adhesives can include, for example, epoxy, polyimide, silicone, other materials, and combinations thereof. Furthermore, the adhesives can be filled or unfilled with a filler, such as silicon and carbon, among other types of fillers. The adhesive layer 113 is shown as a structured layer; the adhesive layer 113 can be a closed layer between the chips 105 . Furthermore, the boundaries of the adhesive layer 113 may be at or within the package footprint of each die 105, or the adhesive layer may extend (laterally) beyond the package footprint of each die 105.

In 1d For example, a second layer of semiconductor chips 114, illustrated for example as chips 114-1 and 114-2, may be or will be disposed directly on the adhesive 113. Pick and place positioning equipment can be used. The second semiconductor chips 114 can each have a first side 115, for example a top side, with a plurality of electrically conductive contacts. metallization extensions 117 formed, for example, of copper or other conductive materials; may be formed on the contacts of the second semiconductor chip 114, in the same or a similar manner as the first layer of semiconductor chips 105. In various configurations, the metallization extensions 117 may be pre-deposited on the contacts of the chips 117, for example in the form of Copper under bump metallization (UBM). The second chips 114 may also each have a second side 116 (e.g., a bottom) that may have non-conductive contacts. The second side 116 can be placed directly on the adhesive 113 .

In 1e An electrically insulating layer 119 (e.g. a molding layer or a lamination layer) may be formed around the second semiconductor chip(s) 114 such that the second chip(s) 114 is at least partially embedded are in the insulating layer 119. The insulating layer 119 may be formed by any semiconductor manufacturing process such as lamination, compression molding, printing, etc. In 1F , the insulating layer 119 can be reduced in size (e.g. thinned), e.g. by means of grinding and/or laser drilling of the insulating layer 119. Grinding of the insulating layer 119 (e.g. to a region 121) can extend the conductive extension 117 of the second semiconductor chip(s). 114 expose.

In 1g one or more via(s) 123, for example interconnect pathways, may be formed in the electrically insulating layer 119, for example by means of drilling (for example laser drilling) and/or a photolithographic process. The via 123 may expose the conductive extensions 117 of the second semiconductor chips 114 and/or the first redistribution layer 111 . For example, the drilling may stop at the first redistribution layer 111 and/or one or more conductive extensions 117 .

In 1 hour For example, the vias 123 may be filled with one or more conductive materials 125, such as copper, to allow electrical access to the first redistribution layer 111 and/or conductive extensions 117 of the second semiconductor chips 114. A second redistribution layer 127 may also be formed over the molding layer 119, for example by sputtering and plating, electroless seeding, or electroplating. In various configurations, the vias 123 can be filled together with the formation of the redistribution layer 127 . Alternatively, the vias 123 can be filled independently of the formation of the redistribution layer 127 . For example, vias 123 may be filled first, such as by printing, electroless plating, etc. Then redistribution layer 127 may be formed. The vias 123 may be fully or partially filled with conductive material. Partially filled vias may be plugged vias, with some sort of redistribution layer passed down through the vias, and the rest of the via being filled separately or by means of an electrically insulating material, e.g. a second electrically insulating layer 129, as more fully described described in examples below. The second redistribution layer 127 may form a second fan-out connection area of the conductive contacts of the first and second semiconductor chips. For example, the contacts may fan out outside of the package footprint of each of the first semiconductor chips 105, outside of the package footprint of each of the second semiconductor chips 114, and/or outside of the package footprints of both the first and second semiconductor chips 105, 114. The second redistribution layer 127 may be electrical with the first Redistribution layer 111 be connected by means of the conductive material (s) 125, which fills the at least one via 123. The second redistribution layer 127 may similarly be electrically connected to one or more conductive contacts of the second semiconductor chips 114. In various configurations, the electrical connection between the second redistribution layer 121 and the first redistribution layer 111 and/or the conductive extension 117 may not require soldering. This can potentially simplify the manufacturing process for forming the semiconductor device and/or potentially increase the resistance of the semiconductor device, for example resistance to high heat.

In 1i , a second electrically insulating layer 119, for example a dielectric, can be or will be formed on the second redistribution layer 127. The second redistribution layer 127 may be exposed in one or more regions 131 (e.g. via laser drilling, photolithography, etc.). In 1y , a solder stop layer and/or solder balls 133, for example balls or hemispheres, can be or will be applied. In 1k For example, the underside of the base layer 101, e.g. the molding compound 103, directed away from the side on which the solder balls 133 are or will be applied, may be ground to reduce the height of the structure, e.g. to position 135. The structure may then singulated, e.g. diced, between each of the stacked array of chips and/or other components, e.g. in the area shown by the dashed line in 1k , whereby a plurality of isolated semiconductor device packages (semiconductor device packages) be formed or become. For example, in the example of 1K Two semiconductor device packages 137-1 and 197-2 are shown, each of which may comprise a plurality of semiconductor chips, for example a first semiconductor chip 105 and a second semiconductor chip 114. Alternatively, reference numerals 137-1 and 137-2 may represent a single semiconductor device package form. The first semiconductor chips 105 and second semiconductor chips 114 may not be detachable from the respective package 137 .

2 12 shows another example of a side cross-sectional view of a semiconductor device 200 (or a portion thereof) in accordance with one or more described aspects. Multiple semiconductor chips, such as chips 201, 203, 205, and 207; and/or other active or passive components, as described in more detail in examples below; may be embedded in the reconstituted wafer or other layer. The exemplary semiconductor device package 200 may have a very low package height. For example, the height A of the solder balls may be in a range of 200 µm to 300 µm, for example about 250 µm (with a spacing between solder balls of about 0.5 mm). The height A of the solder balls may be in a range from 150 µm up to 150 µm, for example 200 µm (with a spacing of about 0.4 mm). The height B of the dielectric and the second semiconductor can be in a range from 5 μm to 40 μm, for example approximately 30 μm. The height C of the second semiconductor chip and the second metallization extension can be in a range of 20 μm to 250 μm, for example approximately 120 μm. The height of the second metallization can be in a range of 10 µm to 30 µm for laser drilled connections and in a range of 5 µm to 15 µm for other types of connections. For example, the second semiconductor chip can have a height of approximately 100 μm and the metallization extension can have a height of approximately 20 μm. In various configurations, the second semiconductor chip can have an even smaller height, for example approximately 50 μm. The height D of the first dielectric layer, the first redistribution layer and the adhesive can be approximately 40 μm. The height E of the formed (and ground) reconstituted wafer may be approximately 100 µm. Consequently, the total thickness F of the three-dimensional semiconductor package 200 with two layers of semiconductor chips can be about 490 μm (or about 440 μm if the second semiconductor chip has a height of about 50 μm). Similarly, a package with three layers of semiconductor chips can have an overall height of about 600 µm. The example dimensions described herein may also be applied to other embodiments, such as the example embodiments of FIGS 1k , 3 , 4e , 5d , 6c and 7 . Again, the stacked arrays of chips and/or other components may be singulated, such as diced, to form individual packages.

In addition to the potential economies of scale embodied by the examples in this disclosure, the semiconductor device 200 may be less expensive to manufacture than packages using through silicon vias (TSV), which are quite expensive to manufacture. TSVs can be avoided if desired, for example by fanning out the contact areas of the semiconductor chips and by using one or more redistribution layers. Furthermore, the electrical performance of the stack can be promoted by using layers of redistribution material and short connections between the redistribution layers. Furthermore, the stacking of Chips and / or housings may be possible. For example, a housing can have more than three layers. A housing can also be stacked on top of another housing.

3 FIG. 3 shows another example of a side cross-sectional view of a semiconductor device 300 (or a portion thereof) in accordance with one or more described aspects. The semiconductor device 300 may include three (or more) layers of semiconductor chips. The method of fabricating a three (or more) layer device may vary from that described in 1 hour shown intermediate semiconductor device are continued. A second adhesive layer 303 can be formed, for example by means of printing, laminating, dispensing, etc., at pick-and-place areas of a third layer of a plurality of semiconductor chips 305, illustrated in FIG 3 for example as chips 305-1 and 305-2. The third semiconductor chip 305 can be arranged directly on the adhesive 303 . The third semiconductor chip 305 may have a first side, for example a top, with a plurality of conductive contacts and/or conductive extensions. The third semiconductor chips 305 can also have a second side, for example a bottom side, which is or will be arranged on the adhesive 303 . A third electrically insulating layer 307 may be formed around the third semiconductor chips 305 and a plurality of vias 309 may be formed, for example by drilling, to expose the second redistribution layer and/or the conductive extensions of the third semiconductor chips. A third redistribution layer 311 may be formed over the dielectric 307 . As already described above, the third layer of redistribution 311 can fan out the conductive contacts of the first layer of semiconductor chips 105, the second layer of semiconductor chips 114, and/or the third layer of semiconductor chips 305. An electrically insulating layer 313 may be formed over and/or around the third redistribution layer 311; and drilling and/or other photolithographic processes may expose the third redistribution layer 311 . These steps can thus be repeated any number of times to form any number of stacked layers of semiconductor chips. In the final layer, a solder stop and/or solder balls 315 may be or will be applied to form the semiconductor package 300 . Similar to other embodiments, the stacked arrays of chips and/or other components may be singulated, eg, diced, to form individual packages.

4a-e 12 shows comparative examples of side cross-sectional views of a semiconductor device (or parts thereof) with a flip-chip structure and/or an example of a method for manufacturing a semiconductor device with a flip-chip structure. The method for manufacturing the semiconductor devices with one or more flip-chip packages can be derived from that in 1 shown intermediate semiconductor device are continued. Instead of applying an adhesive layer as in 1c As shown, flip chip packages may be used, such as flip chip packages 409-1 and 409-2. In 4a , the flip-chip packages 409 may have a first side 411, for example an active side, with a plurality of conductive contacts. Flip chip packages 409 may also have a second side 413 that does not have electrically conductive contacts. Flip-chip packages 409 may include a plurality of solder balls 419, such as flip-chip µ-bumps, that are electrically connected to the conductive contacts of the flip-chip package 409. The solder balls 415 may be connected to the conductive contacts by a metallization element, such as a copper UBM. With the solder balls 415 facing up, the flip chip packages 409 can be flipped over and positioned directly on the first redistribution layer 111 . When flipped over, the active side 411 of the flip chip packages 409 may face the active side of the embedded semiconductor chips 105 . The electrical and/or physical connection may be maintained by soldering the solder balls 115 to the redistribution layer 111 and/or by using thermocompression bonding and/or other semiconductor device fabrication methods.

In 4b the flip chip package 409 may be underfilled, overmolded, and/or over/undermolded, such as a molded underfill (MUF); with electrically insulating materials, whereby an electrically insulating layer 417, for example a molded layer, is or will be formed. For example, a material capable of flowing between the gaps that exist between the solder balls 415 can be used as the underfill. In 4c the electrically insulating layer 417 can be ground to reduce the housing height, for example to position 419. A plurality of vias 421, such as interconnects, may be formed, such as by laser drilling, photolithography, etc.; to expose the first redistribution layer. In 4G For example, the vias 421 may be filled with an electrically conductive material 423 and a second redistribution layer 425 may be formed or inserted around the electrical contacts of the first semiconductor die that are incorporated into the reconstituted wafer and/or the flip chip package 409 are bedded to fan out. In the 4a until 4d The illustrated steps can be repeated to form a semiconductor device package with any number of layers of semiconductor chips.

4e 4 shows an example of a cross-sectional side view of a semiconductor device package 427 having two layers of semiconductor chips, with a flip-chip layer, in accordance with one or more described aspects. The semiconductor package 427 may have another electrically insulating layer 429, a solder stop, and/or solder balls 431. Similar to other embodiments, the stacked arrays of chips and/or other components may be singulated, such as diced, to form smaller individual packages.

5a-d 10 show examples of side cross-sectional views of a semiconductor device (or parts thereof) with wires and/or an example of a method for manufacturing a semiconductor device with wires according to one or more described aspects. The method of manufacturing the semiconductor device with wires may differ from that in 1D shown intermediate semiconductor device are continued. Because wires are or will be connected directly to the bare chips, such as the second chip 114, the conductive extensions 117 may not be necessary. In 5A For example, conductive wires 501 may electrically connect the first redistribution layer 111 to the conductive contacts of the second semiconductor chips 114 . In 5b An electrically insulating layer 503, for example a molding compound, can be or will be formed around the second semiconductor chips 114 and/or the wires 501. In 5c a plurality of vias 505, for example interconnects, may be formed in the electrically insulating layer 505 in order to expose the first redistribution layer 111.

5d FIG. 5 shows an example of a semiconductor package 500 having at least two layers of stacked semiconductor chips and using a wire bonding stack for the second layer of semiconductor chips. From the in 5c In the methods illustrated, vias 505 may be filled with an electrically conductive material, a second redistribution layer 509 may be formed, an electrically insulating layer 511, such as a dielectric, may be formed, and/or solder balls 513 (and solder stop) may be formed be. Similar to other embodiments, the stacked array of chips and/or other components may be singulated, such as diced, to form smaller individual packages.

6a-c show comparative examples of side cross-sectional views of a semiconductor device (or parts thereof) with active and/or passive components and/or an example of a method for manufacturing a semiconductor device with active and/or passive components according to one or more described aspects. The semiconductor devices described herein may include any number of active and passive semiconductor chips. Active semiconductor chips may include, but are not limited to: integrated circuits, e.g., memory, baseband chips, processors, etc. Passive semiconductor chips may include, but are not limited to: surface mount devices (SMDs), integrated passive devices ( integrated passive devices IPDS), resistors, capacitors, diodes, inductors and the like.

In 6a , a base layer 601 may be provided, such as a reconstituted wafer. The base layer 601 may have a plurality of embedded active chips 605 and/or a plurality of embedded passive chips 603 . In 6b For example, an electrically insulating layer 607, such as a dielectric, may be formed on the reconstituted wafer. With the contacts of the chips 603 and/or 605 exposed, a first redistribution layer 609 may be formed on the semiconductor device. Other active chips 615 and/or passive chips 611 may be or will be placed in electrical connection with the first redistribution layer 609 . For example, the active chip 615 can be structurally connected to the insulating layer 607 by means of an adhesive 613. As described above, the active side of the active chip 615 can face up, as shown in examples in FIG 1 , such as an RDL connection, and 5 , for example a wire connection. The contacts of the chip 615 may be covered with a metal structure, such as a copper pillar as described above. Alternatively, the active side of the chip 615 can face down as shown in examples in FIG 4 , for example a flip-chip connection.

In 6c an electrically insulating layer 617, for example a photostructurable electrically insulating layer, can be or will be formed around the second layer of the active chips 615 and/or passive chips 611. The first redistribution layer 609 and/or other conductive contacts, e.g. contacts on the active chips and/or passive chips, are exposed, e.g. by means of laser drilling, photolithography, etc.; and conductive filler 619 can be used to fill the first redistribution layer with to connect upper layers electrically. A second redistribution layer 621 and an electrically insulating layer 623, for example a dielectric, can be or will be formed on the semiconductor component. Furthermore, active chips and/or passive chips 625 may be positioned in electrical communication with the second redistribution layer 621 . Solder balls 627 may be positioned or become in electrical connection with the second redistribution layer 612 to form the semiconductor package 600 with a plurality of passive and/or active components. Similar to other embodiments, the stacked arrays of chips and/or other components may be singulated, such as diced, to form smaller individual packages.

7 FIG. 7 shows another comparative example of a side cross-sectional view of a semiconductor device 700 (or a part thereof) with active and/or passive components. The semiconductor device 700 may include a base layer 701, for example a reconstituted wafer, with embedded passive and/or active chips. The semiconductor device 700 may include one or more additional layers of active and/or passive chips and/or packages, for example, an active flip-chip package 703 and a plurality of passive chips 707. These flip-chip packages 703 may be underfilled with a filler material 705 after the flip chip package has been brought into electrical connection with the redistribution layer, e.g. by means of printing, thermocompression bonding, etc. Similar to other embodiments, the stacked array of chips and/or other components may be singulated, e.g. diced, to form smaller ones form housing.

The different embodiments have been shown and described as examples only. Words used in this specification are intended for purposes of illustration rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the present disclosure.

Claims (18)

Semiconductor device, comprising: • a base layer (101, 601, 701) with a first semiconductor chip (105), the first semiconductor chip (105) having at least one electrically conductive contact (106) on a first side (107) of the first semiconductor chip (105); • a first electrically insulating layer (109) on the base layer (101, 601, 701); • a first redistribution layer (111) which contacts the at least one electrically conductive contact (106) of the first semiconductor chip (105), the first redistribution layer (111) extending over the boundaries of the first semiconductor chip (105) and over the first electrically insulating one layer (109) is arranged; • a second semiconductor chip (114) having a first side (115) and a second side (116), the second semiconductor chip (114) having at least one electrically conductive contact (106) on the first side (115) of the second semiconductor chip (114) having; • a patterned adhesive layer (113) arranged between the first side (107) of the first semiconductor chip (105) and the second side (116) of the second semiconductor chip (114), the second semiconductor chip (114) being arranged directly on the adhesive layer (113). and wherein the adhesive layer (113) is at least partially arranged directly on the first redistribution layer (111) and the first electrically insulating layer (109); • an additional electrically insulating layer (119) arranged at least partially over the first side (115) of the second semiconductor chip (114), the additional electrically insulating layer (119) having at least one via (123), so that the first redistribution layer (111) exposed and • a second redistribution layer (127) which contacts at least one electrically conductive contact (106) of the second semiconductor chip (114), the second redistribution layer (127) being electrically connected to the first redistribution layer (111) by means of the at least one via (123) . Semiconductor device according to claim 1 , further comprising: at least one solder ball (133) contacting the second redistribution layer (127). Semiconductor device according to claim 1 , further comprising: • a third semiconductor chip (305) having a first side and a second side, the third semiconductor chip (305) having at least one electrically conductive contact on the first side of the third semiconductor chip (305); • a second adhesive layer (303) arranged between the first side (115) of the second semiconductor chip (114) and the second side of the third semiconductor chip (305), the third semiconductor chip (305) being arranged directly on the second adhesive layer (303); • a second electrically insulating layer (129) arranged at least partially over the first side of the third semiconductor chip (305), the second electrically insulating layer (129) having at least one via (309), so that the second redistribution layer (127) is exposed; and • a third redistribution layer (311) which contacts the at least one electrically conductive contact of the third semiconductor chip (305), the third redistribution layer (311) being electrically connected to the second redistribution layer (127) by means of the at least one via (309) of the second electrically insulating layer (129). Semiconductor device according to one of Claims 1 until 3 wherein the base layer (101, 601, 701) is a reconstituted wafer and wherein the first semiconductor chip (105) is embedded in the reconstituted wafer. Semiconductor device according to claim 4 wherein a plurality of semiconductor chips (105-1, 105-2, 201, 203, 205, 207, 603) are embedded in the reconstituted wafer. Semiconductor device according to claim 5 , wherein the plurality of semiconductor chips (105-1, 105-2, 201, 203, 205, 207, 603) has at least one passive semiconductor chip and at least one active semiconductor chip. Semiconductor device according to one of Claims 1 until 6 , wherein the first semiconductor chip (105) and the second semiconductor chip (114) form a single integrated circuit package. Semiconductor device according to claim 7 , wherein the second semiconductor die (114) is not detachable from the single integrated circuit package without damaging the package. Semiconductor device according to one of Claims 1 until 8th , wherein the first semiconductor chip (105) and the second semiconductor chip (114) are integrated circuits. A method of manufacturing a semiconductor device, the method comprising: • Forming a first redistribution layer (111) over a first electrically insulating layer (109) on a surface of a base layer (101, 601, 701) with a first semiconductor chip (105), the first semiconductor chip (105) having at least one electrically conductive contact ( 106) on a first side (107) of the first semiconductor chip (105), wherein the first redistribution layer (111) contacts the at least one electrically conductive contact (106) of the first semiconductor chip (105); • applying a structured adhesive layer (113) at least partially directly to a surface of the first rewiring layer (111) and the first electrically insulating layer (109); • arranging a second semiconductor chip (114) directly on the adhesive layer (113); • applying a polymer layer (119) around the second semiconductor chip (114) after arranging the second semiconductor chip (114) on the adhesive layer (113); • forming at least one via (123) through the polymer layer (119), wherein the at least one via (123) exposes the first redistribution layer (111); and • forming a second redistribution layer (127) on a surface of the polymer layer (119, 503). procedure according to claim 10 , • wherein the second semiconductor chip (114) has at least one electrically conductive contact (106) on a first side (115) of the second semiconductor chip (114), and • wherein the arranging of the second semiconductor chip (114) comprises: arranging a second side ( 116) of the second semiconductor chip (114) directly on the adhesive layer (113), the second side (116) being different from the first side (115). procedure according to claim 10 or 11 , further comprising: • forming an additional electrically insulating layer (119, 503) at least partially on the first side (115) of the second semiconductor chip (114); and • forming at least one via (123) through the additional electrically insulating layer (119, 503), wherein the at least one via (123) exposes the first redistribution layer (111). Method according to one of Claims 10 until 12 , further comprising: forming a second redistribution layer (127) on the additional electrically insulating layer (119, 503), the second redistribution layer (127) electrically connecting the at least one electrically conductive contact (106) of the second semiconductor chip (114) to the first redistribution layer (111) connects by means of the at least one via (123). Method according to one of Claims 10 until 13 , further comprising: arranging at least one solder ball (133) on the second redistribution layer (127). Method according to one of Claims 10 until 13 , further comprising: • applying a second adhesive layer (303) at least partially on a surface of the second redistribution layer (127); • arranging a third semiconductor chip (305) on the second adhesive layer (303); • forming a second electrically insulating layer (307) at least partially on the third semiconductor chip (305); • forming at least one via (309) through the second electrically insulating layer (307), wherein the at least one via (309) of the second electrically insulating layer (307) exposes the second redistribution layer (127); and • forming a third redistribution layer (311) on the second electrically insulating layer (307), the third redistribution layer (311) electrically connecting at least one electrically conductive contact (106) of the third semiconductor chip (305) to the second redistribution layer (127). the at least one via (309) of the second electrically insulating layer (307). Method according to one of Claims 10 until 15 , further comprising: grinding the base layer (101, 601, 701) to remove excess material. Method according to one of Claims 10 until 16 wherein the base layer (101, 601, 701) is a reconstituted wafer and wherein the first semiconductor chip (105) is embedded in the reconstituted wafer. Method according to one of Claims 10 until 12 and 14 until 17 , further comprising: electrically connecting at least one electrically conductive contact (106) of the second semiconductor chip (114) to the first redistribution layer (111) by means of a wire (501) before the polymer layer (503) is arranged.

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