DE10145699A1 - Layer arrangement used in communication/information technology comprises a crystalline substrate, trenches inserted into the substrate with a part of the trench being filled with electrically insulating material, and crystalline sections - Google Patents

Abstract

Layer arrangement comprises a crystalline substrate (101) made from a first semiconductor material; trenches (102, 103) inserted into the substrate with a part of the trench being filled with an electrically insulating material; and crystalline sections (106, 107) made from a second semiconductor material applied on the first semiconductor material via a part of the trench. An Independent claim is also included for a process for the production of the layer arrangement. Preferred Features: The first and second semiconductor materials are made from silicon, germanium, or a silicon-germanium alloy. The arrangement further comprises an electronic component integrated on or in the substrate. The crystalline section and the substrate are electrically decoupled from each other. The arrangement further comprises a source region, a drain region, a channel region, a gate oxide region and a gate region.

Description

The invention relates to a layer arrangement and a Method for producing a layer arrangement.

The development in communication and information Technology has led to constant in recent years growing scaling requirements (miniaturization) and the speed of logic modules.

However, the conventional silicon microelectronics are used progressing downsizing to its limits bump. If the structure falls below 80 nm the components become disruptive due to quantum effects influenced and below dimensions of about 30 nm dominated. The increasing integration density of the Components on a chip lead to a dramatic increase in Waste heat.

A further training in conventional silicon microelectronics is SOI technology ("Silicon on Insulator"). For the SOI technology requires SOI substrates that consist of one Layer stack of silicon-silicon dioxide-silicon built up are, the two silicon layers, which the If possible, coat the silicon dioxide layer on both sides should be single crystal. There are technological problems on the one hand in the production of an isolated, single-crystal Layer on a silicon dioxide layer, and on the other hand in the integration of this process step into one Overall process in the manufacture of an integrated Circuit.

A central problem of conventional, integrated Circuits is the steady deterioration in electrical Properties of MOS transistors with increasing structure Delicacy, d. H. Miniaturization. The reason for this is the Threshold voltage drop, punch-through effects, the latch Up effect as well as in relation to the reciprocal Transistor size disproportionately growing parasitic Capacitance between the drain / source region and the substrate. The punch-through effect becomes an undesirable one Current penetration between neighboring transistors designated. The phenomenon known as the latch-up effect is that a p-channel MOS transistor and an n-channel MOS transistor If the minimum distance between them is less than one Form parasitic thyristor on which a high ignition current can flow, which integrated local destruction Components can cause.

The SOI technology is described in terms of Problems with the miniaturization of transistors advantageous because with SOI technology every single one Component in a spatially highly localized, complete isolated silicon island. As a result of is the missing connection between the silicon islands Latch-up effect avoided, and since the active function of the Transistors on the thin silicon film is confined parasitic short-channel effects are weakened.

Basics of SOI technology are, for example, in [1] or [2]. The known from the prior art SOI concepts can be used in crystal-based techniques which a single-crystal silicon wafer as a starting material is used in which a below the disc surface buried insulator layer is created, and into the Subdivide recrystallization processes based on oxidic insulators amorphous or polycrystalline silicon Layers are deposited and by supplying energy melted and converted into crystalline films.

This is an example of crystal-based SOI technology So-called SIMOX process ("Separation by Implantation of Oxygen "). The SIMOX process is based on an ion Implantation of oxygen in weakly doped n- or p- conductive silicon wafers, which means below the wafer Surface of a buried, electrically insulating layer is generated from silicon dioxide. However, the Energy transfer of the oxygen ions to the silicon crystal to extreme thermal loads on the silicon wafer during implantation and to a significant radiation Damage to the crystal. In addition, it is according to the SIMOX process required the silicon wafer during the Heat implantation to at least 400 ° C. Further points the single-crystal top layer has a high dislocation density on, and those remaining in the crystalline top layer Oxygen atoms cause binding disorders that lead to Reduction of charge carrier mobility in the substrate to lead. After all, you don't get a homogeneous silicon dioxide Layer, but an atomic oxygen distribution with one Concentration maximum. Therefore, it is in accordance with the SIMOX process not possible a homogeneous, electrically insulating layer with consistently constant material properties in the Form silicon wafers. In addition to those already mentioned There are also disadvantages of SIMOX technology serious disadvantage in the extremely complex Manufacturing process, which creates high costs in the Contradicting the need for inexpensive logic circuits stand. It is also not possible according to the SIMOX process locally narrowly delimited SOI layers on a wafer generate, rather you get a continuous SOI layer across the entire wafer.

An alternative concept is the so-called wafer bonding. Here, two thermally oxidized silicon wafers pressed against each other by means of mechanical pressure. As a result the two wafers are one of van-der-Waals forces weak liability by means of anodic bonding or by means of tempering in a mechanically firm connection can be transferred. Thermal annealing takes place Oxidation in a pure oxygen atmosphere at 1000 ° C. At the anodic bonding will have an electrical voltage of approximately 500 V is applied to the wafers and the wafers are placed on one Brought temperature of about 500 ° C. The attached to each other Wafers are etched on one of the two slices a thickness of a few µm in a crystalline silicon Layer on a silicon dioxide insulator on a silicon Fashioned wafers. Again, it is disadvantageous that by means of Wafer bonding no local SOI layers on a wafer can be generated. Furthermore, even minor ones have an effect Fluctuations in the thickness of the wafers are negative because of one uniform silicon film on the oxide is required. SOI layers that are produced by means of wafer bonding, only serve as the basis for further processing, whereas a parallel, integrated training Circuits on a silicon wafer and a simultaneous one Manufacture of SOI layers according to the wafer bonding Technology is excluded.

With ELO technology ("Epitaxial Lateral Overgrow") a thermally grown oxide layer on a silicon Wafer using a suitable lithography and a suitable etching process structured into islands that in a subsequent epitaxy process based on that Substrate by means of a lateral crystal growth Silicon material are coated. The grown up crystalline silicon layer is made by means of a suitable Polishing process removed and planarized to a to achieve constant film thickness on the oxide islands. However, the SOI area created is in accordance with the ELO method due to the limited overgrowth of the oxide limited.

The following describes how SOI layers are used under Can be produced using a recrystallization process are. An SOI layer is made by depositing high purity Silicon on an insulating substrate followed by one Recrystallization process, producible. As a carrier material thermally oxidized, single-crystalline silicon Slices. The upper layer is deposited on the oxide layer Silicon layer in polycrystalline or amorphous state, depending on which separation technology is selected. The Recrystallization of the deposited amorphous or polycrystalline films are made by irradiating the Disc surface with high-energy radiation, such as for example laser radiation. At the same time as the Irradiation is the silicon wafer of the back to a temperature of 500 ° C to 1250 ° C heated.

In summary, they show the state of the art known SOI technologies have a number of serious disadvantages on. So they cost by using the known methods manufactured SOI wafers more than ten times conventional bulk wafers and are therefore a very expensive Starting material for the training of integrated Circuits on an SOI wafer. This will make the Efforts counteracted, inexpensive mass storage manufacture. Furthermore, the described methods technologically difficult and complex. Another serious disadvantage is that with the described Procedure of forming integrated circuits the silicon wafer only after the manufacture of SOI layers is possible. To such integrated To manufacture circuits with reasonable effort, it would be desirable to know the methods for forming the SOI Layer and the method of forming integrated Combine circuits into an overall process, d. H. to be able to execute in parallel. This is according to the from the SOI methods known in the prior art are not possible. Also it is not possible with the SOI techniques described, form spatially limited SOI areas on a wafer, where the two silicon layers are from each other are electrically isolated.

In the event of successful overcoming or avoidance of the the problems mentioned would offer SOI technology due to its great advantages over the conventional silicon Microelectronics (for example possibility with low power and High power applications, stability at high Operating temperatures and cosmic rays, savings of process steps, avoiding the latch-up effect and Reduction of parasitic pn capacities) diverse economically interesting opportunities.

The invention is based on the problem of To create an arrangement with an SOI layer sequence that in a common procedure simultaneously with others integrated components can be trained and with moderate effort and therefore inexpensive to manufacture.

The problem is compounded by a layer arrangement and a Method for producing a layer arrangement with the Features solved according to the independent claims.

The layer arrangement has a crystalline substrate a first semiconducting material, at least one in the Trench introduced substrate, wherein at least part of the at least one trench at least partially with a first electrically insulating material is filled and at least one over at least part of the trench on the electrically insulating material applied crystalline Section made from a second semiconducting material.

The first and the one are preferably independent of one another second semiconducting material each one of the materials Silicon or germanium or a silicon germanium Alloy.

The first electrically insulating material is silicon dioxide Material, silicon nitride material, calcium fluoride material, Tantalum pentoxide material, aluminum oxide material, hafnium oxide Material, titanium oxide material, nitrided silicon dioxide Material, a silicon dioxide-silicon nitride layer sequence (NO) or a silicon dioxide-silicon nitride-silicon dioxide (ONO) -Schichtfolge.

Is the first and second semiconducting material Silicon selected and is the first electrically insulating The material selected as silicon dioxide is one according to the invention Novel SOI layer provided which the above interesting applications described.

By at least according to the invention in the crystalline substrate a trench is made, which when using a sufficiently small-sized mask a very small Dimension can be a spatially limited SOI layer provided according to the invention, which to the Sides is electrically insulated. Therefore, based on of the layer arrangement according to the invention miniaturized SOI Components can be trained, and as a result of the sufficiently safe electrical decoupling between the crystalline Sections on neighboring trenches and between one crystalline section and the underlying substrate are disadvantageous interactions between neighboring ones integrated components avoided. The technological Difficulties with the increasingly growing Integration density of integrated components Substrates, for example the one described above Latch-up effect or the punch-through described above Effect are therefore avoided according to the invention.

According to an advantageous development of the invention the layer arrangement at least one more on or in the Integrated electronic component substrate.

Advantageously, the formation of the invention Layer arrangement, i.e. H. forming the spatially strong localized SOI layers and other integrated Components carried out as part of an overall process become. Manufacturing is according to the prior art such integrated circuits only in two from each other separate procedures feasible. In a first procedure is an SOI substrate according to the prior art manufactured, and in a subsequent second process the SOI substrate is used to integrated on it Train components. In contrast, it is according to the invention possible to form an SOI structure on the one hand and that Form additional integrated components with a to implement parallel process sequences. I.e. that during the formation of the SOI layers further integrated Components can be formed on a substrate. This is in terms of reducing manufacturing effort integrated components advantageous.

In the case of the layer arrangement, the at least a crystalline section and the crystalline substrate electrically decoupled from each other. According to an advantageous Design assigns the layer arrangement among other things this purpose an area from a second electrical insulating material between the at least one crystalline section and the crystalline substrate such is arranged that the at least one crystalline Section and the crystalline substrate from each other electrically are decoupled.

In other words, the crystalline section is on the first electrically insulating material from the one below lying crystalline substrate electrically decoupled. Therefore is an undesirable interaction between the two semiconducting areas as well as an undesirable Interaction between different crystalline Sections avoided. Therefore, with transistor arrangements, which are based on the layer arrangement according to the invention, disruptive latch-up effects and punch-through effects avoided.

According to an advantageous embodiment of the invention the layer arrangement furthermore doped a source region with doping atoms of a given doping type, in a first surface area of the at least one crystalline section, a drain region, doped with Doping atoms of the specified doping type, in one second surface area of the at least one crystalline Section, a channel area in the at least one crystalline section between the source region and the Drain region, a gate oxide region from a third electrically insulating material on the channel area and a gate region made of an electrically conductive material on the gate oxide area.

In other words, according to the training described an SOI transistor is provided. Such an SOI transistor has the particularly advantageous property that its Expansion on the substrate is extremely small. This is in With regard to the desired high integration density of Transistors on a chip are very advantageous. The extension a transistor is essentially only by resolution the mask for forming the trench of the layer arrangement limited. As a result of the electrical decoupling of the crystalline sections of each other and of the crystalline Substrate on different crystalline sections decoupled from the first electrically insulating material Transistors that can be formed are undesirable Interactions between neighboring transistors Avoided transistor arrangement. This represents a significant one Advantage over transistor arrangements according to the prior art Technique represents where latch-up, punch-through and other distracting Interaction effects occur.

Independent of one another, the first and the second semiconducting material are each one of the materials silicon or germanium or an alloy of silicon and germanium. Furthermore, in the layer arrangement, the first, the second and the third electrically insulating material are silicon dioxide material (SiO ₂ ), silicon nitride material (Si ₃ N ₄ ), calcium fluoride material (CaF ₂ ), tantalum pentoxide material ( Ta ₂ O ₅ ), aluminum oxide material (Al ₂ O ₃ ), hafnium oxide material (HfO ₂ ), titanium oxide material (TiO ₂ ), nitrided silicon dioxide material, a silicon dioxide-silicon nitride layer sequence (NO) or a silicon dioxide Silicon nitride silicon dioxide (ONO) layer sequence. The electrically conductive material is crystalline silicon, polycrystalline silicon, a silicon-metal alloy (silicide) or a metal. If polycrystalline silicon is used as the electrically conductive material, this is preferably doped with doping atoms of the specified doping type.

To produce the layer arrangement according to the invention inexpensive and readily available materials can be used. In particular, a conventional silicon Wafer ("bulk" wafer) can be used by more than one factor ten is cheaper than one according to the prior art for forming an integrated SOI circuit required SOI wafer. This represents regarding the targeted applications of the layered Arrangement as a mass storage device is a great advantage Using doped polycrystalline silicon as electrically conductive material for forming the gate Electrode represents a low resistance of the gate electrode safe, resulting in low leakage currents and one at most slight heating of a transistor arrangement based the layer arrangement according to the invention is ensured.

The specified doping type is either p-doping or an n-doping.

The generation of SOI-like is therefore according to the invention Substrates on conventional bulk substrates during the Processing of the actual electronic components and realized only in local areas on the wafer. You can do this Known and mature process technologies from the Series production according to the state of the art Technology used in many ways semiconductor technology laboratories and factories stand. A complex development of new processes and / or machines is therefore used to manufacture the Layer arrangement according to the invention can be dispensed with. Another The advantage is that both bulk-like components as well as different SOI-like components together can be produced on a single wafer.

The following describes how to use conventional Process technologies on inexpensive bulk substrates by means of a clever process sequence SOI-like layer Structures or transistors in locally restricted areas a substrate can be produced.

Furthermore, the method according to the invention is used Manufacture of the layer arrangement according to the invention in more detail described. Refinements of the layer arrangement apply also for the method for producing the layer arrangement.

In the inventive method for producing a Layer arrangement will have at least one trench in one crystalline substrate made of a first semiconducting material introduced, at least part of the at least one trench at least partially with a first electrically insulating Material filled in and over at least part of the trench at least one on the electrically insulating material crystalline section from a second semiconducting Material applied.

The trenches are preferably produced and the Introducing the first electrically insulating material into the trenches using the trench isolation technique ("Shallow Trench Isolation ", STI).

Trench isolation is the side isolation adjacent integrated components from each other Trenches understood in a monocrystalline substrate introduced and filled with insulating material. With trench isolation technology, trenches are first integrated into one etched monocrystalline substrate, the silicon material in the surface areas of the trench optionally by means of thermal oxidation oxidized to silicon dioxide and the Then dig with an electrically insulating Material, usually silicon dioxide or silicon nitride refilled. When filling the trench with silicon dioxide The material is preferably the TEOS process ("tetraethyl Orthosilicate ") is used. In this way, at least a digging into a crystalline substrate from a first introduced semiconducting material and at least part of the at least one trench at least partially with a first electrically insulating material filled.

Both the trench isolation technology STI and the TEOS Procedures are standardized, semiconductor technology Procedures that are widely used and with moderate effort are feasible.

The at least one crystalline section of the second semiconducting material is preferably grown on the surface region of the electrically insulating material by means of selective epitaxy (“selective epitaxial grow”). In the case of selective epitaxy, silane (SiH ₄ ) or dichlorosilane (SiH ₂ Cl ₂ ) is preferably used as the process gas.

The term epitaxy is used in semiconductor technology understood the application of a layer that is more clearly Orderly grows up on a pad. Using the ELO technology ("Epitaxial Lateral Overgrow") is based on a crystalline layer on which a surface area a different material than the material of crystalline Layer has another crystalline from the side Layer grew up, so that the surface area from the other material from the side edges with the crystalline layer is covered. Within the scope of the invention is on the first electrically insulating material in the A single-crystal trench using selective epitaxy (SEG) Silicon layer generated.

Alternatively, the at least one crystalline section can be made of the second semiconducting material on the surface area of the electrically insulating material using liquid phase Epitaxy (LPE), organometallic epitaxy (MOCVD), Molecular beam epitaxy (MBE) or atomic layer deposition (ALD) are trained.

It is also preferred during the manufacturing process on or in at least one further surface area of the crystalline substrate at least one other electronic Integrated component.

This will integrate the SOI structures and others Components in the layer arrangement according to the invention preferably as part of a single overall process manufactured.

According to a further embodiment of the invention Process for making a layer arrangement is furthermore an area of a second electrically insulating Material between the at least one crystalline section and the crystalline substrate such that the at least one crystalline section and the crystalline Substrate are electrically decoupled from each other.

For example, after an epitaxial growth of crystalline silicon sections on with the first trenches filled with electrically insulating material a combination of a wet etching process and Oxidizing (for example thermal oxidizing) the epitaxially grown crystalline silicon sections be electrically decoupled from the substrate. Thereby Local SOI layers are created that also belong to the Sides are completely electrically insulated.

Furthermore, in the method according to the invention for Manufacture the layer arrangement from a gate oxide region a third electrically insulating material on one Surface section of at least one crystalline Section and a gate area from an electrical conductive material are applied to the gate oxide, and a source region in a first surface region of the at least one crystalline section and a drain region in a second surface area of the at least one crystalline section by doping the first and the second surface area of the at least one crystalline section with doping atoms of a predetermined doping type are formed such that the gate oxide area on the surface section of the crystalline section at least partially between the Source region and the drain region is arranged.

According to the training of the last described Method according to the invention for producing a layer Arrangement is a manufacturing process for an SOI-like Transistor provided according to the invention.

Embodiments of the invention are in the figures are shown and explained in more detail below.

Show it:

Fig. 1 is a cross-sectional view of a layer arrangement according to a first embodiment of the invention,

Figs. 2A to 2C are cross-sectional views of layer sequences at different times during the manufacturing process according to a first embodiment of the inventive method for fabricating a layer arrangement,

Fig. 3A is a first cross-sectional view of a layered assembly along a cutting plane 322 of FIG. 3D according to a second embodiment of the invention,

Fig. 3B is a second cross-sectional view of the shift assembly along a cutting plane 323 of FIG. 3D according to the second embodiment of the invention,

Fig. 3C is a schematic view of a wafer in which the layer arrangement shown in Fig. 3A, Fig. 3B is included,

Fig. 3D a cuboid segment of the wafer shown in Fig. 3C,

FIGS. 4A-4X cross-sectional views of layer sequences at different times during the manufacturing process according to a second embodiment of the inventive method for producing a layer arrangement.

In Fig. 1 a first embodiment of the layer assembly according to the invention is shown.

The layer arrangement 100 has a crystalline substrate 101 made of silicon material, a first and a second trench 102 , 103 introduced into the silicon substrate 101 , both the first and the second trench 102 , 103 being completely filled with silicon dioxide material and a first and a second crystalline section 106 , 107 made of silicon material, which is respectively applied to a part of one of the trenches 102 , 103 on the first electrically insulating material.

The crystalline substrate 100 is a monocrystalline silicon substrate.

As shown in FIG. 1, the first crystalline section 106 is electrically decoupled from the crystalline substrate 101 , the second crystalline section 107 is decoupled from the crystalline substrate 101 , and the first crystalline section 106 is electrically decoupled from the second crystalline section 107 .

The fillings made of the first electrically insulating material in the trenches 102 , 103 form a first and a second region made of the first electrically insulating material 104 , 105 .

Furthermore 2A a first embodiment of the method, referring to Fig., Fig. 2B and Fig. 2C described for fabricating the embodiment shown in FIG. 1, layer assembly 100.

According to the described exemplary embodiment of the method for producing a layer arrangement, the layer sequence 200 shown in FIG. 2A is obtained in a first step by introducing two trenches 202 , 203 into a crystalline silicon substrate 201 .

According to the exemplary embodiment described, the trenches 202 , 203 are introduced into the crystalline substrate 201 using a suitable lithography and a suitable etching method.

The layer sequence 204 shown in FIG. 2B is obtained by completely filling the two trenches 202 , 203 with silicon dioxide material, as a result of which a first region made of silicon dioxide material 205 and a second region made of silicon dioxide material 206 is obtained.

According to the described exemplary embodiment of the method according to the invention for producing a layer arrangement, the trenches 202 , 203 are filled with silicon dioxide material by carrying out the TEOS method (“tetraethyl orthosilicate”). An organic liquid (SiO ₄ C ₈ H ₂₀ ) serves as the silicon dioxide source. The TEOS process has the advantage that, in contrast to gaseous silicon compounds as the silicon dioxide source, the liquid SiO ₄ C ₈ H _{20 is} less dangerous.

After a third method step, the layer arrangement 207 shown in FIG. 2C is obtained, which is essentially identical to the layer arrangement 100 shown in FIG. 1, by extending over both trenches 202 , 203 on the first and on the second region Silicon dioxide material 205 , 206 each have a crystalline section 208 , 209 made of silicon material. For this purpose, a crystalline layer is preferably grown on the entire surface of the layer sequence 204 and this is subsequently structured using a lithography and an etching method, so that the layer arrangement 207 is obtained.

The crystalline sections 208 , 209 made of silicon material are grown on the first and the second area made of silicon dioxide material 205 , 206 by means of selective epitaxy (“selective epitaxial grow”).

In addition, Figure 3A shows a second preferred embodiment of the layer assembly according to the invention, referring to FIG. FIG. 3B.

In order to define the sectional planes along which the first cross-sectional view of a layer arrangement 300 shown in FIG. 3A and the second shown in FIG. 3B is taken, a wafer 320 is shown in FIG. 3C, in which a cuboid 321 is optically highlighted , The box 321 indicates a region of the wafer 320, the layer arrangement according to the invention is arranged in the one part, which corresponds in Fig. 3A, Fig. 3B shown layer assembly 300. The cuboid 321 clearly represents an area in the surrounding region of a trench introduced into the wafer 320. The cuboid 321 , the orientation of which is determined by the arrangement of three of its corners A, B, C, is shown enlarged in FIG. 3D. Furthermore, a first sectional plane 322 is shown in FIG. 3D, along which the first cross-sectional view of the layer arrangement 300 shown in FIG. 3A is recorded. In addition, a second sectional plane 323 is shown in FIG. 3D, along which the second cross-sectional view of the layer arrangement 300 shown in FIG. 3B is recorded. In other words, the sectional view of the cuboid 321 with a cutting plane 322 perpendicular to one of the main surfaces of the wafer 320 is shown in FIG. 3A, and the sectional view of the cuboid 321 with a cutting plane 323 parallel to one of the main surfaces of the wafer 320 is shown in FIG. 3B ,

The layer arrangement 300 shown in FIG. 3A has a crystalline silicon substrate 301 , a trench 302 made in the silicon substrate 301 , which is completely filled with a first silicon dioxide region 303 made of silicon dioxide material and one over the trench 302 on the first silicon dioxide region 303 applied crystalline silicon section 304 .

The crystalline silicon section 304 and the crystalline substrate 301 are electrically decoupled from one another by means of a second silicon dioxide region 305 , which is arranged between the crystalline silicon section 304 and the crystalline silicon substrate 301 .

Furthermore, the layer arrangement 300 has an n-doped source region 306 in a first surface region of the crystalline silicon section 304 , an n-doped drain region 307 in a second surface section of the crystalline silicon section 304 Channel region 308 in the crystalline silicon section 304 between the source region 306 and the drain region 307 , a gate oxide region 309 made of silicon dioxide material on the channel region 308 and a gate region 310 made of n-doped polycrystalline Silicon on.

Furthermore, the layer arrangement 300 has first silicon nitride spacers 311 , second silicon nitride spacers 312 , a passivation layer 313 produced from BPSG (boron phosphor silicate glass), a silicide cover layer 314 , metal contacts 315 , a metal connection 316 and a metallic gate contact 317 .

In addition to a part of the elements of the layer arrangement 300 described with reference to FIG. 3A, a metallic gate connection 318 is shown in FIG. 3B, which can be coupled to an external voltage source.

In Fig. 3A, Fig. 3B-layer arrangement 300 shown is a SOI transistor. Of course, an arrangement of a plurality of such is SOI transistors also subjects of this invention.

As shown in FIG. 3A, the crystalline silicon substrate 301 is electrically decoupled from the crystalline silicon section 304 by means of the second silicon dioxide region 305 and by means of the second silicon nitride spacer 312 . As a result, the crystalline silicon section 304 is also of a layer structure possibly arranged in a different surface area of the crystalline silicon substrate 301 (or of the wafer 320 shown in FIG. 3C), for example of a layer arrangement similar to that in FIG. 3A, Fig. 3B shown layer assembly 300, electrically decoupled. Therefore, disadvantageous effects such as, for example, the latch-up effect or the punch-through effect, as can occur with adjacent transistors in a substrate, are avoided by means of the arrangement of the components of the layer structure 300 .

As shown in FIG. 3A, the n-doped source region 306 has two subsections 306 a, 306 b, and the n-doped drain region 307 has two subsections 307 a, 307 b. The first subsection of the source region 306 a and the first subsection of the drain region 307 a are each doped with a first charge carrier density. In contrast, the second subsection of the source region 306 b and the second subsection of the drain region 307 b are doped with a second charge carrier density. The second charge carrier density is lower than the first charge carrier density, so that the first subsections of the source region 306 a and the drain region 307 a are referred to as n ⁺ -doped, whereas the second subsections of the source Region 306 b and the drain region 307 b are referred to as n-doped regions.

The functionality shown in FIG. 3A, FIG. 3B shown layer assemblies 300 as the SOI transistor.

The crystalline silicon substrate 301 serves as the substrate of the transistor. The electrical conductivity of the channel 308 between the source region 306 and the drain region 307 depends on whether an external electrical voltage is applied to the gate connection 318 and therefore to the gate contact 317 and to the gate region 310 , If an external electrical voltage is applied to the gate region 310 , the channel 310 has a higher electrical conductivity than in a scenario in which an electrical voltage is not applied to the gate region 310 . The current flow between the source region 306 and the drain region 307 as a result of a further external electrical voltage applied between the gate region 306 and the drain region 307 is therefore considerably greater if the channel region 308 is sufficiently electrically conductive, that is, when an electrical voltage is applied to the gate region 310 compared to a scenario in which the gate region 310 is free of an external electrical voltage. Therefore, the transistor shown 3B for example be used as a switching element in Fig. 3A, Fig. Can. Upon making of modifications shown in Fig. 3A, Fig. 3B shown shift assembly 300 the use of the invention in the layer arrangement is possible as contained 300 transistor memory element.

Furthermore, Figure 4A shows a second preferred embodiment of the inventive method for manufacturing the in Fig. 3A, Fig. 3B shown layer assembly 300, referring to FIG. To FIG. 4X described. Those elements of Fig. 4A to Fig. 4X, the above with reference to FIG. 3A, FIG. 3B are provided with reference numerals, 4A are provided to FIG. 4X with the same reference numerals in Fig..

The layer sequence 400 shown in FIG. 4A is obtained by first applying a first electrically insulating auxiliary layer 401 made of silicon dioxide material and then a second electrically insulating auxiliary layer 402 made of silicon nitride material to the crystalline silicon substrate 301 .

The layer sequence 403 shown in FIG. 4B is obtained by using a suitable lithography method to photostructure a photoresist layer (not shown in FIG. 4B) applied to the layer sequence 400 and then using reactive ion etching ( RIE, "Reactive Ion Etch") a trench 302 is etched into the layer sequence 400 .

The layer sequence 404 shown in FIG. 4C is obtained by producing the first section 303 a of the first silicon dioxide region 303 on the side walls of the trench 302 by means of thermal oxidation. This rounds out the edges of the trench and reduces mechanical stress and electrical leakage currents.

The layer sequence 405 shown in FIG. 4D is obtained by filling the trench 302 of the layer sequence 404 from FIG. 4C with silicon dioxide material 406 using the TEOS method. Excess silicon dioxide material, which in the vertical direction according to FIG. 4D protrudes beyond the second electrically insulating auxiliary layer 402 made of silicon nitride material, is removed using the CMP process ("Chemical Mechanical Polishing"). During the polishing process, the second electrically insulating auxiliary layer 402 serves as a stop layer.

The layer sequence 407 shown in FIG. 4E is obtained by etching the layer sequence 405 from FIG. 4D, more precisely the second electrically insulating auxiliary layer 402 made of silicon nitride material is removed by means of selective wet-chemical etching by means of hot phosphoric acid.

In order later (see FIG. 4G) to realize an approximately planar transition from the crystalline silicon substrate 301 to the first silicon dioxide region 303 , the layer sequence 408 shown in FIG. 4F is produced by a third electrically insulating auxiliary layer 409 made of silicon dioxide Material is deposited on the side surfaces of the silicon dioxide material 406 . With a simplified process management, this optional process step can be omitted.

In order to get from the layer sequence 408 from FIG. 4F to the layer sequence 410 from FIG. 4G, the layer sequence 408 is etched wet-chemically, so that the first electrically insulating auxiliary layer 401 made of silicon dioxide material is completely etched away, so that the third is electrically insulating auxiliary layer 409 is also completely etched away and so that the silicon dioxide material 406 is etched back in such a way that a second section 303 b of the silicon dioxide region 303 remains as a result. The first and the second section 303 a, 303 b of the silicon dioxide region form the silicon dioxide region 303 .

After this method step, the trench 302 is filled with the first silicon dioxide region 303 .

The layer sequence 411 shown in FIG. 4H is obtained by applying a crystalline silicon region 412 to the first silicon dioxide region 303 above the trench 302 . According to the exemplary embodiment described, the crystalline silicon region 412 is grown on the first silicon dioxide region 303 by means of selective epitaxy (“Selective Epitaxial Grow”, SEG). In other words, a crystalline silicon region 412 is grown over the entire surface of the layer sequence 410 by means of selective epitaxy. The duration of the epitaxy process depends on the size of the area to be covered. Since facets 413 can be formed in such an epitaxial production of silicon, these facets 413 can be used, for example, to be used to optimize the later channel area if the process is appropriately mastered. A dilution of the crystalline silicon region 412 in the later channel region may well be desirable. For example, an “in situ” doping of the later channel region can take place during the epitaxy. In the following, however, a production method of the layer arrangement according to the invention is described in which the facets 413 are removed in a scenario in which these facets 413 are rather disruptive.

In order to move from the layer sequence 411 shown in FIG. 4H to the layer sequence 414 shown in FIG. 4I, the facets 413 from FIG. 4H are removed by thinning the crystalline silicon region 412 until the facets 413 disappear. Depending on the doping and dimensions used, completely depleted (FD, "fully depleted") or optionally partially depleted (PD, "partially depleted") SOI-MOSFETs can be produced later. Fig. 4I shows the layer sequence 414, as obtained following dilution of the crystalline silicon section 412. This creates a crystalline silicon layer 415 that is essentially planar.

In order to move from the layer sequence 414 shown in FIG. 4I to the layer sequence 416 shown in FIG. 4J, a gate oxide layer 417 made of silicon dioxide material is deposited on the surface of the layer sequence 414 .

The layer sequence 418 shown in FIG. 4K is obtained by depositing a polysilicon layer 419 made of polycrystalline silicon on the gate oxide layer 417 . Optionally, the polysilicon layer 419 can be n-doped in order to reduce the ohmic resistance of the polysilicon layer 419 .

In order to get from the layer sequence 418 from FIG. 4K to the layer sequence 420 from FIG. 4L, the crystalline silicon layer 415 and the gate oxide layer 417 are structured using a suitable lithography and a suitable etching method, so that the Gate oxide region 309 and gate region 310 are formed.

In other words, a gate oxide area in the methods sections whose 4L intermediates in Fig. 4J, Fig. 4K, Fig. Are shown 309 of silicon dioxide material on a surface portion of the crystalline silicon layer 415 and a gate region 310 of preferably n-doped polycrystalline silicon applied to the gate oxide region 309 .

In order to move from the layer sequence 420 shown in FIG. 4L to the layer sequence 421 shown in FIG. 4M, a fourth electrically insulating auxiliary layer 422 made of silicon nitride material is deposited on the entire surface of the layer sequence 420 .

The layer sequence 423 shown in FIG. 4N is obtained by using a suitable lithography and a suitable etching method, a left and right region of the crystalline silicon substrate 301 , the crystalline silicon layer 415 and the fourth according to FIG. 4N electrically insulating auxiliary layer 422 is removed from silicon nitride material. The portion of the crystalline silicon layer 415, which remains after execution of the lithography and etching described of the method described is referred to in accordance with Fig. 3A, Fig. 3B to as crystalline silicon portion 304. The paint mask required in this process step is not shown in FIG. 4N. After the photostructuring of the resist mask, the layer sequence 423 is generated by means of reactive ion etching ("Reactive Ion Etch", RIE).

To get from the layer sequence 423 shown in FIG. 4N to the layer sequence 424 shown in FIG. 40, the exposed side surfaces of the crystalline silicon substrate 301 , the crystalline silicon section 304 and the fourth electrically insulating auxiliary layer 422 are applied by applying a fifth electrically insulating auxiliary layer 425 made of silicon nitride material electrically decoupled to the sides. This reduces the thermal load in the vicinity of the epitaxial silicon film, which prevents diffusion of doping atoms from the gate region 310 made of n-doped polycrystalline silicon material and from other layers.

In order to move from the layer sequence 424 shown in FIG. 40 to the layer sequence 426 shown in FIG. 4P, exposed silicon surfaces of the crystalline silicon substrate 301 are etched by means of wet etching. In particular, the crystalline silicon substrate 301, as shown in Fig. 4D is shown undercut in a boundary region between the crystalline silicon substrate 301 and the fifth electrically insulating auxiliary layer 425.. As an alternative to the wet etching described, the method step described can also be implemented using a dry etching method.

In order to move from the layer sequence 426 shown in FIG. 4P to the layer sequence 427 shown in FIG. 4Q, the crystalline silicon substrate 301 etched in the preceding method step is oxidized in a surface area such that the crystalline silicon section 304 of is electrically decoupled from the crystalline silicon substrate 301 . To simplify the oxidation, an implantation with oxygen or hydrogen can optionally be carried out beforehand. In accordance with the nomenclature chosen in FIG. 3A, the oxidized silicon regions, that is to say the silicon dioxide regions arising as a result of the described method step, are referred to as second silicon dioxide region 305 .

In other words, in this method step, the second silicon dioxide region 305 is formed between the crystalline silicon section 304 and the crystalline silicon substrate 301 in such a way that the crystalline silicon section 304 and the crystalline silicon substrate 301 are electrically decoupled from one another.

In order to arrive at the layer sequence 428 shown in FIG. 4R, the fourth electrically insulating auxiliary layer made of silicon nitride material 422 and the fifth electrically insulating auxiliary layer 425 made of silicon nitride material are removed by wet chemical means using a suitable etching method.

From this step onwards, all others are Process steps compatible with CMOS technology. in the The further processing for generating an n- Channel MOSFETs described, optionally can be used using corresponding p-doping atoms alternatively also a p-channel MOSFET are manufactured.

In order to get from the layer sequence 428 shown in FIG. 4R to the layer sequence 429 shown in FIG. 4S, an LLD region ("Lightly Doped Drain") of the transistor is generated using an ion implantation method. Referring to the nomenclature of Fig. 3A, Fig. 3B is a second sub portion 306 b of the source region and a second sub portion 307 b of the drain region formed by the exposed surface doping of the crystalline silicon portion 304 with n-type impurity atoms becomes. As shown in FIG. 4S, the n-doped second subsections of the source region and the drain region 306 b, 307 b extend laterally partially below the gate oxide region 309 .

The layer sequence 430 shown in FIG. 4T is obtained by applying a sixth electrically insulating auxiliary layer 431 made of silicon nitride material to the side walls of the layer sequence 429 exposed according to FIG. 4S. This sixth electrically insulating auxiliary layer 431 serves to spatially define the n ⁺ doping (HDD, "Highly Doped Drain") of the crystalline silicon section 304 to be carried out in a subsequent method step.

In order to obtain the layer sequence 432 shown in FIG. 4U, exposed surface sections of the crystalline silicon section 304 are heavily n-doped (n ⁺ -doped) with high ion doses using an ion implantation method, whereby a first Subsection of the source region 306 a and a first subsection of the drain region 307 a are formed ("Highly Doped Drain"). As shown in FIG. 4U, the first subsection of the source region 306 a is in electrically conductive contact with the second subsection of the source region 306 b, analogously the first subsection of the drain region 307 a is in contact with the second subsection of the drain Area 307 b in electrically conductive contact. It should be pointed out that the doping of the first subsections of the source region 306 a or the drain region 307 a is lower than the doping (ie the charge carrier concentration of the doping atoms) of the second subsection of the source region 306 b or drain region 307 b. In other words, the concentration of charge carriers in the first subsection of the source region 306 a or the drain region 307 a is higher than that in the second subsection of the source region 306 b or the drain region 307 b. The first subsection of the source region 306 a and the second subsection of the source region 306 b form the ndoped source region 306 , and the first subsection of the drain region 307 a and the second drain region 307 b form the n-doped Drain area 307 .

In the in Fig. 4S, Fig. 4D and Fig. 4U shown stages of the procedure therefore a drain region 306 in a first surface region of the crystalline silicon portion 304 and a drain region 307 in a second surface portion of the second crystalline Silicon section 304 is formed by n-doping the first and second surface regions of the crystalline silicon section 304 with doping atoms of the n-doping type such that the gate oxide region 309 on the surface section of the crystalline silicon section 304 is at least partially is arranged between the source region 306 and the drain region 307 .

In order to get from the layer sequence 432 shown in FIG. 4U to the layer sequence 433 shown in FIG. 4V, the exposed surfaces of the crystalline silicon section 304 and the gate region 310 made of n-doped polysilicon are covered with silicon material. As a result, a silicide cover layer 314 is deposited on the exposed surface section of the first subsection 306 a of the source region 306 and on the exposed surface section of the first subsection 307 a of the drain region 307, and on the exposed surface section of the gate Region 310 , a gate contact 317 made of silicon material is deposited.

The layer sequence 434 shown in FIG. 4W is obtained by depositing a BPSG layer 435 on the entire surface of the layer sequence 433 . The BPSG layer 435 (borophosphosilicate glass) is produced using a modified TEOS process, in which, in addition to the process liquid SiO ₄ C ₈ H ₂₀ common in the TEOS process, the doping gases diborane and phosphine are added so that Store a few percent of phosphorus and boron in the silicon dioxide material.

The layer sequence 436 shown in FIG. 4X is obtained by etching the BPSG layer 435 using a suitable lithography and a suitable etching method in such a way that contact holes are created such that the silicide cover layer 314 in an environment of the source Region 306 and an environment of the drain region 307 is exposed. This intermediate step is not shown separately in the figures. In a further process step, the contact holes produced in this way are filled with a conductive, metallic material. The metal contacts 315 are thereby formed.

The layer sequence 436 shown in FIG. 4X, according to the invention produced substantially corresponds to the layer arrangement according to the invention 300 of Fig. 3A, Fig. 3B.

The following publications are cited in this document:
[1] Widmann, D, Mader, H, Friedrich, H ( 1996 ) "Technology of Highly Integrated Circuits", Chapter 8.4, Springer Verlag, Berlin, IBSN 3-540-59357-8
[2] Hilleringmann, U (1999) "Silicon Semiconductor Technology", chapter 11.3, Teubner Study Books Electrical Engineering, Stuttgart, Leipzig, ISBN 3-519-10149-1 Reference Signs List 100 layer assembly
101 crystalline substrate
102 first trench
103 second ditch
104 first area made of the first electrically insulating material
105 second area made of the first electrically insulating material
106 first crystalline section
107 second crystalline section
200 layer sequence
201 crystalline substrate
202 first trench
203 second trench
204 layer sequence
205 first area made of silicon dioxide material
206 second area made of silicon dioxide material
207 layer arrangement
208 first crystalline section
209 second crystalline section
300 layer arrangement
301 crystalline silicon substrate
302 trench
303 first silicon dioxide area
303 a first section of the first silicon dioxide region
303 b second section of the silicon dioxide range
304 crystalline silicon section
305 second silicon dioxide area
306 n-doped source region
306 a first subsection of the source area
306 b second subsection of the source area
307 n-doped drain region
307 a first subsection of the drain region
307 b second subsection of the drain region
308 channel area
309 gate oxide area
310 gate area
311 first silicon nitride spacer
312 second silicon nitride spacer
313 passivation layer
314 silicide top layer
315 metal contact
316 metal connector
317 gate contacting
318 gate connector
320 wafers
321 cuboids
322 first section plane
323 second section plane
400 sequence of layers
401 first electrically insulating auxiliary layer
402 second electrically insulating auxiliary layer
403 layer sequence
404 layer sequence
405 layer sequence
406 silicon dioxide material
407 layer sequence
408 layer sequence
409 third electrically insulating auxiliary layer
410 sequence of layers
411 layer sequence
412 crystalline silicon area
413 facet
414 layer sequence
415 crystalline silicon layer
416 layer sequence
417 gate oxide layer
418 layer sequence
419 poly silicon layer
420 sequence of layers
421 layer sequence
422 fourth electrically insulating auxiliary layer
423 layer sequence
424 layer sequence
425 fifth electrically insulating auxiliary layer
426 layer sequence
427 layer sequence
428 layer sequence
429 layer sequence
430 layer sequence
431 sixth electrically insulating auxiliary layer
432 layer sequence
433 layer sequence
434 layer sequence
435 BPSG layer
436 layer sequence

Claims (18)

1st layer arrangement with
a crystalline substrate made of a first semiconducting material;
at least one trench made in the substrate, at least part of the at least one trench being at least partially filled with a first electrically insulating material;
at least one crystalline section made of a second semiconducting material and applied to the first electrically insulating material over at least part of the trench. 2. Layer arrangement according to claim 1, wherein each of the first and the second semiconducting material independently of one another of the materials
Silicon;
germanium; or
a silicon germanium alloy
is. 3. layer arrangement according to claim 1 or 2, the further at least one other on or in the substrate Has integrated electronic component. 4. Layer arrangement according to one of claims 1 to 3, in which the at least one crystalline section and the crystalline substrate are electrically decoupled from each other. 5. layer arrangement according to claim 4, the one area from a second electrically insulating Has material that between the at least one crystalline section and the crystalline substrate such is arranged that the at least one crystalline Section and the crystalline substrate from each other electrically are decoupled. 6. Layer arrangement according to one of claims 1 to 5, further comprising:
a source region, doped with doping atoms of a predetermined doping type, in a first surface region of the at least one crystalline section;
a drain region, doped with doping atoms of the predetermined doping type, in a second surface region of the at least one crystalline section;
a channel region in the at least one crystalline section between the source region and the drain region;
a gate oxide region made of a third electrically insulating material on the channel region;
a gate region made of an electrically conductive material on the gate oxide region. 7. Layer arrangement according to claim 6, in which the first, the second and the third electrically insulating material are independent of one another
Silicon dioxide material;
Silicon nitride material;
Kalziumflurid material;
Tantalum pentoxide material;
Alumina material;
Hafnium oxide material;
Titanium oxide material;
nitrided silicon dioxide material;
a silicon dioxide-silicon nitride layer sequence or
a silicon dioxide-silicon nitride-silicon dioxide (ONO) layer sequence
is. 8. Layer arrangement according to claim 6 or 7, wherein the electrically conductive material
crystalline silicon;
polycrystalline silicon;
a silicon metal alloy or
a metal
is. 9. layer arrangement according to claim 8, in which the polycrystalline silicon with doping atoms of predetermined doping type is doped. 10. layer arrangement according to one of claims 6 to 9, where the specified doping type is p-doping or is an n-doping. 11. A method for producing a layer arrangement, in which
at least one trench is introduced into a crystalline substrate made of a first semiconducting material;
at least part of the at least one trench is at least partially filled with a first electrically insulating material;
at least one crystalline section made of a second semiconducting material is applied over at least part of the trench on the electrically insulating material. 12. The method according to claim 11, in which during the manufacturing process of the layer Arrangement on or in at least one other Surface area of the crystalline substrate at least one further electronic component is integrated. 13. The method according to claim 11 or 12, in which the first electrically insulating material in the Digging using the trench isolation technique ("Shallow Trench Isolation ") is introduced. 14. The method according to any one of claims 11 to 13, in which the at least one crystalline section from the second semiconducting material on the surface area of the electrically insulating material by means of selective epitaxy ("Selective Epitaxial Grow"). 15. The method according to claim 14,
in the case of selective epitaxy as a process gas
silane; or
dichlorosilane
is used. 16. The method according to any one of claims 11 to 13, wherein the at least one crystalline section of the second semiconducting material on the surface region of the electrically insulating material by means of
Liquid phase epitaxy;
Organometallic epitaxy;
Molecular beam epitaxy; or
Atomic layer deposition
is trained. 17. The method according to any one of claims 11 to 16, in which an area from a second electrical insulating material between the at least one crystalline section and the crystalline substrate such is formed that the at least one crystalline Section and the crystalline substrate from each other electrically be decoupled. 18. The method according to any one of claims 11 to 17, further comprising
a gate oxide region made of a third electrically insulating material is applied to a surface section of the at least one crystalline section and a gate region made of an electrically conductive material is applied to the gate oxide region;
a source region in a first surface region of the at least one crystalline section and a drain region in a second surface region of the at least one crystalline section are formed in this way by doping the first and the second surface region of the at least one crystalline section with doping atoms of a predetermined doping type that the gate oxide region on the surface portion of the crystalline portion is at least partially disposed between the source region and the drain region.