DE10110777A1 - Arrangement and method for testing integrated circuits - Google Patents

Abstract

The invention relates to an arrangement for testing an integrated circuit (1; 21). To avoid a test vector memory and an on-board test system, a data word generator (2; 22) that supplies deterministic data words is a means (3, 4, 5, 6; 22, 23, 24, 25, 26, 27) for test pattern generation, which change the deterministic data words so that predetermined test patterns, the inputs of an integrated circuit to be tested (1; 21) can be supplied, and comparison means (12; 30) for comparing test output patterns of the integrated Circuit (1; 21) with target output patterns.

Description

The invention relates to an arrangement and a method for testing integrated Circuits.

Integrated circuits are tested after they are manufactured; for this they will be General so-called test vectors supplied, which are data words delt, which are fed to the inputs of the integrated circuit and to the Outputs produce a certain behavior of the integrated circuit that with a target behavior is compared. This makes it possible to determine whether the integrated circuit works flawlessly, that means it was manufactured correctly.

Due to the increasing integration density of such integrated circuits, the The number of required test vectors is increasing. According to the state of the art these test vectors are stored in vector memories. It may be several million test vectors per pin of the integrated circuit to be tested. By this high number makes the effort for such test systems very high, which in turn leads to Increases the manufacturing cost of the integrated circuit to be tested leads.

Another solution known from the prior art is a so-called built-in Self-Test (BIST), in which a special test circuit is installed on the integrated circuit is provided, which works together with an external, simple test system. This again has the disadvantage that additional areas on the integrated circuit needs for the test circuit arises, and that also on the integrated circuit existing circuit must be modified. This in turn runs the risk that this useful circuit cannot be optimally constructed.

It is an object of the invention to provide an arrangement and a method for testing inte to specify integrated circuits that do not require any special precautions require testing integrated circuit and which are relatively simple in their construction are.  

This object is achieved by the features of claim 1:
Arrangement for testing an integrated circuit with a data word generator, which delivers deterministic data words, with means for test pattern generation, which change the deterministic data words in such a way that predetermined test patterns, the inputs of an integrated circuit to be tested, can be supplied, and with comparison means for comparing test output patterns of the integrated circuit with target output patterns, the arrangement being provided outside the integrated circuit to be tested.

In the arrangement according to the invention for testing an integrated circuit, extensive vector memory can be dispensed with. Instead, it's a data Word generator provided that provides deterministic data words. So this means that the data word generator delivers a sequence of data words that are known, that is, predict are cash.

These deterministic data words of the data word generator are generated bit by bit Modified test pattern generation means. The individual bits are one each of these deterministic data words changed so that predetermined, deterministic Test patterns are created. These test patterns are intended to match the inputs of the to be tested, integrated circuit to be supplied or the target output pattern represent.

The modification also generates target output patterns. The exit signals of the integrated circuit to be tested, which result from the test pattern, are compared with these target output patterns by means of comparison means.

In this relatively simple way, a test pattern generation that does not Test pattern memory required, in which all test patterns or test vectors are stored. Rather, a sequence of successive test patterns can be generated by the data word genera tor and the means for generating the test pattern are generated sequentially without this must be present in a memory.  

The arrangement is provided outside of an integrated circuit and requires the integrated circuit to be tested, no special precautions, i. H. so in particular no modification of the circuit to be tested and also no additional space requirement on the integrated circuit.

The arrangement according to the invention is generally carried out using a simple test system work together, essentially the control of the arrangement and possibly the off evaluates the comparison results.

According to one embodiment of the invention is according to claim 2 as a data word generator a feedback shift register is provided. Such a feedback sliding register supplies pseudo-random data words, which are generated according to a fixed pattern become known and are therefore deterministic. In terms of circuitry very much the deterministic data words for the means for Test pattern generation can be generated.

The means for generating the test pattern are structured according to a further embodiment of the invention according to claim 3 advantageously in a bit flipping control and in bit Flipping logic that is controlled by the bit flipping control. The bit Flipping logic is provided to individually separate the bits of each of the data word Generator delivered deterministic data word to modify so that for the desired value is reached on the output side, so that the bit flipping Logics in total on the output side a desired predetermined deterministic test provide sample data word that the inputs of the integrated circuit to be tested is fed.

In the integrated circuit, circuit elements can be provided, if necessary have undefined or memory behavior. In this case, an evaluation of the Integrated circuit output pattern not possible during testing. It is about generally doing certain initial test patterns in certain phases of the Testing that cannot or should not be evaluated. To solve this problem is  according to a further embodiment of the invention according to claim 4, a masking Logic provided that controls the comparison means in the arrangement so that only pre given test output pattern of the integrated circuit to be tested with the target Patterns are compared. In other words, this logic masks certain offs gait pattern, d. H. Initial patterns that are not selected for the reasons explained above should be suppressed with regard to the evaluation.

A further embodiment of the invention according to claim 5 includes a test pattern Counter that counts a clock signal that controls the test process and the corresponding count pass on the result to elements of the arrangement, in particular to the bit flipping control tion and / or the masking logic. Because of the structure of the invention If a clock signal is sufficient to generate the test pattern, it is in this way relatively easy to determine which one based on the counting result of the counter Test phase there is a test process.

The comparison means may not have to specify each individual data word individually with a target Compare patterns; it can, as in a further embodiment of the invention is provided according to claim 6, also done by means of a signature register. The Signature register links each new output data word of the integrated to be tested Circuit with a previous storage result by exclusive OR operation. This process is repeated with each new test pattern. At the end of the test process the value of the signature register is read out and compared with a target value.

The arrangement according to the invention can be advantageous, as in a further embodiment device of the invention is provided according to claim 7, implemented as programmable logic his. Furthermore, it can advantageously, as provided in claim 7, outside the Integrated circuit provided as a link to a simple test system his. The test system controls the arrangement according to the invention and delivers, for example have the necessary clock signals.

The above task is for a method of testing integrated circuit circles solved by the features of claim 10.

An exemplary embodiment of the invention is described in more detail below with reference to the drawing explained. Show it:

Fig. 1 is a block diagram of the arrangement according to the invention and

Fig. 2 shows a more detailed block diagram of the arrangement according to the invention on a test board which is connected between an IC to be tested and a test system.

Fig. 1 shows a block diagram of the inventive arrangement for testing an integrated circuit 1.

The arrangement has a data word generator 2 , which is constructed as a feedback shift register. The data word generator 2 is controlled by a clock signal T, by means of which the test process is controlled. With each new edge of the clock signal T, the data word generator delivers a new deterministic data word. Deter ministic in this context means that it is a known sequence of data words, so that for each clock of the clock signal T it is known what the data word supplied by the data word generator 2 looks like.

The data words of the data word generator 2 generated in this way are themselves not yet suitable as test vectors, since the test vectors should have certain bit values that differ from those of the data words.

Means for test pattern generation are therefore provided which generate predetermined deterministic test patterns and target output patterns from the deterministic data words supplied by the data word generator 2 .

The means for generating the test pattern have so-called bit-flipping logics 3 , 4 and 5 , to which the respective bits of a data word are fed on the input side. In the exemplary embodiment according to FIG. 3, for the sake of clarity, the data words provided as the test pattern only consist of 2 bits each and the data words provided as the desired output pattern each consist of one bit.

The bit-flipping logics 3 , 4 and 5 are controlled by means of a bit-flipping controller 6 , which is also part of the means for generating the test pattern. The bit flipping controller 6 controls for each new data word that is supplied by the data word generator 2 as a function of the clock signal T, whose bits are changed individually so that the output of the bit flipping logic 3 , 4 and 5 the desired bits of the respective data words and target output patterns arise, which are thus deterministic.

The bit-flipping logics 3 , 4 and 5 should deliver a data word which is fed to the inputs of the IC to be tested. Furthermore, for each test step they supply a data word as a target output pattern which is compared with the output signal of the IC 1 to be tested.

In the embodiment shown in FIG. 1 for simplicity's sake is the one data word is coupled to the tested IC 1 to the inputs of only 2 bits. For the sake of simplicity, the target output test pattern, which is also to be generated by the means for test pattern generation, consists of only one bit.

In the exemplary embodiment according to FIG. 1, the two bit flipping logics 3 and 4 generate the two bits of each data word which is coupled to the inputs of the IC 1 to be tested. In contrast, the bit flipping logic 5 generates the only bit of each desired output pattern.

The data words supplied by the two bit-flipping logics 3 and 4 are coupled via signal formers 7 and 8 and driver stages 9 and 10 to inputs of the integrated circuit 1 to be tested.

Is coupled to each test step and thus each new data word to be tested by means of the drivers 9 and 10 to the inputs of the integrated circuit 1, the integrated circuit 1 supplies its output side an output pattern, which passes via a driver stage 11 to a comparator 12th The comparator 12 is part of comparison means, which is used to compare the test output pattern of the integrated circuit to be tested with target output patterns.

In the exemplary embodiment according to FIG. 1, as already explained above, the desired output patterns are generated by the bit flipping logic 5 . In this embodiment, it is only 1 bit for each target output pattern.

For each test step, the comparator 12 therefore compares the test output pattern of the integrated circuit 1 to be tested with the respective target output pattern that comes from the bit flipping logic 5 . The output behavior of the integrated circuit can thus be checked for each test step and for each new test pattern or test data word supplied to the integrated circuit 1 .

The evaluation of the results provided by the comparator 12 is carried out in a manner not shown in the figure, for example by means of a simple test system.

Possibly. the integrated circuit 1 or individual elements of this circuit can have an undefined behavior which leads to the fact that not all output signals of the integrated circuit 1 are to be evaluated. In particular, suppression of the output signals can be useful in individual test steps.

For this purpose, masking logic 13 is additionally provided, which controls the comparator 12 so that a comparison does not take place in certain test phases or the comparison result is not passed on for evaluation.

As already explained above, the sequence of testing the integrated circuit 1 is controlled by the clock signal T. With each cycle of this clock signal T, the data word generator 2 delivers a new deterministic data word to the bit-flipping logics 3 , 4 and 5 . Although these are deterministic data words, it must be known at all times what data word it is so that its value is known. To ensure this, a test vector counter 14 is provided, which counts the clock signal T and supplies the counting result to the bit flipping controller 6 and the masking logic 13 . This means that the test phase is always aware of the test phase. The bit flipping controller 6 can thus control the bit flipping logics 3 , 4 and 5 for each new clock of the clock signal T due to the fact that the data word supplied by the data word generator 2 is known so that the output side deliver the desired deterministic data words or target output patterns.

This arrangement according to the invention enables the integrated circuit 1 to be tested without special circuit elements or even on-board test systems being required on the circuit.

The arrangement according to the invention can also basically store a test vector be saved in which otherwise all the bits of each according to the prior art Test vector or test data word are stored individually.

For flexibility, for example in order to use new test vectors that are not provided for the test, a test vector memory 15 can additionally be provided, which by means of electronic switches 16 , 17 , 18 and 19 instead of the outputs of the bit-flipping logics 3 , 4 and 5 on the signal formers 7 and 8 or the comparator 12 can be switched. For each test step, data stored in the test vector memory 15 also determine whether the comparator 12 should compare a target output pattern with the output test pattern actually supplied by the integrated circuit 1 . For this purpose, the electronic switch 19 is provided, by means of which the control of the comparator 12 can be switched either to the test vector memory 15 or to the bit flipping controller 6 .

However, it should be explicitly stated that the test vector memory 15 is only provided optionally and is not required for the function of the arrangement according to the invention.

Rather, their mode of operation consists in designing deterministic data words supplied by the data word generator 2 by means of the bit-flipping controller 6 and the bit-flipping logics 3 and 4 in such a way that the integrated circuit to be tested 1 has test patterns of predetermined deterministic values be fed. The output test patterns supplied on the output side by the integrated circuit 1 to be tested are compared with target test patterns which are compared with target output patterns provided by the bit flipping logic 5 . These target output patterns are also obtained from the deterministic data words of the data word generator 2 by means of the bit flipping logic 5 and the bit flipping control 6 .

In Fig. 2, an arrangement according to the invention for testing an integrated circuit 1 is shown, which is slightly modified compared to that of FIG. 1. The comparison means in particular are constructed differently in the exemplary embodiment according to FIG. 2.

Fig. 2 shows the inventive arrangement for testing of the integrated circuit 21 to a test board 35, which is to be tested between the integrated circuit 21 and a simple test system 36 is connected. The test system 36 is used above all to generate certain clock signals, which will be discussed later, and to evaluate the comparison results.

The arrangement according to the invention constructed on the test board 35 can in particular be implemented as programmable logic.

The arrangement according to the invention according to FIG. 2 has a test vector generator 22 , to which bit-flipping logics 23 , 24 , 25 and 26 are connected. In this case, the bit-flipping logics 23 to 26 serve to generate a 4-bit-wide test pattern with each clock step, which is fed to 4 inputs of the integrated circuit 21 to be tested.

As already explained on the occasion of the exemplary embodiment according to FIG. 1, the bit flipping logics 23 to 26 are also controlled in this exemplary embodiment according to FIG. 2 by means of a bit flipping controller 27 .

A test vector counter 28 is also provided in the exemplary embodiment according to FIG. 2, which controls the bit flipping controller 27 . Furthermore, a masking logic 29 is seen, which is also controlled by the test vector counter 28 .

A test control input of the integrated circuit 1 to be tested is controlled by a control signal which is obtained by linking an AND gate from a signal TC supplied by the test system 36 and a signal supplied by the test vector counter 28 . In this way, the integrated circuit 21 to be tested is controlled such that it takes over new test patterns at the desired times.

In the exemplary embodiment according to FIG. 2, the target output patterns are not generated by means of a data word generator and bit-flipping logics, but rather a compression is used by means of a signature register 30 to compress all the output test patterns of the test sample to be tested, Integrated circuit 21 miteinan the linked and finally evaluated by the test system 36 , wherein a comparison is made with a target output pattern. In each test step, an exclusive-OR link is made for each new data word with the data word that has already been buffered in the signature register 30 . This process is repeated for each new test pattern step. At the end of a test process, the signature result is delivered to the test system 36 , which evaluates this result. The signature register 30 is clocked on the output side as well as the integrated circuit 21 to be tested by means of a clock signal CLK.

With this procedure, it can happen, just as in the embodiment according to FIG. 1, that due to undefined behavior of components in the integrated circuit 21 to be tested, certain outputs of the integrated circuit in certain test phases deliver signals which cannot be evaluated, since they take random values.

In the exemplary embodiment according to FIG. 2, bit modification logics 31 , 32 , 33 and 34 are therefore provided, with which bits that cannot normally be evaluated are modified to specific target values. This is necessary so that there are defined states for each test step at the inputs of the signature register 30 , since only in this way is it possible to link all test patterns which are fed to the signature register 30 over all test steps or to deliver defined results.

In summary, it should be noted that in the exemplary embodiment according to FIG. 1, the data word generator and the means for generating the test pattern, in particular the bit flipping logic and the bit flipping control, serve to generate both test patterns on the input side are supplied to the integrated circuit to be tested, as well as target output patterns which are compared with actual output patterns of the integrated circuit during testing.

In contrast to this, in the exemplary embodiment according to FIG. 2, the data word generator 22 and the means for generating test patterns are used exclusively to generate input test patterns for the object to be tested. In the second exemplary embodiment according to FIG. 2, the output test patterns are linked to one another via a signature register, so that at the end of a test process the signature register supplies a signature result which only represents a data word and which is associated with a target Data word, which is permanently stored in the test system, for example, is compared.

For both embodiments of the invention, testing with a variety of Test vectors is possible without providing extensive test vector memory. Also In both cases, the integrated circuits to be tested do not have to be on-board Test systems include. There is also a modification to the circuits to be tested the integrated circuit is not required.

Claims (10)

1. Arrangement for testing an integrated circuit ( 1 ; 21 ) with a data word generator ( 2 ; 22 ) that delivers deterministic data words, with means ( 3 , 4 , 5 , 6 ; 22 , 23 , 24 , 25 , 26 , 27 ) for test pattern generation, which change the deterministic data words so that predefined, deterministic test patterns, the inputs of an integrated circuit to be tested ( 1 ; 21 ) can be fed, and with comparison means ( 12 ; 30 ) for comparing the test - Output patterns of the integrated circuit ( 1 ; 21 ) with at least one target output pattern, the arrangement being provided outside the integrated circuit ( 1 ; 21 ) to be tested. 2. Arrangement according to claim 1, characterized in that a feedback shift register is provided as the data word generator ( 2 ; 22 ). 3. Arrangement according to claim 1, characterized in that a bit flipping control ( 6 ; 27 ) is provided as means ( 3 , 4 , 5 , 6 ; 22 , 23 , 24 , 25 , 26 , 27 ) for generating the test pattern which controls bit-flipping logics ( 3 , 4 , 5 ; 23 , 24 , 25 , 26 ) in such a way that the deterministic data words are changed bit by bit in such a way that the predetermined, deterministic test patterns arise. 4. Arrangement according to claim 1, characterized in that a masking logic ( 13 ; 29 ) is provided, which causes the comparison means ( 12 ; 30 ) exclusively predetermined test output pattern of the inte grated circuit to be tested ( 1 ; 21 ) with compares the target output patterns. 5. Arrangement according to claim 3 or 4, characterized in that a test pattern counter ( 14 ; 28 ) is provided which counts a clock signal and the counting result to the bit flipping control ( 6 ; 27 ) and / or the masking logic ( 13 ; 29 ) provides. 6. Arrangement according to claim 1, characterized in that a signature register ( 30 ) is provided, which links successive test output patterns with each other and the linking result is compared with a target output pattern. 7. Arrangement according to claim 1, characterized in that the target output pattern by means of the data word generator ( 2 ) and with means ( 3 , 4 , 5 , 6 ) for generating the test pattern are generated. 8. Arrangement according to claim 1, characterized, that the arrangement is implemented as programmable logic. 9. Arrangement according to claim 1, characterized in that the arrangement is provided on a test board ( 35 ) which is connected between a test system ( 23 ) and the IC to be tested. 10. A method for testing an integrated circuit ( 1 ; 21 ), wherein deterministic data words are changed so that predetermined, deterministic test patterns, the inputs of an integrated circuit to be tested ( 1 ; 21 ) can be supplied, test output patterns of the testing integrated circuit ( 1 ; 21 ) with at least one target output pattern, and wherein the method is carried out outside the integrated circuit to be tested ( 1 ; 21 ).