DE10101735C1 - Switch stage acting as input buffer for dynamic random-access memory has difference stage coupled via level converter to memory element providing output signal - Google Patents

Abstract

The switch stage has difference stage (1) with 2 circuit paths (10,13; 11,14), respectively controlled by an input signal (IN) and a reference potential (VREF), a level converter (4) with 2 inverters (41,42), controlled by the outputs (21,22) of the difference stage circuit paths, the input of one inverter coupled to the output of the other inverter and a memory element (5) coupled to the outputs (47,48) of the level converter and providing the output signal (OUT). A switch (20) is connected between the outputs of the difference stage and further switches (45) are used for switching out the level converter and the inputs of the memory element, each of the switches controlled by a clock signal.

Description

The invention relates to a switching stage, the input side an input-side differential stage, a level converter and on the output side comprises an output side storage element.

Switching stages are known to be used to digital signals le to be processed discreetly. Switching stages are common implemented in integrated circuits. There is the Be strive for the lowest possible supply voltage. in particular especially in dynamic semiconductor memories, so-called DRAMs (Dynamic Random Access Memories) can reduce the signal level stroke of the externally applied to the integrated circuit Input signals may be less than the supply voltage. For example, the signal level swing can be between 0.2 V to 1.2 V lie.

In JP 7-245 558 A (summary) there is a difference stage shown, the outputs of each one inverter and one Storage element are connected downstream. The circuit serves as Input stage, for example for an address buffer, one Semiconductor circuit. In JP 5-227 005 A (summary) a differential amplifier is shown, at the output of which short level converters are connected. Finally in JP 3-229 514 A (summary) a difference level ge shows whose branches are connected via a transistor to by shorting the branches depending on one Control signal to increase the working speed.

The object of the invention is to provide a switching stage admit the input signals with low signal level swing ver can work and a high working frequency at possible Achieved minimal switching effort.  

According to the invention, this object is achieved by a switching stage solved according to the features of claim 1.

In the switching stage according to the invention, the outputs the differential level is short-circuited during the idle state. Since in clocked systems the data is only active Clock edge are valid, no information is lost. By short-circuiting the outputs of the differential stage this brought into a level-neutral working point. After this The outputs of the differential stage are unlocked itself in an unstable state, so that the differential level at Apply an input signal depending on its Pe gel is set. Switching from the neutral operating point  in one or the other of the binary switching States of the differential level are therefore relatively quick. Reaching the respective switching state from the neutral Working point is particularly quicker than at for example a switching of caused by the input signal one switching state to the complementary other switching state. The short-circuiting and free the outputs of the differential stage giving switch is a transistor by the operating clock is controllable.

The level converter comprises one of the outputs of the difference level assigned inverter. The inverters are related to ih rer inputs and outputs connected together to make a flip Form flop. For controlling the inverters on the input side are the outputs of the differential stage via respective switches connected to the inputs of the inverters. The feeding of Supply voltage or supply current to the inverter cyclically switchable. For this is the reference voltage side Supply connection of the inverters via a corresponding Switch can be connected to the reference potential connection. The In level converter are during the idle state of the Difference stage switched off.

A storage element is provided on the output side Si determined at the time of sampling the input signal signal level until the next measure stores and at an off provides for subordinate functional elements. at For example, an RS flip-flop is suitable for each leading edges at the set or reset input in one or the other the other of its binary switching states is transferred. During the idle state of the differential level or the abge switched state of the level converter, the inputs of the Storage element brought to a defined potential by they are connected to the positive supply potential. For this purpose, there are corresponding switches at the output of the level wall lers provided that the inputs of the memory element clock-controlled  with the connection for the positive supply potential tial connect.

The switch short-circuiting the outputs of the differential stage is preferably an n-channel MOS transistor. Alternatively, you can a p-channel MOS transistor can also be used. The the In switch of the level converter at the supply connection The switch is preferably an n-channel MOS transistor. The the Outputs of the level converter to positive supply potential Legend switches are preferably p-channel MOS transistors. The n-channel MOS transistor at the outputs of the differential stage fe is therefore directly driven by a clock signal, wäh rend the other n-channel MOS transistors or p-channel MOS Transistors are driven by the inverted clock signal.

The difference stage has a first and a second Rung on. The first branch is indicated by the input signal controls, the second branch is ge from a reference signal controls. The outputs are at respective in the two branches arranged p-channel MOS switched as load elements Transistors connected. The one is expediently capacitive connection to the output of the other from the Refe renzsignal controlled branch of the differential stage coupled. For this purpose, it is the connection of the input signal most differential amplifier branch via a capacitor which is formed from an n-channel MOS transistor on the two th branch of the differential level coupled.

The switching stage according to the invention is particularly advantageous used as the input stage of an integrated circuit det. Here the input signal of the integrated scarf device fed to one of their input signal connections and direct - apart from any circuits for derivation electrostatic discharges, so-called ESD Protection structures - the gate connection one in the input branch the differential stage arranged MOS transistor supplied. The gate connection is therefore apart from the ESD  Protective structure directly, in particular without further intermediate switched switching stage with the input connection of the integrier connected circuit. The input port is becoming more common wise through a connection surface, a so-called connection pad, educated. The connection pad is a metallization surface, on which is stamped on a bond wire that connects to the pad connects with a pin that goes through the housing is guided and integrated from outside the housing Circuit is accessible.

The circuit is expediently carried out in CMOS circuit technology using n-channel MOS transistors and p-channel MOS transistors. The transistor connected to the input signal connection and, if appropriate, the transistor forming the coupling capacitance, the transistor controlled by the reference signal and the transistor short-circuiting the outputs of the differential stage are expediently those which have a low threshold voltage. For example, the power supply 1, 8 V, so that the threshold voltages of said transistors are about 0.3 V and the threshold voltages of the remaining Transisto ren about 0.5 V are. The reference voltage is approximately 1.2 V. Input signals with a level swing of 0.2 V to 1.2 V can then be processed. The signal levels are between +/- 0.1 V and +/- 0.6 V based on the reference potential. By means of the switching stage described, input signals with a relatively low level, which is less than the supply voltage available, can be reliably detected. The Arbeitsgeschwin speed is relatively high, with only a manageable number of components is required. The switching stage according to the invention can therefore be used particularly advantageously as an input buffer for DRAMs.

The invention is based on the in the figure of the Switching step shown in the drawing.  

The switching stage in the figure comprises a differential stage 1 , a level converter 4 and a memory element 5 . The dif ference stage 1 has a first branch or current path which contains an input transistor 10 and a load transistor 13 . The second branch of differential stage 1 comprises a reference transistor 11 and a load transistor 14 . The load transistors 13 , 14 are p-channel MOS transistors with short-circuited gate and drain connections, which are connected to a connection 23 for a positive supply potential VDD at approximately 1.8 V. The source connections of the transistors 10 , 11 are coupled and are connected via a transistor 15 to a connection 24 for reference potential (Mas se) VSS. The transistor 15 serves as a constant current source and is supplied by a constant potential, which is accessed by feeding a constant current IBIAS at a terminal 17 on a transistor 16 connected as a diode. The gate connection of the reference transistor 11 is connected to a reference potential VREF at a connection 18 which has approximately 1.2 V. The gate connection of the transistor 10 is controlled by the input signal IN to be sampled at a connection 6 . The input signal IN is provided by a connection pad 9 , which forms an input of the integrated circuit. The connection 6 is given if necessary only via an ESD protective structure to the connection pad 9 . The outputs 21 , 22 of the differential stage 1 are connected to the coupled drain and source connections of the load transistors 13 , 14 .

The drain-source path of a switching transistor 20 is connected between the output connections 21 , 22 . The transistor 20 can be an n- or a p-channel MOS transistor. The transistor 20 is controlled by a clock signal CLK, which is provided at a terminal 7 .

In the idle state of differential stage 1 , transistor 20 is turned on , so that the output connections 21 , 22 of differential stage 1 are short-circuited. To sample the input signal IN, the transistor 20 is switched off after a falling edge of the clock signal CLK. Difference stage 1 , which had previously been in a neutral operating point, is now brought into one of its stable operating points depending on the signal level of the input signal IN. If the level of the input signal IN is above the reference potential VREF at the time of sampling, then the transistor 11 is driven more strongly than the transistor 10 . After reaching the stable working state, the transistor 11 is conductive, the transistor 10 is blocked. The reverse applies if the input signal IN is below the reference potential VREF. At the output 22 there is a low level in the example described, at the output 21 a high level. Even slight differences between the input signal IN and the reference potential VREF are sufficient to bring the differential stage into one of its stable states after the outputs 20 have been short-circuited in the idle state. Since the switching stage is in a neutral, unstable operating point, the switch to the stable switching state takes place extremely quickly. It is irrelevant in which stable state the differential stage was previously.

The input terminal 6 is connected via a transistor GE connected as a capacitor 12 to the drain terminal of the transistor 11 in the reference branch of the differential stage. The drain and source connections of the transistor 11 are coupled with each other and connected to the drain connection of the transistor 11 , which also forms the output 22 of the differential stage 1 . An edge of the input signal IN is thereby coupled directly to the reference branch of differential stage 1 . This compensates for the parasitic gate-drain capacitance of the input transistor 10 . The symmetry of the differential stage is increased by the capacitor 12 in particular on steep edges of the input signal IN.

The level converter 4 is connected downstream of the outputs 21 , 22 . The level converter 4 each has an inverter 41 or 42 assigned to the outputs 21 , 22 of the differential stage 1 . The input of the inverter 41 is formed by its coupled gate connections and is connected to the output of the inverter 42 , which is formed by the coupled drain connections of its transistors. Accordingly, the input of the inverter 42 is connected to the output of the inverter 41 . This creates a flip-flop. The inputs of the inverters 41 , 42 are controlled by the outputs 21 , 22 of the differential stage 1 via respective switches 43 , 44 . The switches 43 , 44 are p-channel MOS transistors, the drain-source paths of which connect the inputs of the respective inverters 41 , 42 to the connection 23 for the positive supply potential VDD. On the gate side, transistors 43 , 44 are driven by outputs 21 , 22 of differential stage 1 .

In the idle state of differential stage 1 , the outputs 21 , 22 of which are short-circuited by transistor 20 , switching transistors 43 , 44 are switched off. Subsequently, the output from the outputs 21 , 22 of the differential stage 1 are amplified by the switches 43 , 44 and ensure that the level converter 4 assumes a switching state corresponding to the connections 21 , 22 present at the signal level. Simultaneously with the switching off of the transistor 20 , the inverter 41 , 42 with current supplying transistor 45 is turned on . Simultaneously with the sampling of the input signal IN by the differential stage 1 , the level converter 4 is brought into a switching state derived from the input signal IN accordingly.

The signal connections 47 , 48 of the level converter 4 are fed to a memory element 5 . In the exemplary embodiment shown, two inverters 51 , 52 connected in series are provided for signal amplification in each signal path. The memory element 5 is an RS flip-flop, which changes its switching state as a function of a pulse at the set or reset input. The memory element 5 provides at its output terminal 8 an output signal OUT corresponding to the sampled input signal IN until a different signal level is sampled at the input signal IN. While the differential stage 1 is in the idle state, the signal connections 47 , 48 of the level converter or the corresponding signal inputs of the memory element 5 are connected via respective switches 53 , 54 to the connection 23 for the positive supply potential VDD. The switches 53 , 54 are p-channel MOS transistors which are driven by the clock signal CLK, which is inverted via the inverter 46 . The Transisto ren 53 , 54 are thus driven by the same phase of the clock signal CLK as the transistor 45th During the scanning phase of the differential stage 1 , the inverters 41 , 42 of the level converter 4 are thus supplied with current via the transistor 45 , while the transistors 53 , 54 are switched off. As a result, the level of the signal connections 47 , 48 can be set accordingly according to the control by the input signal IN.

In summary, for the sampling of a level of the input signal IN, the difference stage 1 previously in the idle state is released, so that complementary signal levels are set as a function of the input signal IN at their output terminals 21 , 22 . These signal levels are amplified via the transistors 43 , 44 to the feedback inverter-containing level converter 4 , which accordingly adjusts its signal state. Complementary signal levels are now available at the output-side signal connections 47 , 48 of the level converter 4 and have level values at the level of the supply potentials VDD, VSS. Simultaneously with the release of the output connections 21 , 22 of the differential stage 1 , the level converter 4 is connected to ground via the transistor 45 and the output connections 47 , 48 of the level converter 4 are disconnected from the positive supply potential VDD by blocking the transistors 53 , 54 . The RS flip-flop 5 adjusts itself according to the levels of the connections 47 , 48 . The output signal OUT at the output terminal 8 now provides the level of the input signal IN for the subsequent signal processing until the next sampling clock of the clock signal CLK.

LIST OF REFERENCE NUMBERS

1

switching stage

4

level converter

5

storage element

6

.

7

input terminal

8th

output terminal

9

connecting pad

10

.

11

transistors

12

capacitor

13

.

14

load transistor

15

.

16

transistor

17

Connection

20

switch

21

.

22

output terminal

23

.

24

Supply potential connection

41

.

42

inverter

43

.

44

switching transistors

45

transistor

46

inverter

47

.

48

output terminals

51

.

52

inverter

53

.

54

transistors
VDD, VSS supply potentials
VREF reference potential
IBIAS constant current
CLK clock signal
OUT output signal

Claims (9)

1st switching stage, comprising:
a differential stage ( 1 ) with a first ( 10 , 13 ) and a second ( 11 , 14 ) branch, of which the first branch ( 10 , 13 ) can be controlled by an input signal (IN) and of which the second branch ( 11 , 14 ) can be controlled by a reference potential (VREF) and each has an output ( 21 , 22 ) connected to the branches;
a level converter ( 4 ) comprising a first and a second inverter ( 41 , 42 ), each of which can be controlled by one of the outputs ( 21 , 22 ) of the differential stage ( 1 ), and wherein the input of the one inverter ( 41 ) connected to the output of the other inverter ( 42 );
a memory element ( 5 ) which is connected on the input side to output connections ( 47 , 48 ) of the level converter and has an output ( 8 ) for tapping an output signal (OUT);
a first switch ( 20 ) connected between the outputs ( 21 , 22 ) of the differential stage ( 1 );
respective further switches ( 45 ) for switching off the level converter ( 4 ) and for switching off the inputs ( 53 , 54 ) of the memory element ( 5 ); and
a connection ( 7 ) for supplying a clock signal (CLK) through which the first ( 20 ) and the further switches ( 45 , 53 , 54 ) can be switched. 2. Switching stage according to claim 1, characterized in that the first switch ( 20 ) is a transistor, the controlled path between the outputs ( 21 , 22 ) of the differential stage ( 1 ) is connected and its control connection with the connection ( 7 ) for supply of the clock signal (CLK) is connected. 3. Switching stage according to one of claims 1 or 2, characterized in that the further switch ( 45 ) for switching off the level converter ( 4 ) between a supply connection of the inverters ( 41 , 42 ) of the level converter ( 4 ) and a connection ( 24 ) for a first supply potential (VSS) is connected and that this switch ( 45 ) can be controlled as a function of the clock signal (CLK). 4. Switching stage according to claim 3, characterized in that the further switches ( 53 , 54 ) for switching off the inputs of the memory element ( 5 ) each between one of the inputs of the memory element ( 5 ) and a connection ( 23 ) for a further supply potential ( VDD) are switched and that these switches ( 53 , 54 ) can be controlled depending on the clock signal (CLK). 5. Switching stage according to claim 4, characterized in that the first switch ( 20 ) directly and the further switches ( 45 , 53 , 54 ) via an inverter ( 46 ) with the connection ( 7 ) for leading to the clock signal (CLK) are. 6. Switching stage according to claim 3, characterized in that respective switches ( 43 , 44 ) are provided between ei nen connection ( 23 ) for a second supply potential (VDD) and one of the inputs of the inverters ( 41 , 42 ) of the level converter ( 4 ) are connected and each of which can be controlled by an output ( 21 , 22 ) of the differential stage ( 1 ). 7. Switching stage according to one of claims 1 to 6, characterized in that a capacitive element ( 12 ) is provided through which a connection ( 6 ) for the input signal (IN) to the second branch ( 11 , 14 ) of the differential stage ( 1 ) is coupled. 8. Switching stage according to one of claims 1 to 7, characterized by an input connection ( 9 ) of an integrated circuit containing the switching stage, through which the input signal (IN) can be provided. 9. Switching stage according to one of claims 1 to 7, characterized in that the differential stage ( 1 ), the level converter ( 4 ), the SpeI cherelement ( 5 ) and all switches ( 20 , 45 , 43 , 54 , 43 , 44 ) MOS Transistors contain and that those Transisto ren, which the input signal (IN) and the reference signal (VREF) can be fed and the first switch ( 20 ) have a threshold voltage which is lower than the threshold voltage of the other transistors.