DE10058947A1 - Non-volatile NOR single-transistor semiconductor memory cell and associated semiconductor memory device, production method and method for programming it - Google Patents

Abstract

The invention relates to a non-volatile NOR single-transistor semiconductor memory cell and associated semiconductor memory devices, production methods and methods for programming them, a bit line (BL, 7, 10) for driving the source / drain regions (S / D) line by line essentially below the word lines (WL1 ) for column-wise control of the control layer (13) of a single-transistor semiconductor memory cell and above the source / drain regions (S / D) is arranged. Due to the elimination of additional contact and the sublithographic formation of the bit lines, this results in a greatly reduced area requirement and an improved integration density.

Description

The present invention relates to a non-volatile ge NOR single-transistor semiconductor memory cell, an associated rige semiconductor memory device, a manufacturing method and a method for programming them and in particular on a flash EPROM memory cell or an associated one EPROM memory with a "virtual ground" architecture.

To store larger amounts of data are currently in Re Chen units or computers usually magnetic plat ten drives used. Such disk drives need however, a relatively large space and have a variety moving parts. As a result, they are prone to failure and have a considerable power consumption. About that In addition, the future computing units or computers as well as other digital devices such as digital Ka meras, music players or PALM devices getting smaller, which is why conventional mechanical storage devices are suitable.

As an alternative to such conventional mechanical memory devices, non-volatile semiconductor memory devices have recently become increasingly popular, as are known, for example, as flash memories, E ² PROM, EPROM and the like. The most important representatives of such electrically erasable and electrically programmable memory devices are the so-called NAND and NOR semiconductor memory devices. In both semiconductor memory devices, the memory cells have so-called single-transistor memory cells, a drain region and a source region being usually formed in an active region of a semiconductor substrate, and an insulated charge-storing layer and an insulated control layer arranged above it being located above the channel section in between. To program such a single transistor memory cell, relatively high voltages are applied to the control layer and the drain region. In such circumstances, charge carriers are introduced into the charge storage layer, for example by means of channel injection, injection of hot charge carriers and / or Fow ler-Nordheim tunnels. The charge carriers remain in the charge storage layer and permanently change the switching behavior of the respective field effect transistor.

While in NAND semiconductor memory devices a variety of single transistor memory cells connected in series are and via a common selection gate or one Selection transistor are driven, are the respective Single transistor memory cells in NOR semiconductor memory directions organized in parallel or in a matrix, whereby each memory cell can be selected individually.

Fig. 1 shows a simplified representation of an equivalent circuit diagram of a conventional non-volatile NOR semiconductor memory device with so-called "common-source" architecture. Referring to FIG. 1, a plurality of Eintransis gate memory cells T1, T2,. , , arranged in a matrix, ie rows and columns. As already described above, each single transistor memory cell T1, T2,. , , from mutually spaced drain and source regions D and S. which are formed in an active region of a semiconductor substrate. A control gate CG (control gate) is here in each case line by line with an associated word line WL1, WL2, WL3,. , , connected. In contrast, the drains are D of the respective single-transistor memory cells T1, T2,. , , with a respective bit line BL1, BL2,. , , connected in columns. The source regions S of the non-volatile NOR semiconductor memory device are all connected to ground or are all connected to one another, which is why such a NOR semiconductor memory device is referred to as a memory device with a “common-source” architecture.

FIG. 2 shows a simplified plan view of a layout of a single-transistor semiconductor memory cell according to the prior art, as is used, for example, in a conventional semiconductor memory device according to FIG. 1.

Referring to FIG. 2, a substantially T-shaped active region AA is formed in a semiconductor substrate by means of trench isolation STI (shallow trench isolation), in which the transverse area of a common source region S determines the semiconducting terspeichereinrichtung. In contrast, in the upper area there is a drain region D with an associated contact K for connecting a respective bit line BL1. In order to implement a field effect transistor or a transistor semiconductor memory cell, an insulated charge-storing layer 3 and a word line WL1 insulated therefrom for driving the cell transistor are located between the drain region D and the source region S.

A disadvantage of such a conventional single transistor However, semiconductor memory cell is the relatively high space May, in particular from the presence of a respective only contact K results for each memory cell. Beyond that results from a semiconductor memory realized with it chereinrichtung due to the high density of contact holes a relatively high defect density and sensitivity in the Production. Since the word lines also consist of a finally doped polysilicon layer exist furthermore, so-called "depletion" or impoverishment effects a reduction in the capacitive coupling to the charge lead storage layer. This usually has to be done by a compensate for larger cell area or higher control voltages be settled. Especially with future technologies this problem is significant since the control polysilicon layer or word line usually by means of ion implantation  together with the source / drain regions S / D the.

The invention is therefore based on the object of volatile NOR single transistor semiconductor memory cell and egg ne associated semiconductor memory device, a manufacturer and a method for programming them admit, with minimal control voltages a minimal Cell area and thus high integration density can be realized is.

According to the invention, this task is performed with regard to the non- volatile NOR single transistor semiconductor memory cell with the Features of claim 1 and with regard to the procedure rens solved by the measures of claim 8. Further is the semiconductor memory device by the features of Claim 19 and the method for programming them solved by the measures of claim 20.

In particular, through the use of bit lines that are in the Essentially below the word lines and above the Source / drain areas are arranged, you get a NOR Single transistor semiconductor memory cell with minimal area needs, because in particular the area-intensive areas for the external contacts are eliminated.

The bit line preferably touches the source / drain regions immediately and consists of an in-situ-doped polysili ziumschicht. In this way, existing in the bit line diffuse the dopants into the source / drain regions and make an almost ohmic contact. For improvement The conductivity of the bit lines can also be determined from si Licated polysilicon exist, which increases the access further reduce times.

A control layer and the word lines are preferred formed with a metal-containing material, whereby  very low sheet resistances compared to ago conventional poly or polycide layers or word lines give and the realization of very short access times becomes possible. To avoid diffusion or ver The electrical properties can deteriorate Control layer and the word lines further barrier layers exhibit.

The charge storage layer consists, for example, of egg ner electrically conductive polysilicon layer. However, it can in the same way also from a non-conductive layer stand, resulting in the occurrence of leakage currents and Have cargo hold times significantly improved.

By using a sacrificial layer or a dummy Control gates can initially be known during manufacture Procedures are used where the embedded bitlei lines and overlying word lines only to a late later point in time.

Preferably, CMP- Process and / or further etching process for thinning out selectively tiv for a protection surrounding the actual transistor shift carried out.

In the same way, the sacrificial layer and one can also represent selectively to side walls via arranged mask layer Water protective layer are removed, which is a relative simple implementation of the embedded bit lines results.

To program a selected cell in such a way A NOR line becomes a word line to a first potential and all on one side of the chose bit lines on a second Po tential while everyone else on the other side of the selected cell located bit lines to a third Po potential. With such a "virtual ground" -  Architecture and control are obtained in addition to the minimum Cell area and the very short access times beyond from very small control voltages in connection with very ge leak currents in the rest of the cell field.

In the further claims further advantageous Ausges characterized circuits of the invention.

The invention is illustrated below by means of an embodiment game described in more detail with reference to the drawing.

Show it:

Figure 1 is a simplified representation of an equivalent circuit diagram of a non-volatile NOR semiconductor storage device with "common source" architecture according to the prior art.

FIG. 2 shows a simplified plan view of a NOR single-transistor semiconductor memory cell used in FIG. 1 according to the prior art;

Fig. 3 is a simplified plan view of a semiconductor memory device according to the invention;

Fig. 4 is a simplified plan view of the semiconductor memory device according to the invention in a writing state; and

FIGS. 5A-5B and 12A to 12B simplified Schnittansich th of the NOR semiconductor memory device according to FIG. 3 ent long a section AA 'and BB' illustrating respective manufacturing steps.

Fig. 3 shows a simplified plan view of a non-volatile NOR semiconductor memory device, a plurality of strip-shaped active areas AA with associated source / drain regions S / D being formed in a semiconductor substrate by means of trench isolation STI (shallow trench isolation). Above the channel regions between the source / drain regions there are a multiplicity of isolated charge-storing layers and insulated control layers 13 which are connected to a multiplicity of column-shaped word lines WL1, WL2, WL3 and WL4. Directly between the control layers 13 arranged in rows are bit lines BL1 to BL4, for example directly on the substrate surface or directly on the source / drain regions and the trench isolation STI.

Since in this way the formation of conventional contacts K, as shown in FIG. 2, is omitted, there is a substantial reduction in a cell area for a selected cell AZ, which is now in a range of 4F.2F = 8F ² , where F represents a smallest structure size to be realized lithographically. This saving of the cell area also results from a non-lithographic design of the bit lines, which essentially result from a separation between the cells arranged in rows. In addition, both the control layers 13 and the word lines WL1 to WL4 can now have a metal, as a result of which the layer resistances can be significantly reduced in comparison to conventional polysilicon or polycide layers and very good access times are possible.

Fig. 4 shows a simplified plan view of the NOR semiconductor memory device during a programming step, where the same or similar layers or elements as in Fig. 3 denote the same reference numerals and a repeated description is omitted below.

For programming or writing of a selected cell in the AZ NOR semiconductor memory device shows a first potential to a selected word line WL2 is in accordance. 4 created. For example, a voltage of +10 V can be used for this. To implement a so-called "virtual ground" architecture, all bit lines BL1 and BL2 located on one side of the selected cell AZ are connected to a second potential, for example +5 V. More specifically, all bit lines above the selected cell AZ have the same potential. Furthermore, a third potential, for example 0 V, is applied to all other bit lines BL3 and BL4 located on the other side of the selected cell AZ, as a result of which a voltage drop between the source / drain regions and the control layer 13 required for programming is applied exclusively to the selected cell AZ or the word line WL2 is present. Since the bit lines are essentially divided into two areas above and below the selected cell, each with the same potential, there is no voltage drop between the bit lines in this area, which is why the occurrence of leakage currents is minimal. In addition, since the non-selected word lines WL1, WL3 and WL4 are preferably at a ground potential of 0 V, there are also no undesired leakage currents between these lines, so that the occurrence of leakage currents in the rest of the cell field is also minimized and precisely a selected cell AZ can be addressed from the cell field.

To illustrate the invention, the non-volatile NOR semiconductor memory device according to FIGS . 3 and 4 will be described in detail below with reference to the respective manufacturing steps. FIGS. 5A to 12A in this case each show weils sectional views taken along a section AA 'in Fig. 3, while Fig. 5B to 12B show simplified sectional views taken along a section BB' represent in Fig. 3.

According to Fig. 5A and 5B is initially in a Halbleitersub strat 1, a plurality of strip-shaped Speicherzellensta PelN disposed linearly substantially from formed. Each memory cell stack essentially consists of source / drain regions S / D formed in active regions AA, the active regions AA being formed in strips in the semiconductor substrate 1 essentially by means of flat trench insulation STI. To implement a first insulating layer 2 , a charge-storing layer 3 , a second insulating layer 4 and a gate layer 5 , conventional manufacturing methods for non-volatile single-transistor semiconductor memory cells are preferably used, which will not be described in more detail below.

The first insulating layer 2 consists, for example, of a silicon dioxide layer which serves as a tunnel oxide and is preferably formed thermally on the silicon semiconductor substrate 1 . The charge-storing layer 3 consists, for example, of a highly doped or electrically conductive polysilicon layer and serves as a so-called floating gate. However, the charge-storing layer 3 can also have a non-conductive charge-storing layer, as are used, for example, in SONOS cells. The second insulating layer 4 consists, for example, of an ONO layer sequence (oxide / nitride / oxide), although other dielectric materials can also be used. In particular, dielectrics with a high relative dielectric constant can be used, whereby a coupling factor can be improved and the threshold voltages can be reduced. As gate layer 5 , in turn, an electrically conductive polysilicon layer known from conventional single-transistor semiconductor memory cells is used, which, however, only serves as a sacrificial layer in accordance with the present invention and is therefore also referred to as a so-called “dummy control gate”.

To protect this layer stack or strip-shaped memory cell stack, a protective layer is used which essentially consists of a mask layer 6 and a side wall protective layer 8 and 9 . The mask layer 6 serves, for example, as a hard mask and can have an oxide. Furthermore, a side wall insulating layer 8 , which has, for example, an oxide, can be formed on the side walls of the memory cell stack, as a result of which damage to the first and second insulating layers and the charge-storing layer 3 can be prevented during ion implantation to form the source / drain regions S / D , Furthermore, the side wall protective layer sits a spacer 9 , which has an oxide in example.

A first conductive layer 7 is then formed over the entire surface of the strip-shaped memory cell stacks, which has, for example, a highly doped or electroconductive semiconductor layer. Preferably, (e.g. with phosphorus) in situ-doped polysilicon is deposited as the first conductive layer 7 , as a result of which dopants diffuse into the source / drain regions at the contact surfaces to the source / drain regions in subsequent thermal treatment steps and thus have an almost ohmic resistance Allow contact.

According to FIG. 6A and 6B in a subsequent Her provision step a rear formation of the first conductive layer 7, said layer-for example, first by means of a CMP process using the preferably made of a nitride mask layer 6 as a detection medium and stop a polishing back the first conductive layer 7 takes place. In addition, according to FIG. 6B, a further thinning of the first conductive layer 7 can in turn be carried out selectively with respect to the mask layer 6 and the spacer 9 , as a result of which possible short circuits or remaining connection regions between the respective bit lines can be reliably prevented. For example, a temporary dry etching is carried out for this purpose. According to FIG. 6B, the first conductive layer 7, which acts as a bit line, lies directly on the source / drain regions S / D and can have a structure width which is below a minimum photolithographic structure width F.

To improve an electrical conductivity or to shorten the access times in the semiconductor memory device, the regenerated first conductive layer 7 can optionally be provided with a highly conductive second conductive layer 10 according to FIG. 7B. For realizing such a second conductive layer 10, siliconization of the exposed strip-shaped poly layers or first conductive layers 7 is preferably carried out. The first conductive layer 7 and the second conductive layer 10 consequently already implement the bit lines of the semiconductor memory device, no special contacts as in the prior art according to FIG. 2 being necessary for contacting the associated source / drain regions S / D. As a result, he already saves a substantial amount of space and reduces the defect density for a memory cell.

According to Fig. 8B is a drit th insulating layer 11 is to insulate the plurality of Bitlei obligations and first and second conductive layers 7 and 10 is performed in a subsequent step. For example, an oxide is deposited over the entire surface of the wafer by means of an LPCVD method and then, by means of, for example, a CMP method, again using the mask layer 6 as an etching stop and CMP detection medium, planarization is carried out. Along a section BB 'there is consequently a sectional view as shown in FIG. 8B.

To implement a large number of single-transistor memory cells arranged in the form of a matrix, however, the mask layer 6 must subsequently be structured in columns as shown in FIG. 8A, for example a stripe mask and a selective anisotropic etching of the mask layer 6 , which preferably has a nitride. Due to the selective etching, the last deposited third insulating layer 11 or the oxide remains and thus protects the buried bit lines BL or the first conductive layer 7 and the second conductive layer 10 .

According to FIGS. 9A and 9B, the stripe-shaped memory cell stacks are structured in a plurality of single-transistor memory cells in a subsequent step, the sacrificial layer 5 , the second insulating layer, now being selective to oxide and nitride using the “mask islands” 6 4 and the charge storage layer 3 are partially removed.

Filled as shown in FIG. 10A and 10B such exposed trenches are in a subsequent step by means of a fourth lierschicht Iso 12, for example, represents a HDP-TEOS layer. According to FIGS. 10A and 10B, only island pieces of the original mask layer or hard mask 6 are present at this time.

These are selectively removed in a subsequent step, for example with hot phosphoric acid. Another selective etching, for example with KOH, removes the sacrificial layer 5 or the "dummy control gate" of the respective one-transistor memory cells, the excellent selectivity of KOH being used for the oxide and thus, for example, when using an ONO layer sequence as second insulating layer 4 this is practically not attacked. In this way, the sectional views shown in Figs. 11A and 11B are obtained.

Referring to FIG. 12A and 12B in a subsequent step for the respective one-transistor memory cells, a control layer 13, preferably being carried out a deposition of a metal layer or metal-containing layer which application for example by means of a CMP method under Ver the third insulating layer 11 as a stop layer plan is aryanized. Due to the use of a metal or a metal-containing layer for the control layer 13 of the single-transistor memory cell, a particularly high conductivity and thus particularly short access times are obtained. Under certain circumstances, a stack of a barrier layer, not shown, such as, for. B. TiN and a metal the, whereby the reliability of the semiconductor device can be improved.

According to Fig. 13A and 13B is in a final herstel treatment step a further metal layer or metal-wise de layer is deposited after its structuring, the actual word lines WL1, WL2, WL3, etc. form. In this case too, a stack can again be deposited from a barrier layer, not shown, such as TiN and a metal, whereby the electrical properties can be further improved. A misalignment can be tolerated to a certain extent, since the control layer 13 has an extraordinarily high conductivity and is directly limited by the fourth insulating layer 12 .

According to Figs. 12A to 13B, the control layer 13 and the word lines WL1 to WL3 are made in different steps forth. The formation of the control layer 13 and the word lines WL1 to WL3 can, however, also take place in a simultaneous step, but due to the now narrower word line / word line spacing, a capacitive load on the word lines is increased and the access times deteriorate as a result.

The rest of the process management takes place in the same way as for the stand the technology, which is why after a detailed description is subsequently waived.

The invention has been described above on the basis of silicon semi-lead described. However, it is not limited to this and includes all other semiconductor materials in the same way lien. Furthermore, for the word lines and the tax layer uses a metal. However, it can be done in the same way  also used an electrically conductive semiconductor material become.

Claims (20)

1. Non-volatile NOR single transistor semiconductor memory cell with
an active region (AA) formed in a semiconductor substrate ( 1 );
spaced-apart source / drain regions (S / D) which are formed in the active region (AA);
a first insulating layer ( 2 );
a charge storage layer ( 3 );
a second insulating layer ( 4 );
a control layer ( 13 );
a word line (WL) for column-wise control of the control layer ( 13 ); and
at least one bit line (BL) for driving the source / drain regions (S / D) line by line,
characterized in that the at least one bit line (BL, 7) is arranged essentially below the word line (WL) and above the source / drain regions (S / D). 2. Non-volatile NOR single transistor semiconductor memory cell according to claim 1, characterized in that the at at least one bit line (BL) the source / drain regions (S / D) un indirectly touched. 3. Non-volatile NOR single-transistor semiconductor memory cell according to claim 1 or 2, characterized in that the at least one bit line (BL) has an in-situ doped polysilicon layer ( 7 ). 4. Non-volatile NOR single-transistor semiconductor memory cell according to one of the claims 1 to 3, characterized in that the at least one bit line (BL) has a silicide layer ( 10 ). 5. Non-volatile NOR single-transistor semiconductor memory cell according to one of the claims 1 to 4, characterized in that the control layer ( 13 ) has a metal. 6. Non-volatile NOR single-transistor semiconductor memory cell according to one of the claims 1 to 5, characterized in that the control layer ( 13 ) has a barrier layer. 7. Non-volatile NOR single-transistor semiconductor memory cell according to one of the claims 1 to 6, characterized in that the charge-storing layer ( 3 ) has an electrically conductive or non-conductive layer. 8. A method for producing a semiconductor memory device with the steps:

• a) forming a plurality of strip-shaped memory cell stacks in a semiconductor substrate ( 1 ) with source / drain regions (S / D) formed in active regions (AA);
  a first insulating layer ( 2 );
  a charge storage layer ( 3 );
  a second insulating layer ( 4 );
  a gate layer ( 5 ); and
  a protective layer with a mask layer ( 6 ) and a side wall protective layer ( 8 , 9 ), the gate layer ( 5 ) representing a sacrificial layer;
• b) forming a plurality of bit lines (BL) between the stripe-shaped memory cell stacks;
• c) forming a third insulating layer ( 11 ) for isolating the plurality of bit lines (BL);
• d) structuring the strip-shaped memory cell stacks into a multiplicity of single-transistor semiconductor memory cells;
• e) removing the mask layer ( 6 ) and the sacrificial layer ( 5 ) of the single-transistor semiconductor memory cells;
• f) forming a control layer ( 13 ) for the single transistor semiconductor memory cells; and
• g) forming a plurality of word lines (WL) to close the control layer ( 13 ).

9. The method according to claim 8, characterized in that in step b) a first conductive layer ( 7 ) is deposited over the entire surface and then re-formed. 10. The method according to claim 9, characterized in that an in-situ doped polysilicon layer is deposited as the first conductive layer ( 7 ). 11. The method according to claim 9 or 10, characterized in that forming the back of the first conductive layer ( 7 ) has a CMP method. 12. The method according to any one of claims 9 to 11, characterized in that the back of the first conductive layer ( 7 ) further comprises a thinning selectively to the protective layer ( 6 , 9 ). 13. The method according to any one of claims 9 to 12, characterized in that a second conductive layer ( 10 ) is further formed in step b). 14. The method according to claim 13, characterized in that the second conductive layer ( 10 ) is formed by siliconizing the re-formed first conductive layer ( 7 ). 15. The method according to any one of claims 8 to 14, characterized in that in step c) the third insulating layer ( 11 ) is deposited over the entire surface by means of an LPCVD method and is then selectively planarized to the mask layer ( 6 ) by means of a CMP method. 16. The method according to any one of claims 8 to 15, characterized in that in step d) portions of the sacrificial layer ( 5 ) of the second insulating layer ( 4 ) and the charge-storing layer ( 3 ) are removed up to a trench insulation (STI). 17. The method according to any one of claims 8 to 16, characterized in that in step e) the mask layer ( 6 ) and the sacrificial layer ( 5 ) to the side wall protective layer ( 8 , 9 ) and the third insulating layer ( 11 ) is removed , 18. The method according to any one of claims 8 to 17, 1 characterized in that in step f) and / or g) metal-containing material for the control layer ( 13 ) and / or the word lines (WL) is used. 19. NOR semiconductor memory device with a variety of non-volatile NOR single transistor Semiconductor memory cell according to one of the claims 1 to 7, the variety of word lines (WL) and bitlei lines (BL) are switched on in columns and rows. 20. A method for programming a selected cell (AZ) in a NOR semiconductor memory device according to claim 19 with the steps:

• a) applying a first potential to a selected word line (WL2) of the selected cell (AZ);
• b) applying a second potential to all bit lines (BL1, BL2) located on one side of the selected cell (AZ); and
• c) Applying a third potential to all further bit lines (BL3, BL4) located on the other side of the selected cell (AZ).