DE10058214A1 - Data bus supports two different types of memories and has controlled switching stages - Google Patents

Abstract

The data bus[1] supports two different types of memory module [2,3] coupled by switching stages [6] and using line terminators [7]. The switching stages are controlled by a data bus controller [5]. The controller generates addresses to access the respective memories.

Description

The invention relates to a data bus for a first memory chermodule and a second memory module, in particular one first memory module that can be operated on an LVTTL data bus and a second memory module connected to an SSTL-2-Da tenbus is operable.

A recurring occurs every few years fundamental change in technology for memory construction stones, such as those used in personal computers can be set. Likewise, often changes the data bus system used to get data from a memory read module or write data into it. This is done to ensure the performance of each used data bus to the rapidly growing capacity of the to adapt to newer memory modules.

With a change of technology of the memory modules and one associated change in the technology of the data bus system it is usually not possible to use the ones previously used To operate memory modules with the new data bus. The logical provided on the data bus system Differentiate voltage level or data transmission protocols usually differ from each other. In particular, at correspondingly higher data transmission frequencies adapted line termination facilities necessary to Reduce signal reflections.

To share memory devices of different technology together So far it has been necessary to use a computer system maneuverable, the different memory modules from each other the separate data bus systems. In particular with today's data bus widths of 64 bits and more  this requires enormous additional wiring wall.

It is therefore an object of the invention to provide an improved system to make available at the different storage mo can be operated.

This object is achieved by a data bus according to claim 1 and solved by a storage system according to claim 8. More before partial configurations are in the dependent claims specified.

According to the invention, a data bus for a first memory module and a second memory module is provided. The data bus points a line termination facility, while still a Switching device is provided in order to address of the first memory module the line termination device disconnect from each line of the data bus and at one Addressing the second memory module from the line connecting device to each line of the data bus gene.

In this way, two can be advantageously achieved to connect different memory modules to one data bus. The switching device makes it possible to advance the data bus in this way see that either the first memory module or the second Memory module can be operated on it. The switching device be acts that the memory modules either have a data bus a line termination facility or without a line Find the graduation facility. The switching device will controlled so that it depends on the memory module to be controlled those required for the respective memory module electrical conditions on the data bus. The before part of this invention is that for the operation of two un Different memory modules that hold different data bus configurations require only one data bus  must become. This minimizes the wiring effort since a second data bus is not required.

According to a preferred embodiment of the invention, provision is now made to connect memory modules that can be operated on an LVTTL data bus and memory modules that can be operated on an SSTL-2 data bus to a common data bus. Without a further measure, it is initially not possible to connect a memory module that can be operated on an LVTTL data bus to an SSTL-2 data bus. Because of the line termination device usually provided for SSTL-2 data buses, the signal levels of 2.4 V for high signals and 0.4 V for low signals required for the LVTTL data buses would be due to a voltage potential present via a terminating resistor V _TT not reached. As a result, the memory modules that are intended for connection to an LVTTL data bus would not function on an SSTL-2 data bus.

Memory provided for an SSTL-2 data bus can also be used modules cannot be operated on an LVTTL data bus. The high data transmission frequencies as well as double the data rate cause at the unmatched ends of the data bus line reflections on an LVTTL data bus significant disruption in data transmission where by using an SSTL-2 memory module on one LVTTL data bus is not possible.

In a further preferred embodiment can be provided be that the switching device divides the data bus to switch between a read end of the data bus and the Switching device, the first memory module and between the Switching device and the line termination device that second memory module is arranged. That way he can be enough that with an open switching device the first memory module, which is preferably provided that it's on a bus with no line termination facility  is operable with an open switching device is controllable. If the switching device is closed, so there is a line termination on at one end of the data bus direction and the second memory module that on a Da tenbus can be operated with a line termination device can be controlled.

An essential embodiment of the invention is in the fol genden explained in more detail with reference to the drawings. Show it:

Figures 1a shows an inventive data bus system in which both memory modules, which are operable at a LVTTL data bus, and memory modules which are operable in a SSTL-2 data bus connected. and

Fig. 1b, a line termination circuit, as it is operated on the Da tenbussystem according to Fig. 1a.

Fig. 1a shows an inventive data bus system 11 to which two LVTTL memory modules 2 and two SSTL-2 memory modules 3 are connected in parallel. The data bus system 1 has data bus lines 4 which have bus terminators 5 at one end and line terminators 7 at another end. The data bus lines 4 are divided by a switching device 6 , so that the LVTTL memory modules 2 are located between the data bus control device 5 and the switching device 6 and the SSTL-2 memory modules 3 are located between the switching device 6 and the line terminations 7 . The switching device 6 is connected via a control line 8 to the data bus control device 5 , so that the data bus control device 5 controls the switching device 6 to the part of the data bus lines 4 to which the SSTL-2 memory modules 3 and the line terminations 7 are connected to separate or connect the part of the data bus lines 4 with the LVTTL memory modules 22 .

A possible switching of the line terminations 7 is shown in FIG. 1b. The line terminations 7 essentially have a resistor 72 , which is connected in series to a voltage potential connection 73 , and a parasitic capacitance 71 . The line terminations are necessary to suppress signal reflections on the data bus lines. Signal reflections occur, for example, if memory modules that can be operated on an SSTL-2 data bus would be connected to a data bus without line terminations, because these memory modules generally have higher data transmission frequencies and, moreover, data with a double data rate, ie rising and falling edges, of the clock used signals transmitted.

According to the SSTL-2 specification, the value of the serial resistor 72 is 25 Ω. The capacitance 71 corresponds to the parasitic capacitance of the lines and is approximately 30 pF for each data bus line 4 . The voltage potential connection 73 is connected to that of a voltage source V _TT . The voltage potential of V _TT is approximately half of the supply voltage potential provided for the memory modules 3 . In this way, the SSTL-2 data bus system can be adapted to different supply voltages.

Usually there is another one with an SSTL data bus serial resistor provided in each data bus line between a data bus control device and the SSTL-2 memory chermodules is arranged. The value of this resistance be carries approx. 20 Ω.

Furthermore, memory modules that are provided for LVTTL data buses are operated without line termination devices, so that signal reflections can occur on the data bus lines 3 .

From the above For reasons it is not possible to connect to a data bus to operate with line terminations LVTTL memory modules.  

So that the LVTTL memory modules 2 can still be used anyway, the data bus control device 5 signals via the control line 8 of the switching device 6 that the SSTL-2 memory modules 3 and the line terminations 7 are to be separated from the data bus lines 4 . Now the LVTTL memory modules 2 can be addressed in a conventional manner, since they find a simple data bus 1 without a line termination 7 .

If an SSTL-2 memory module 3 is to be addressed, the data bus control device 5 signals the switching device 6 to connect the SSTL-2 memory modules 3 and the line terminators 7 to the data bus lines 4 . The switching device 6 is preferably provided such that it has a resistance of 20 Ω in the closed state in order to correspond to the SSTL-2 specification described above. Now the data bus control device 5 can access the SSTL-2 memory modules 3 , the SSTL-2 memory modules 3 having a data bus system 1 according to the SSTL-2 specification at their connections. The LVTTL memory modules 22 , which are also connected to the data bus, do not influence the functioning of the data bus system in SSTL-2 operation, since the outputs from the LVTTL memory modules 22 connected to the data bus lines 24 are switched to high impedance as long as they are not addressed by the data bus control device be settled.

The embodiment described is particularly suitable for Use of memory modules for LVTTL data buses and SSTL-2 data buses are designed. It is with the Invention According to the data bus, however, basically possible, storage mo dule on data buses with or without line termination on direction are operable with each other on a single Da tenbus system can be operated according to the invention.

The in the preceding description, the claims and the Drawings disclosing features of the invention can both  individually as well as in any combination for the forfeiture Lichung the invention in its various embodiments be essential.  

LIST OF REFERENCE NUMBERS

1

data bus system

2

LVTTL memory module

3

SSTL-2 memory module

4

data bus

5

Datenbussteuereinrichtung

6

switching device

7

Line termination circuit

8th

control line

71

capacity

72

resistance

73

Voltage potential terminal
V _TT

voltage potential

Claims (8)

1. Data bus ( 1 ) for a first memory module ( 2 ) and for a second memory module, the data bus comprising a line termination device, characterized in that a switching device ( 6 ) for the data bus ( 1 ) is provided in order to duls (2) separate addressing of the first Speichermo the line termination device (7) of the data bus (1) and to apply the line termination device (7) to the data bus (1) in an addressing the second memory module (3). 2. Data bus ( 1 ) according to claim 1, characterized in that the switching device ( 6 ) is acted upon by a resistor, so that when the switching state is closed, a serial resistor is applied to the data bus ( 1 ). 3. Data bus ( 1 ) according to claim 2, characterized in that the switching device ( 6 ) divides the data bus ( 1 ), so that the first memory module ( 2 ) is arranged between a read end of the data bus ( 1 ) and the switching device ( 6 ) and the second memory module ( 3 ) between the switching device ( 6 ) and the line termination device ( 7 ) is arranged. 4. data bus (1) according to one of the preceding claims, by in that each line termination device (7) voltage source (73) comprises a resistor (72), a capacitance (71) and a chip, wherein the voltage source (73) connected via the resistor (72) to the data bus (1) and the capacitance (71) is connected as a load capacity. 5. Data bus ( 1 ) according to one of the preceding claims, characterized in that the first memory module ( 2 ) can be operated on an LVTTL data bus. 6. Data bus ( 1 ) according to one of the preceding claims, characterized in that the second memory module ( 3 ) can be operated on an SSTL-2 data bus. 7. Data bus ( 1 ) according to one of the preceding claims, characterized in that the data bus ( 1 ) comprises address lines, control lines and data lines. 8. Storage system with a data bus ( 1 ) according to one of the preceding claims, characterized in that
that a first memory module ( 2 ) and a second memory module ( 3 ) are provided on the data bus ( 1 ),
wherein the first memory module ( 2 ) is designed to connect it to a data bus ( 1 ) without line termination device ( 7 ), and the second memory module ( 3 ) is designed to connect it to a data bus ( 1 ) with a Connect the line termination device ( 7 ).