DE10051382A1 - Fabrication of stack for emitter windows of bi-complementary metal oxide semiconductor circuits involves depositing silicon nitride and silicon dioxide layers in semiconductor substrate at same temperature and pressure - Google Patents
Fabrication of stack for emitter windows of bi-complementary metal oxide semiconductor circuits involves depositing silicon nitride and silicon dioxide layers in semiconductor substrate at same temperature and pressureInfo
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- DE10051382A1 DE10051382A1 DE10051382A DE10051382A DE10051382A1 DE 10051382 A1 DE10051382 A1 DE 10051382A1 DE 10051382 A DE10051382 A DE 10051382A DE 10051382 A DE10051382 A DE 10051382A DE 10051382 A1 DE10051382 A1 DE 10051382A1
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- layer
- semiconductor substrate
- stack
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- silicon nitride
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000000151 deposition Methods 0.000 title abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title abstract 8
- 229910052581 Si3N4 Inorganic materials 0.000 title abstract 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title abstract 6
- 235000012239 silicon dioxide Nutrition 0.000 title abstract 4
- 239000000377 silicon dioxide Substances 0.000 title abstract 4
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract 4
- 229910021529 ammonia Inorganic materials 0.000 abstract 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 235000019270 ammonium chloride Nutrition 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006735 deficit Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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Abstract
Description
Die Erfindung bezieht sich auf ein Verfahren zum Herstellen eines Stapels aus einer Si3N4-Schicht und einer darüberlie genden SiO2-Schicht auf einem Halbleitersubstrat.The invention relates to a method for producing a stack from an Si 3 N 4 layer and an overlying SiO 2 layer on a semiconductor substrate.
Bei der Herstellung integrierter Halbleiterschaltungen ist eine häufig herzustellende Struktur ein Stapel aus einer Si3N4-Schicht und einer darüberliegenden SiO2-Schicht auf einem Halbleitersubstrat. Diese Struktur wird insbesondere bei der Bildung von Emitter-Fenstern in Basiszonen von für hohe Frequenzen geeigneten BiCMOS-Schaltungen benötigt. Die Basiszone des Halbleitersubstrats, innerhalb der das Emit ter-Fenster gebildet werden soll, ist eine mit Bor dotierte Zone, deren Profil (Spitzenkonzentration, Verteilungsbreite) stark durch Verfahrensschritte beeinflußt wird, die sich an die Bildung der Basiszone anschließen. Insbesondere wirken sich hohe Temperaturen, die über einen längeren Zeitraum angewendet werden, ungünstig auf das Profil mit der Folge aus, daß das Hochfrequenzverhalten und die Leistungsfähig keit der herzustellenden Schaltung verschlechtert werden. In the production of integrated semiconductor circuits, a structure that is frequently to be produced is a stack of an Si 3 N 4 layer and an overlying SiO 2 layer on a semiconductor substrate. This structure is particularly required for the formation of emitter windows in base zones of BiCMOS circuits suitable for high frequencies. The base zone of the semiconductor substrate, within which the emitter window is to be formed, is a zone doped with boron, the profile (peak concentration, distribution width) of which is strongly influenced by process steps which follow the formation of the base zone. In particular, high temperatures that are used over a longer period of time adversely affect the profile, with the result that the high-frequency behavior and the performance of the circuit to be manufactured are deteriorated.
Bei dem derzeit üblichen Verfahren zur Herstellung des Schichtenstapels werden zwei Prozeßschritte angewendet, wobei im ersten Schritt das Halbleitersubstrat in einem Reaktor in einem bei niedrigem Druck durchgeführten chemi schen Dampfabscheidungsprozeß einer Atmosphäre aus NH3 und Dichlorsilan (DCS) bei einer Temperatur von 800°C ausgesetzt wird. Bei diesem Schritt scheidet sich auf dem Halbleiter substrat die gewünschte Si3N4-Schicht ab. Anschließend wird das Halbleitersubstrat in einen zweiten Reaktor gebracht, in dem ebenfalls bei niedrigem Druck und durch chemisches Dampfabscheiden in einer Atmosphäre aus Sauerstoff und Tetraethoxysilan (TEOS) bei etwa 700°C auf der Si3N4-Schicht die gewünschte SiO2-Schicht abgeschieden wird. Die Dauer der beiden, in zwei Reaktoren durchgeführten Verfahrensschritte beträgt mindestens 8,5 Stunden, wobei sich das Halbleiter substrat stets über einer Temperatur von 650°C befindet, bei der die unerwünschte Beeinträchtigung des Bor-Profils in der Basiszone eintritt.In the currently conventional method for producing the layer stack, two process steps are used, the first step being to expose the semiconductor substrate in a reactor in a chemical vapor deposition process carried out at low pressure to an atmosphere of NH 3 and dichlorosilane (DCS) at a temperature of 800 ° C. becomes. In this step, the desired Si 3 N 4 layer is deposited on the semiconductor substrate. The semiconductor substrate is then brought into a second reactor in which the desired SiO 2 layer is also deposited on the Si 3 N 4 layer at low pressure and by chemical vapor deposition in an atmosphere of oxygen and tetraethoxysilane (TEOS) at about 700 ° C. becomes. The duration of the two process steps carried out in two reactors is at least 8.5 hours, the semiconductor substrate always being above a temperature of 650 ° C. at which the undesired impairment of the boron profile occurs in the base zone.
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren der eingangs geschilderten Art zu schaffen, bei dem der ge wünschte Schichtstapel in wesentlich kürzerer Zeit und bei niedrigeren Temperaturen erhalten wird.The invention has for its object a method of to create the type described in which the ge wanted layer stack in a much shorter time and at lower temperatures is obtained.
Zur Lösung dieser Aufgabe enthält das erfindungsgemäße Ver
fahren folgende Schritte:
To achieve this object, the method according to the invention includes the following steps:
- a) die Si3N4-Schicht wird in einem Reaktor in einer NH3 und Bis(tert.-butylamino)silan enthaltenden Atmosphäre bei einer Temperatur von 600 bis 650°C und einem Druck von 40 bis 53 Pa auf dem Halbleitersubstrat abgeschieden;a) the Si 3 N 4 layer is deposited on the semiconductor substrate in a reactor in an atmosphere containing NH 3 and bis (tert-butylamino) silane at a temperature of 600 to 650 ° C. and a pressure of 40 to 53 Pa;
- b) die SiO2-Schicht wird im gleichen Reaktor in einer O2 und Bis(tert.-butylamino)silan enthaltenden Atmosphäre bei einer Temperatur von 600 bis 650°C und einem Druck von 40 bis 53 Pa auf der Si3N4-Schicht abgeschieden.b) the SiO 2 layer is in the same reactor in an atmosphere containing O 2 and bis (tert-butylamino) silane at a temperature of 600 to 650 ° C. and a pressure of 40 to 53 Pa on the Si 3 N 4 - Layer deposited.
Bei Anwendung des erfindungsgemäßen Verfahrens wird der gewünschte Stapel aus einer Si3N4-Schicht und einer darüber liegenden SiO2-Schicht auf einem Halbleitersubstrat in einem einzigen Prozeß im selben Reaktor durchgeführt, wobei die Verweilzeit kurzgehalten werden kann und mit Temperaturen gearbeitet wird, die nicht zu einer wesentlichen Beeinträch tigung des Dotierungsprofils der unter dem Schichtenstapel im Halbleitersubstrat liegenden Zonen führt. Dadurch können integrierte BiCMOS-Schaltungen mit besserem Hochfrequenzver halten hergestellt werden.When using the method according to the invention, the desired stack of an Si 3 N 4 layer and an overlying SiO 2 layer is carried out on a semiconductor substrate in a single process in the same reactor, the residence time being kept short and operating at temperatures which does not lead to a substantial impairment of the doping profile of the zones lying under the layer stack in the semiconductor substrate. Integrated BiCMOS circuits with better high-frequency behavior can thereby be produced.
Für das anschließend zu beschreibende Ausführungsbeispiel des erfindungsgemäßen Verfahrens wird angenommen, daß in dem Halbleitersubstrat eine für Hochfrequenzanwendungen geeigne te BiCMOS-Schaltung hergestellt werden soll und daß in einer durch Dotieren mit Bor hergestellten Basis-Zone das Emitter- Fenster eines bipolaren Transistors gebildet werden soll. Bei der Bildung dieses Emitter-Fensters ist es erforderlich, auf der freiliegenden Basis-Zone zunächst eine Si3N4-Schicht mit einer Dicke von etwa 35 nm abzuscheiden und darauf eine SiO2-Schicht mit einer Dicke von 115 nm zu bilden.For the embodiment of the method according to the invention to be described subsequently, it is assumed that a BiCMOS circuit suitable for high-frequency applications is to be produced in the semiconductor substrate and that the emitter window of a bipolar transistor is to be formed in a base zone produced by doping with boron. When forming this emitter window, it is necessary to first deposit an Si 3 N 4 layer with a thickness of approximately 35 nm on the exposed base zone and to form an SiO 2 layer with a thickness of 115 nm thereon.
Zur Herstellung des Schichtenstapels wird das Halbleitersub strat in einen üblicherweise als LPCVD-Reaktor bezeichneten Reaktor eingebracht, also einen Reaktor, in dem bei niedri gem Druck ein chemisches Dampfabscheidungsverfahren durch geführt werden kann. In diesem Reaktor wird ein niedriger Druck im Bereich von 40 bis 53 Pa erzeugt, und es wird eine Atmosphäre erzeugt, die NH3 und Bis(tert.-butylamino)silan in einem Mischungsverhältnis von 3 : 1 oder 2 : 1 enthält. Die Arbeitstemperatur wird im Reaktor auf etwa 600°C gehalten. Dabei erfolgt eine Abscheidung der Si3N4-Schicht mit einer Geschwindigkeit, die nicht unter 2 nm/min liegt. Nach Erreichen der Schichtdicke von 35 nm erfolgt ein kurzer Spülzyklus von etwa 10 Minuten, um aus dem Reaktor die Atmosphäre zu entfernen, die zur Abscheidung der ersten Schicht geführt hat. Nach diesem Spülzyklus wird in den gleichen Reaktor unter den gleichen Druck- und Temperaturbedingungen eine Atmosphäre aus O2 und Bis(tert.-butyl amino)silan erzeugt, die zur Abscheidung einer SiO2-Schicht auf der Si3N4-Schicht führt. Die Abscheidungsgeschwindigkeit liegt dabei nicht unter 6 bis 7 nm/min, so daß die gewünsch te Schichtdicke von 115 nm nach ca. 20 Minuten erreicht ist. Nach einem erneuten Spülvorgang kann das Halbleitersubstrat weiteren Prozeßschritten zugeführt werden.To produce the layer stack, the semiconductor substrate is introduced into a reactor usually referred to as an LPCVD reactor, that is to say a reactor in which a chemical vapor deposition process can be carried out at low pressure. A low pressure in the range of 40 to 53 Pa is generated in this reactor and an atmosphere is generated which contains NH 3 and bis (tert-butylamino) silane in a mixing ratio of 3: 1 or 2: 1. The working temperature is kept at about 600 ° C in the reactor. The Si 3 N 4 layer is deposited at a rate not less than 2 nm / min. After the layer thickness of 35 nm has been reached, there is a short rinsing cycle of about 10 minutes in order to remove the atmosphere from the reactor which led to the deposition of the first layer. After this rinsing cycle, an atmosphere of O 2 and bis (tert-butyl amino) silane is generated in the same reactor under the same pressure and temperature conditions, which leads to the deposition of an SiO 2 layer on the Si 3 N 4 layer. The deposition rate is not below 6 to 7 nm / min, so that the desired layer thickness of 115 nm is reached after about 20 minutes. After a new rinsing process, the semiconductor substrate can be fed to further process steps.
In der Praxis hat sich gezeigt, daß die gesamte Prozeßzeit zur Herstellung des Schichtenstapels etwa 4,5 Stunden be trägt, wobei in einem einzigen Schritt 150 Halbleitersub strate bearbeitet werden können. Der Gesamtdurchsatz kann also mit ca. 33 Halbleitersubstraten pro Stunde angegeben werden.In practice it has been shown that the entire process time about 4.5 hours to produce the layer stack carries, in a single step 150 semiconductor sub strate can be edited. The total throughput can So specified with about 33 semiconductor substrates per hour become.
Das beschriebene Verfahren führt somit nicht nur zu Halb leiterschaltungen mit verbesserten Eigenschaften, sondern es ermöglicht auch einen beträchtlich gesteigerten Durchsatz an Halbleitersubstraten. Ein weiterer wesentlicher Vorteil der Anwendung des beschriebenen Verfahrens besteht darin, daß es nicht mehr notwendig ist, das bisher zur Herstellung der Si3N4-Schicht verwendete Dichlorsilan einzusetzen, so daß im Reaktor kein Ammoniumchlorid mehr entsteht, das in zeit aufwendigen und regelmäßig durchzuführenden Wartungsvorgän gen aus dem betroffenen Reaktor entfernt werden mußte, um eine Verunreinigung der Halbleitersubstrate durch Ammonium chloridpartikel zu vermeiden.The described method thus not only leads to semiconductor circuits with improved properties, but also enables a considerably increased throughput of semiconductor substrates. Another significant advantage of using the method described is that it is no longer necessary to use the dichlorosilane previously used for the production of the Si 3 N 4 layer, so that ammonium chloride is no longer formed in the reactor, which is time-consuming and has to be carried out regularly Maintenance procedures had to be removed from the reactor concerned in order to avoid contamination of the semiconductor substrates by ammonium chloride particles.
Claims (3)
- a) die Si3N4-Schicht wird in einem Reaktor in einer NH3 und Bis(tert.-butylamino)silan enthaltenden Atmosphäre bei einer Temperatur von 600 bis 650°C und einem Druck von 40 bis 53 Pa auf dem Halbleitersubstrat abgeschieden;
- b) die SiO2-Schicht wird im gleichen Reaktor in einer O2 und Bis(tert.-butylamino)silan enthaltenden Atmosphäre bei einer Temperatur von 600 bis 650°C und einem Druck von 40 bis 53 Pa auf der Si3N4-Schicht abgeschieden.
- a) the Si 3 N 4 layer is deposited on the semiconductor substrate in a reactor in an atmosphere containing NH 3 and bis (tert-butylamino) silane at a temperature of 600 to 650 ° C. and a pressure of 40 to 53 Pa;
- b) the SiO 2 layer is in the same reactor in an atmosphere containing O 2 and bis (tert-butylamino) silane at a temperature of 600 to 650 ° C. and a pressure of 40 to 53 Pa on the Si 3 N 4 - Layer deposited.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10051382A DE10051382A1 (en) | 2000-10-17 | 2000-10-17 | Fabrication of stack for emitter windows of bi-complementary metal oxide semiconductor circuits involves depositing silicon nitride and silicon dioxide layers in semiconductor substrate at same temperature and pressure |
| EP01122519A EP1199743A3 (en) | 2000-10-17 | 2001-09-21 | Method of fabricating a stack consisting of a layer of Si3N4 topped by a layer of SiO2 on a semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10051382A DE10051382A1 (en) | 2000-10-17 | 2000-10-17 | Fabrication of stack for emitter windows of bi-complementary metal oxide semiconductor circuits involves depositing silicon nitride and silicon dioxide layers in semiconductor substrate at same temperature and pressure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE10051382A1 true DE10051382A1 (en) | 2002-05-02 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10051382A Ceased DE10051382A1 (en) | 2000-10-17 | 2000-10-17 | Fabrication of stack for emitter windows of bi-complementary metal oxide semiconductor circuits involves depositing silicon nitride and silicon dioxide layers in semiconductor substrate at same temperature and pressure |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE10051382A1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874368A (en) * | 1997-10-02 | 1999-02-23 | Air Products And Chemicals, Inc. | Silicon nitride from bis(tertiarybutylamino)silane |
| US5976991A (en) * | 1998-06-11 | 1999-11-02 | Air Products And Chemicals, Inc. | Deposition of silicon dioxide and silicon oxynitride using bis(tertiarybutylamino) silane |
-
2000
- 2000-10-17 DE DE10051382A patent/DE10051382A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874368A (en) * | 1997-10-02 | 1999-02-23 | Air Products And Chemicals, Inc. | Silicon nitride from bis(tertiarybutylamino)silane |
| US5976991A (en) * | 1998-06-11 | 1999-11-02 | Air Products And Chemicals, Inc. | Deposition of silicon dioxide and silicon oxynitride using bis(tertiarybutylamino) silane |
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