DE10012112C2 - Bridge field effect transistor and method for producing a bridge field effect transistor - Google Patents

Description

The invention relates to a fin field effect transistor and a method for producing a bridge field effect transi stors.

Such a fin field effect transistor and a method for Manufacture of such a bridge field effect transistor are off [1] known.

The web field effect transistor 200 from [1] has a silicon substrate 201 and an oxide layer made of silicon oxide SiO ₂ 202 thereon (see FIG. 2).

A web 203 made of silicon is provided on part of the oxide layer 202 . A gate 204 of the resulting land field effect transistor 200 is disposed over part of land 203 and along the entire height of the land part.

In the fin field effect transistor 200 known from [1], the channel region (not shown) can be inverted by charge carriers with the aid of the gate 204 extending along the side walls 205 of the fin 203 . The web 203 forms a source region 206 and a drain region 207 .

In the case of the fin field transistor 200 known from [1], however, there is no self-aligned spacer technology for the LDD implantation or HDD implantation around the fin 203 , which is also referred to as mesa, in the source region 206 and in the drain Region 207 with high doping atoms.

This is due in particular to the fact that oxide spacers 208 only form along the side walls 205 of the web 203 .

However, the existing oxide spacers 208 prevent the mesa 203 from being implanted via the side walls 205 , and the channel region is implanted with doping atoms in addition to the source region 206 and the drain region 207 . The channel area is not protected by an oxide spacer. This leads to a diffusion at a lower implantation of the fin field-transistor 200 with doping atoms.

Furthermore, it is often desirable to keep the source region 206 and the drain region 207 of the web 203 freely accessible so that the drain region 207 of the web 203 can be doped easily and precisely.

However, this is not possible with the fin field-effect transistor 200 according to the [1] and the corresponding manufacturing process described in [1].

Under a bridge field effect transistor is in the context of Er to generally understand a field effect transistor, de source and drain are vertical, also exposed, or over an insulator layer, for example an oxide layer, extends and has a gate that is partially above the vertically extending area, especially over the Ka nalbereich the field effect transistor, and along the sides walls of the resulting vertical structure. The Channel area extends along the vertical structure from source to drain.

The invention is therefore based on the problem of Specify field effect transistor in which an underdiffusion in the channel area below the gate as part of an implan tion of the gate with doping atoms is avoided.

Furthermore, the invention is based on the problem of methods to produce such a bridge field effect transistor to admit.  

The problems are compounded by the fin field effect transistor as well through the methods of making the web field effect oil sistors with the features according to the independent patent sayings solved.

A bridge field effect transistor has a substrate, a bridge over the substrate and a gate and a spacer over one Part of the jetty.

In a method of making a land field effect oil sistor a web is formed on a substrate. About that A gate layer becomes the substrate and over part of the web educated. Then an iso is over the gate layer tion layer formed. Below the insulation layer the gate layer partially removed and partially ent distant area, a spacer is formed.

In another method of making a web field effect transistor, a web is formed over a substrate det. Above the substrate, along and over part of the web a gate layer is formed. Over the gate layer is ei ne insulation layer formed. Over the area that is not is covered by the gate layer, one is to be etched away Layer formed to a height above the footbridge and lies below the insulation layer. Over part a spacer is formed in the layer to be etched away and the The layer to be etched away is essentially down to the part removed, which is directly below the spacer.

The invention makes a web field effect oil for the first time sistor using a self-aligned process specified spacer. In the web field according to the invention The effect transistor is the spacer over part of the bridge formed so that underdiffusion in a source, Drain implantation with doping atoms is avoided.  

Also remain in the web field effect oil according to the invention sistor the source region and the drain region of the web freely accessible, so that an exact and simple doping of the source region and the drain region of the web possible becomes.

Preferred developments of the invention result from the dependent claims.

The configurations described below relate both on the fin field effect transistor and on the Method of manufacturing the fin field effect transistor.

The gate and / or the spacer can essentially be extend along the entire height of the part of the web.

The substrate can include silicon and, alternatively, it can also a further layer on the substrate, for example be made of silicon oxide, generally an oxide, on which the bridge and the gate are arranged.

The web can have silicon.

According to one embodiment of the invention, the gate has poly silicon on. Furthermore, the gate can also be a stack formed by polysilicon and tungsten silicide.

The spacer can have silicon oxide and / or silicon nitride sen.

According to a further embodiment of the invention, the Spacer a first spacer part with silicon oxide and one second spacer part with silicon nitride. The second spacer part is arranged over the first spacer part.

According to a further embodiment of the invention, between an etch stop layer on the substrate and the land and the gate  intended. The etch stop layer preferably has silicon nitride.

This configuration further simplifies the Manufacturing process of the fin field effect transistor he sufficient because there is no active monitoring when etching the gate forming polysilicon layer on the boundary with the substrate or the oxide is required. The etching process is done according to this configuration automatically ge on the etch stop layer stops.

Furthermore, the height of the spacer can be with respect to the substrate be substantially equal to the height of the gate.

This configuration makes underdiffusion in the Implantation of the source and drain areas of the Bridge field effect transistor virtually completely avoided.

At least part of the elements of the bridge field effect transi stors can be formed by deposition.

According to this further development, conventional semiconductor Process technology can be used, making a simple and Cost-effective implementation of the manufacturing process enables light is.

The layer to be removed can be removed by etching the, for example by means of dry etching or wet etching.

Embodiments of the invention are shown in the figures represents and are explained in more detail below.

Show it

. Figure 1 shows a fin field effect transistor according to a first embodiment of the invention;

Fig. 2 is a fin field effect transistor according to the prior art;

FIG. 3 shows a plan view of the fin field effect transistor from FIG. 1 with a section line A-A ';

FIGS. 4A to 4E are sectional views of the fin field-effect transistor of Fig. 1 taken along line AA 'in Fig. 3, in which the individual Verfahrensschrit te of the manufacturing process of the fin field-effect transistor of Fig. 1 according to a first exporting approximately example of the invention shown are;

Fig. 5 is a fin field effect transistor according to a second embodiment of the invention;

FIG. 6 shows a top view of the fin field effect transistor from FIG. 5 with a section line B-B ';

FIGS. 7A to 7E are sectional views of the fin field-effect transistor of FIG. 5 taken along section line BB 'of FIG. 6, in which the individual Verfahrensschrit te of the manufacturing process of the fin field-effect transistor of FIG. 6 according to a second exporting approximately example of the invention shown are;

Fig. 8 shows a fin field effect transistor according to a third embodiment of the invention.

Fig. 1 shows a fin field effect transistor 100 according to a first embodiment of the invention.

The web field effect transistor 100 has a substrate 101 on which an oxide layer 102 made of silicon oxide SiO _{2 with} a layer thickness of approximately 200 is deposited (cf. FIG. 1).

A web 103 made of silicon is formed on the oxide layer 102 . To produce the web 103 , a method known from SOI technology (SOI: Silicon on Isolator) is used in accordance with the exemplary embodiment. A polysilicon layer 106 forming a gate 104 and spacers 107 , 108 made of silicon oxide are arranged over a partial region of the web 103 and along the partial region in the vertical direction along the side walls 105 of the web 103 and in the corresponding, linearly continued region on the oxide layer 102 net.

Over the gate 104 and the spacers 107 , 108 , a protective layer 111 made of silicon nitride Si ₃ N _{4 is applied} to protect the gate 104 . A source region 109 and a drain region 110 are thus formed, which can be conductively coupled to one another depending on the control by means of the gate 104 via a channel region (not shown).

Furthermore, the same elements in different Drawings used the same reference numerals.

FIG. 3 shows the fin field effect transistor 100 from FIG. 1 in a top view.

In Fig. 3, a cutting line AA 'is shown along which a cut is made, the result in Fig. 4A to Fig. Sectional views of the fin field-effect transistor 100 shown 4E in FIG. 1.

Referring to Figs. 4A to Fig. 4E, the individual process steps are described for producing the fin field-effect transistor 100 according to the first game Ausführungsbei hereinafter.

The starting point is an SOI wafer, ie clearly a silicon substrate 101 , in which a silicon oxide layer 102 is located (cf. FIG. 4A).

In a first step, the threshold voltage of the bridge field effect transistor 100 is set by implantation of doping atoms, in accordance with the exemplary embodiment with boron atoms. In the case of a completely depleted transistor, this channel implantation can also be omitted as part of the method.

In a further step, photoresist is applied to the silicon layer formed in such a way that the photoresist indicates where the web 103 is to be formed.

In a further step, the silicon that is not using Is covered by a wet etching process or etched using a dry etching process.

The etching process is stopped as soon as the surface of the silicon oxide layer 102 is reached.

In a further step, the photoresist is removed from the resulting web 103 .

In a further step, gate oxide is formed along the side walls of the web 103 and above the web 103 .

In a further step, a layer of polysilicon is deposited over the silicon oxide layer 102 , along the side walls of the web 103 and over the web 103 by means of a CVD process. During the deposition of the polysilicon, the resulting polysilicon layer is doped with phosphorus or boron atoms.

In a further step, a silicon nitride layer (Si ₃ Ni ₄ ) is deposited as protective layer 111 on the polysilicon layer, which serves as gate 104 in the fin field effect transistor 100 , by means of a CVD method.

Subsequently, photoresist is applied to the silicon nitride layer 107 in such a way that the region that is later to be used as gate 104 or spacer 105 , 106 is not etched by the photoresist in further etching steps.

In a subsequent step, the silicon nitride layer 111 , which is not covered with photoresist, is etched by means of a wet etching process or a dry etching process.

Furthermore, the polysilicon layer 106 , which is not protected by the photoresist, is etched away using a dry etching method or a wet etching method.

The etching process is ended on the surface of the silicon oxide layer 102 , so that oxide is not etched.

The photoresist is then removed from the silicon nitride layer 111 (cf. FIG. 4B).

In a further step (cf. FIG. 4C), the polysilicon layer 160 below the silicon nitride layer 111 is partially etched away using wet etching or dry etching. This clearly results in a T-shaped structure 400 .

In a further step (cf. FIG. 4D), a silicon oxide layer with a thickness of approximately 500 nm is deposited by means of a CVD process.

The silicon oxide layer is then removed again by means of a chemical-mechanical polishing process until the silicon nitride layer 111 is reached. If the silicon nitride layer 111 is reached, the CMP process is stopped.

Subsequently, silicon oxide is etched up to the surface of the silicon oxide layer 102 using a dry etching method. Dry etching is selective to silicon nitride.

The desired spacers 105 , 106 of the fin field-effect transistor 100 shown in FIG. 1 thus form below the silicon nitride layer, but above the fin 103 and on the side walls of the fin and on the silicon oxide layer 102 (see FIG. 4D).

In a further step (cf. FIG. 4E), stray oxide is deposited and the source region and the drain region of the web 104 are implanted n ⁺ via the side walls of the web 103 , which are now more exposed.

An implantation of atoms in the channel area is now also not possible since the entire gate 104 is completely protected by the spacers 105 , 106 .

In final standard semiconductor process steps can be used for the fin field-effect transistor 100 contacts for the gate, source, drain, are etched, and it is a silicidation of the fin field-effect transistor 100 is possible.

Fig. 5 shows a fin field effect transistor 500 according to a second embodiment of the invention.

In the case of the fin field-effect transistor 500 , as will be explained below, the polysilicon layer 106 no longer needs to be under-etched to produce it.

The fin field effect transistor 500 according to the second exemplary embodiment is therefore particularly suitable for standard semiconductor processes.

The fin field effect transistor 500 according to the second exporting approximately example differs from the fin field effect sistor 100 according to the first embodiment in wesentli chen characterized in that the silicon nitride layer 107 chen in wesentli only over the polysilicon layer of the gate 104 is located, and that via the spacers 107, 108 two silicon nitride spacers 501 , 502 are arranged.

Fig. 6 shows the fin field effect transistor 500 of Fig. 5 the top view with the section line B-B ', along which the sectional views of Fig. 7A to Fig. 7E of the fin field effect transistor 500 result.

FIG. 7A shows the fin field effect transistor 500 according to the second exemplary embodiment in a sectional view along the section line BB ′ from FIG. 6 with the substrate 101 of the silicon oxide layer 102 and the fin 103 and a silicon nitride layer 701 on the fin 103 .

Optionally, in a further step, a charge carrier implantation for setting the threshold voltage of the bridge field effect transistor 500 can be carried out.

In a further step, gate oxide is formed over the web and the silicon nitride layer 701 .

In a further step (cf. FIG. 7B), a polysilicon layer is deposited using a suitable CVD method, the polysilicon layer 106 being doped with phosphorus atoms or boron atoms during the deposition. The polysilicon layer 106 has a thickness of approximately 400 nm.

In this context, it should be noted that the thickness of the polysilicon layer 106 is not a critical criterion in the context of the manufacturing process.

After the polysilicon has been removed by means of a chemical-mechanical polishing process to such an extent that the height of a structure which ultimately forms the gate 104 of the fin field effect transistor 100 results, a silicon nitride layer 111 is provided as a protective layer on the polysilicon layer 106 by means of a CVD Process separated (see FIG. 7B).

Subsequently, photoresist is applied to the area which is provided for the gate 104 of the fin field effect transistor 500 , and the part of the silicon nitride layer 702 which is not covered with the photoresist is etched away by means of a dry etching method or a wet etching method.

The areas of the polysilicon layer 106 that are not protected by the photoresist are also etched away by means of a dry etching process or a wet etching process. This etch is selective to silicon nitride.

The etching process is stopped on the surface of the silicon nitride layer 701 .

The photoresist is then removed from the silicon nitride layer 111 again (cf. FIG. 7B).

In a further step, a silicon oxide layer 702 with a thickness of approximately 500 nm is deposited by means of a suitable CVD method over the web 103 , on the silicon nitride layer 701 of the web 103 and over the remaining surface areas of the web field effect transistor 500 that have been exposed until then.

The silicon oxide is removed by means of a chemical-mechanical polishing process, the CMP process being stopped at the upper limit of the silicon nitride layer 111 which is arranged on the polysilicon layer 106 .

The silicon oxide layer 702 is then anisotropically etched up to the lower edge of the silicon nitride layer 111 located on the polysilicon layer 106 (cf. FIG. 7C).

Then, a silicon nitride layer according to the out example of the thickness of 50 nm, it should be noted that the thickness of the silicon nitride layer can be specified very variably is deposited by means of a suitable CVD process.

In a further step, the silicon nitride spacers 501 , 502 (cf. FIG. 7C) are etched using a dry etching process.

In a final step, the silicon oxide film 702 is etched to the silicon nitride layer 701 by means of a Trockenätzverfah Rens, whereby silicon oxide spacers 107 are formed, 108 (see. Fig. 7D).

In a further step (cf. FIG. 7E), stray oxide is deposited and the source region and the drain region of the web 104 are implanted n ⁺ via the side walls of the web 103 , which are now more exposed.

The result is the fin field effect transistor 500 , in which the contacts to the source, gate, drain can be etched in further process steps or which can be subjected to a conventional semiconductor standard process for further treatment. The silicidation of the bridge field effect transistor 500 according to the second embodiment is also possible.

Fig. 8 shows a fin field effect transistor 800 according to a third embodiment.

The fin field effect transistor 800 according to the third exemplary embodiment essentially corresponds to the fin field effect transistor 100 according to the first exemplary embodiment, with the difference that a silicon nitride layer 801 is provided as an etching stop layer on the silicon oxide layer 102 . A further silicon oxide layer 802 is further provided on the silicon nitride layer 801 .

Due to the etch stop layer 801 , no “temporary etch” of the last etching process step is required up to the surface of the silicon oxide layer 102 , since each etching process is automatically stopped at the etch stop layer 801 .

Alternatively, representing over the silicon oxide layer 102 for an etching stopper layer 801, such as, for example, the silicon nitride layer 702 according to the second execution, PolySi lizium be used.

The manufacturing process for the fin field effect transistor 800 according to the third exemplary embodiment likewise essentially corresponds to the manufacturing process for the fin field effect transistor 100 according to the first exemplary embodiment, although the further silicon oxide layer 802 is deposited on the silicon nitride layer 801 by means of a CVD method. After appropriate preparation of the polysilicon layer with photoresist, the further silicon oxide layer 802 is anisotropically etched using a dry etching process or a wet etching process. The etching is ended on the silicon nitride layer 801 .

It should be pointed out that, according to another exemplary embodiment, provision is made for the fin field effect transistor 500 according to the second exemplary embodiment to be provided without the etching stop layer 701 , in which case the respective etching processes have to be stopped “manually” on the surface of the silicon oxide layer 102 .

It should also be noted that instead of the CVD process sputtering or vapor deposition processes are also used that can, each in combination with each other.  

The following publication is cited in this document:
[1] D. Hisamoto et al. A Fully Depleted Lean-Channel Transi stor (DELTA) - A novel vertical ultrathin SOI MOSFET, IEEE Electron Device Letters, Volume 11 , No. 1, pp. 36-38, 1990

Claims (21)

1. Bridge field effect transistor, with
a substrate,
a web above the substrate, and
a gate and a spacer over part of the bridge. 2. bridge field effect transistor according to claim 1, in which the gate and / or the spacer essentially extends along the entire height of the part of the web. 3. bridge field effect transistor according to claim 1 or 2, in which the substrate has silicon oxide. 4. bridge field effect transistor according to one of claims 1 to 3, in which the web has silicon. 5. bridge field effect transistor according to one of claims 1 to 4, in which the gate has polysilicon. 6. bridge field effect transistor according to one of claims 1 until 5, in which the spacer is based on silicon oxide and / or silicon nitride has. 7. bridge field effect transistor according to one of claims 1 to 5,
in which the spacer has a first spacer part with silicon oxide and a second spacer part with silicon nitride,
wherein the second spacer part is arranged above the first spacer part. 8. bridge field effect transistor according to one of claims 1 to 7,  where one between the substrate and the land and the gate Etching stop layer is provided. 9. bridge field effect transistor according to claim 8, in which the etch stop layer has silicon nitride. 10. bridge field effect transistor according to one of claims 1 till 9, in which the height of the spacer with respect to the substrate in the we the height of the gate is substantially the same. 11. Method for producing a bridge field effect transistor,
in which a web is formed on a substrate,
in which a gate layer is formed over the substrate and over part of the web,
in which an insulation layer is formed over the gate layer,
in which the gate layer is partially removed below the insulation layer, and
in which a spacer is formed below the insulation layer. 12. Method for producing a fin field effect transistor,
in which a web is formed on a substrate,
in which a gate layer is formed over the substrate and over part of the web,
in which an insulation layer is formed over the gate layer,
in which a layer to be removed is formed above the region which is not covered by the gate layer, to a height which lies above the web and below the insulation layer,
in which a spacer is formed over part of the layer to be removed,
in which the layer to be removed is essentially removed except for the part which lies directly below the spacer. 13. The method according to claim 11 or 12, in which at least some of the elements of the web Field effect transistors are formed by means of deposition. 14. The method according to any one of claims 11 to 13, in which silicon oxide is used for the substrate. 15. The method according to any one of claims 11 to 14, in which silicon is used for the web. 16. The method according to any one of claims 11 to 15, which uses polysilicon for the gate. 17. The method according to any one of claims 11 to 16, in the case of the spacer silicon oxide and / or silicon nitride will be used. 18. The method according to any one of claims 11 to 17, wherein the spacer is formed in the following way:
a first spacer part with silicon oxide is formed,
a second spacer part with silicon nitride is formed over the first spacer part. 19. The method according to any one of claims 11 to 18, where one between the substrate and the land and the gate Etching stop layer is formed. 20. The method according to claim 19, in which silicon nitride is used for the etching stop layer becomes. 21. The method according to any one of claims 11 to 20,  in which the spacer is formed such that its height be the height of the substrate is substantially the same Gates.