CS269961B2 - Circuit for signals processing - Google Patents

Abstract

A signal processing circuit is provided which comprises: a plurality of cascaded delaying means 10, 12, 14, 16, 18 successively delaying input signals; a means 100 for detecting magnitude changes of the input signals; and selective coupling means 20, 22 responsive to the detecting means, for selectively coupling the inputs of certain of the delaying means to the inputs of selected others of the delaying means to enhance the transition times of input signals, thereby providing sharper edges at colour boundaries in a video signal. <IMAGE>

Description

(57) The signal processing circuitry comprises a plurality of cascaded delay stages subsequently delaying the input signals, transition detectors as means for detecting the magnitude of the input signals, and selective interconnecting means responsive to the detection means. These circuits highlight the transition times of the input signals.

The invention relates to a signal processing circuit comprising an input for receiving input signals and an output on which output signals are generated in response to input signals, several delay stages connected in cascade between the input and output for sequentially delaying the input signals.

When signals are processed by systems of limited bandwidth or viewing speed, the rise and fall times between signal levels are correspondingly reduced, i.e., the lower bandwidth produces more gradual transitions, for example in a television system the bandwidth of the chrominance signals is limited by the transmission system standard. the NTIC system has a chrominance X signal of 1.5 MHz and a chrominance Q signal has a bandwidth of 0.5 MHz · often the TV's circuitry processes both chrominance 1 signals and chrominance Q signals at 0.5 MHz ·

For most image conditions, the signal processing described above is satisfactory, even if it is desirable that the rise and fall times be improved. However, limited chrominance rise times tend to blur object edges and reduce color fidelity. These undesirable picture effects are particularly evident when an object has a well-defined edge that a high-bandwidth 4.2 MHz brightness signal can reproduce, but which cannot be reproduced by chrominance signals with a lower bandwidth, and further when the object color is substantially different from the background color.

Thus, there is a need for circuitry that highlights, for example, decreases the rise and fall times of the signal when certain transitions occur, and at the same time detectors of such transitions are needed. It should be noted. That conventional centering circuits that emphasize higher frequency components relative to lower frequency components have a limited effect where higher frequency components are severely attenuated due to reduced signal bandwidth ·

FIG. 1 is a block diagram of one embodiment of the circuit, FIGS. 2a and 2b are diagrams showing signals in the circuit of FIG. 1, and FIGS. circuit according to FIG. 1

The invention achieves gradual delay of input signals, detection of transition of input signals, and interconnection of delay means in response to detection of transition.

Although the signals in the following description are referred to as digital signals, it is to be understood that the invention operates satisfactorily with many different types of signals, for example with both analogue and digital type sampling data signals and analogue signals. In the figures, the broad arrows show signal paths for multi-bit parallel digital signals, while the line arrows show signal paths for single-bit or serial digital signals or for analog signals.

Giant. 1 illustrates a signal transition enhancement circuit including a transition detector. The receiver is configured to process digital color signals in a television having digital signal processing circuits. The receiver generates digital color signals CS which are further processed by a device using the present invention to produce enhanced digital color signals CS?

In the following description, the operation of the delay stages l0, 12, 14, 16 and 18 and the multiplexers 20 and 22 are first described to effect a rise time. The operation of the first loo transition detector is described later.

Under the initial assumption that the muitiplexers 2o and 22 connect signals at locations 13 and C to their respective outputs, the CS input color signals are subsequently delayed by cascaded delay stages lo, 12, 14, 16 and 10 so that the output color signals are simply input signals. color-coded CS signals are delayed. Each of the delay stages lo, 12, 14, 16 and 18 is, for example, an 8-bit parallel storage responsive to the clock signal f _{and c} . The clock signal f has a repetition rate related to the subcarrier frequency, i.e. about 3.58 MHz in the NTSC television system. Thus, the output chrominance signal CS * is delayed in time2 compared to the input chrominance signal CS by β cylae of the clock signal t. —— sc

When transitions of the input chrominance signal CS * occur that meet certain predetermined criteria for magnitude and rise time, the first transition detector 100 generates a control signal M_C and feeds it to multiplexers 2o and 22 so that multiplexers 2o and 22 selectively connect inputs to one delay delay. The first multiplexer 20 connects the input of the first delay stage 12 to the input of the second delay stage 14 and disconnects the output of the first delay stage 12 similarly. The second multiplexer 22 connects the input of the fourth delay stage 18 to the input of the third delay stage 16. and disconnects the output of the second delay stage 14 *

For example, if the timing sequence of the samples A * V, C * D * E * F of the color input signal CS shown in Figure * 2a is considered, forming a transition from a lower size to a higher size, i.e. a positive direction transition. That in the case of systems with sampled data either analog or digital, the signal retains the value * it has for the whole period * A straight line between samples is created for the sake of clarity only in this type of system * time interval represented by fig. the time sequence of the samples of the color CS signal was clocked through the delay stages lo * 12 * 14 * 16 and 18,

Thus, the samples * indicated by the sample denoting the letters in Fig. 2a * correspond to the values of the samples on the signal paths on the corresponding * signal path indicating the letters in the fig. 1 * that is the color input signal CS. indicated by Sample A five clock cycles t before * Solid line 5o connects Sample A * F * to illustrate the rise time represented by Sample A to X ·

If it is further considered that at this time this sample sequence is of magnitude such that the first loo transition detector generates a control signal MC activating the multiplexers 2o and 22 * as described above, the first multiplexer 2o replaces the sample value hodnotou by the value of sample D at the input of the second Delay stage 14 and the second multiplexer 22 replace the sample value V with the value of sample C at the input of the third delay stage 16. These substitutions are indicated by arrows 54 and 52 respectively and the sample substitution values from samples E and В are shown. Fig. 2a, In the emerging clock signal cycle i _{and c} Are samples B, ^{c D} Jh F respectively blocked in delay stages 18 * 16 * 14, 12 and lo and the first transition detector loo removes the control signal MC * because transition detection criteria already not retained * In response to other frequency cycles í _sc · the color signal CS will be output * include a modified sequence of samples A * J * C * D * E * _F * to That is the size A * J3, В * E, E, F in this sequence * that have highlighted gradients * to That is gradients with reduced rise time * Thought Line 56 joins the samples in a modified sequence so as to illustrate the highlighted rise time of the transition thus represented, _r In another example, the sequence of the color input signal CS shown in Fig. 2b may be considered as generating a transition from a higher magnitude to a lower magnitude. In accordance with the above-described operation with respect to FIG. 2a, the multiplexers 2o * and 22 respectively substitute 6o * or 64 in response to the control signal MC so that a modified sequence A * _B * J3 * IS * E is formed. F of the output chrominance signal CS1 representing the highlighted deceleration time represented by the imaginary line 66,

The first transition detector loo and predetermined criteria * according to which the appearance of the transition * is detected will be described below. The signal shape transition is a change in instantaneous amplitude from one amplitude level to the other amplitude level and can be described by the difference between the levels and the time required to change the level. For sampled data * exemplified by Digital signals *, the transition can be described by sample size or sample groups and the number of samples * in which the size changes.

The first loo transition detector detects a transition * when the signal sizes of the sampled data are relatively close in size for each of the two groups of successive samples, and when the size difference between successive samples is substantial. Especially in a sequence of Six consecutive samples Jo transition detected * when the first and second samples, ie the first group after each of the consecutive samples »Are relatively close in size to one another, the fifth and sixth sample, ie the second group after the two consecutive samples · They are relatively close in size to one another and when the sizes of the second and fifth samples * ie Two non-consecutive samples differ substantially from one another * These criteria establish that * the first, second, fifth and sixth samples are not part of the transition and That a substantial transition occurs between the two groups of samples. As shown in Figures * 2a and 2b *

The first loo transition detector of Fig. 1 includes a first 3o digital subtractor * which produces an absolute value of the difference between the sizes of consecutive samples E and which is fed to the second comparator 32 * The second comparator 32 produces an output for bringing the opening level k Similarly, the second digital subtractor 34 creates an absolute value of the difference between successive samples .A.A and the third comparator 36 brings the opening level to the second input of the first product circuit 46 * Is-11 the difference A - В in absolute value less * than the relatively small reference value REF — 2 * In addition, the third digital subtractor 4o generates from the consecutive samples В and E the absolute value of the difference В - E than the MIN value, cause Concerns that the first comparator 42 applies the opening level to the third input of the first product circuit 46 * Assuming the opening signal EN is present, the input frequency of the first product circuit 46 generates a control signal MC which causes multiplexers 20 and 22 to supply the sample value E to the input of the second delay stage 14 and the sample value В to the input of the third delay stage 16 * As described above * These criteria for detecting the transition Are summarized in Table 1 ·

Table 1

Number Elements Test criteria on the product circuit 1 3o, 32 | E ~ F | <REF 1 2 34.36 A-B | <REF 2 3 4o, 42 | b-e | min 4 48 EN - 1

Pulse generator or digital stepper 47 is responsive to the first AND circuit 46 and the clock signal t * p ^ro create Impulse MC, for example, one period of a wide, and not at the outlet generate a subsequent pulse, for example in two periods sampled · Digital stepper 47 prevents continuous reclrkulacl sample loop including a second multlplexer 22 and a third delay stage 16 * that could occur when the transition detection signals enter the transition enhancement circuit * Alternatively, if the transition detector and enhancement circuit use separate but parallel delay stages, the digital stepper 47 is not required *

The control circuit 48 generates an opening signal EN * that opens and closes the first loo transition detector. The control circuit 48 is, for example, a transition detector generating an opening EN signal in response to transitions in the Brightness YS signals. The CS and YS signals are temporally related since they are the components of the signals representing the same figure. The control circuit 48 may be omitted.

The second transition detector 200 shown in FIG. 3 is a modification of the first transition detector loo in which additional detection criteria * must be met to produce the control signal MC. Additional detection criteria ensure * that the gradient will only be highlighted * if it is a smooth and monotonous gradient, thus avoiding the loss of valid, relatively high-frequency sample information.

This is achieved by additional detection criteria requiring that the difference in the size of the transition between the second and the fifth sample does not exceed the maximum value and that the sizes of the third and fourth samples are between the average of the second and fifth sample sizes, respectively.

The second transition detector 200 comprises digital subtractors 3o, 34 and 4o and comparators 32, 26 and 42 that correspond to similarly numbered elements of the first transition detector loo as described above. Referring to Fig. 2, Fig. 3, the fourth comparator 44 applies an opening level to the input of the second product circuit 46 * when the absolute value of the difference - - E is generated by the third digital subtractor 40o less than the maximum value MAX itself greater than the minimum value. The third digital subtractor 40 also creates a sign bit SB _B which indicates if the transition is in the positive or negative direction and which is used to simplify the construction of the correlator for testing additional detection criteria.

The criteria indicating smoothness and monotony of the transition are tested by comparators 7o, 74, 64 and 8V as follows. The fifth comparator 70 compares the samples V and C, the result of which is selectively inverted by the first controllable inverter block 72 in response to the sign bit SB. Thus, one input of the second product circuit 46 is opened when the criterion VC for the positive direction of the transitions is met and when the criterion VC is met for the negative direction of the transitions. Similarly, the sixth comparator 74 and the second controllable inverter block 76 open the input to the second product circuit 46 when the criterion D < E for the positive direction of the transitions is met and when the criterion D > E for the negative direction of the transitions. This ensures that sample sizes C and D are between samples В and E, which is the first indication of monotony.

The summation circuit 8o and the divider circuit 82 by the two forming the diameter of the sample sizes V and E, which diameter is indicated by imaginary lines at level 1/2 (v ♦ E) in Figures 2a and 2b. For the sampled analog signals, the sum circuit 8o and the divider circuit 82 are two of the resistor network. For digital signals *, the summation circuit 8o is a digital summation circuit and the divider circuit 82 is a binary. The seventh comparator 84 and the third controllable inverter block 86 opening the input of the second product circuit 46 when the criterion C <1/2 (В + E) for positive direction transitions is met and when the criterion C 1/2 (В + E) for negative transitions. Similarly, the eighth comparator 88 and the fourth controllable inverter block 9o open the input of the second product circuit 46 if the criterion D> 1/2 (B + E) is met for the positive direction of the Going Transitions and when the criterion D4.1 / 2 (в) ♦ E) for Negative Transitions. This ensures that the sample size C is between the average level V and E and the sample size B, and that the sample size D is between the average level and the sample size E, thereby providing a further indication of monotony.

The second product circuit 46 * generates a control signal MC in response to signal coincidence at all of its inputs. These detection criteria are summarized in Table II.

Table II

Number Circuits Test criteria on the product circuit (reference numbers) Transitions in a positive direction Transitions negative, direction 1 · 3o, 32 | E-F «REF -1 | E-F | <REF -1 2. 34, 36 | A-D | <REF — 2 | A-B | <REF — 2 3. 4o. 42 ) B-E |> MIN | B-E | > MIN 4. 4o, 44 | В-Е | <МАХ | B-E | <MAX 5. 7o. 72 В <C В> C 6. 74 »76 D <E D> E 7. 8o, 82, 84, 86 C <1/2 (E4B) C> 1/2 (B4E) 8. 8o, 82o, 88o, 9o D> 1/2 (E 4 li) D <1/2 (B4E) 9. 48 EN - 1 EN - 1

For an 8-bit digital chrominance signal having values corresponding to decimal values from zero to 255, the following Rated Comparative Levels are satisfactorily: REF -1-8 »REF -2-8, MIN-48, MAX-255.

The remaining portion of FIG. 3 illustrates a control circuit 48 comprising a luminance signal transition detection system. The luminance signals YS are then delayed by delay stages 31o, 312, 314, 316, and 318 and are coupled to a third transition detector 300. For example, the third transition detector 300 is similar in design to any of the loo or 200 detectors as described above, except that the control signal therefrom is applied to the second product circuit 45 * as the opening signal EN. Delay stages 31o to 318 may be delay lines existing as part of the final pulse response or comb filter in the brightness processing circuits.

Giant. 4 and 5 show exemplary embodiments useful, for example, as a replacement for comparators

32, 36, 42, or 44 of Figs. 1 and 2. These exemplary embodiments may be used where the digital samples are represented, in sign form size. The inverted input of the third product circuit 32 * of FIG. 4 responds to the selected number of higher valid bits, but not to the sign bit of the difference generated by the first digital subtractor 3o, all zero to apply the opening level to the first product circuit 46 or the second product circuit 46 *. . The logic sum negation circuit 32 of FIG. 4 responds to the selected number of higher valid bits of the absolute value of the difference produced by the first digital subtractor 3o, all of which are zero, to bring the opening level beyond the first product circuit 46 or the second product circuit 46 '.

The REF-1 reference level value provided by the third product circuit 82 * or logical sum negation circuit ** is given (2 ^ -1), where N is the number of lower valid bits not connected to it, and is enumerated in Table III.

Table III

Г

Product circuit 32 * and logic sum circuit 32 ne gace | 1 Value k El · - 1 brought higher p latch bits t 1 lower valid bits not supplied - 1 8 1 1 ! O 1 1 O 7 1 | 1! 1 6 1 2! 3 5 1 1 ³ ! 7. 4 1 1 4 i | 15 Dec 3 1 ⁵ ! 31 2 1 1 6 1 F 63 1 1 1 AND 1 ⁷ ! 1 1 127 1 1

Giant. 6 illustrates an exemplary embodiment useful, for example, as a replacement for the first comparator 42 of FIG. 2, when the digital samples are presented in the form of a signed size. The logic sum circuit 42 * responds to any of the higher valid bits of the absolute value of the difference produced by the third digital subtractor 4o, each having a value of 1 for bringing the opening level to the first product circuit 46 or the second product circuit 46. -1), where N is the number of lower significant bits not connected to the logical total circuit 42,

Other possible modifications are within the scope of the invention. For example, the sum circuit V0, the divider circuit 82 by the two, the eighth comparator 88 and the fourth inverter block 9o of FIG. 2 can be eliminated and samples C and D can be fed directly to the seventh comparator. This provides an indication of monotony, where the criterion C ^ D is met for positive-going transitions and where the criterion D is met for negative-going transitions. In addition, the comparator arrangement of FIGS. 4, 5 and 6 illustrates that the absolute value of the difference size is obtained for signed signed digital values by excluding the sign bit SB from the comparison.

The number of delay stages lo, 12, 14 ..... that are used, the repetition rate of the clock signal f »are from the subsequently delayed samples of the CS signals attached to the loo and detector transition detectors and the location of the multiplexers 2o and 22 in the delay stage cascade, all the influence on the detection limits of the rise and fall times and the degree to which the rise and fall times are highlighted. For example, a greater number of delay stages are required to enhance the transition of luminance signal samples generated at four times the subcarrier frequency, i.e., 4 t, which is approximately equal to 14.32 MHz for the NTSC system. In addition, the number of samples in the groups may be greater or less than the two samples A, V and E, F described herein and the number of samples between these groups may be greater or less than the two samples C, D as described herein.

Transitions faster than those shown in Figs. 2a, 2b can be highlighted if there is at least one sample signal within the transition, i.e., if the two samples compared to detect the transition are not consecutive. For example, the circuit of FIG. 1 may be modified so that the signal samples E and C of FIG. 2 are compared by a third digital subtractor 4o and a first comparator 42 for detecting the transition, in which case the delay stages 12 and 14 and the first multiplexer 2o are essential elements. and only substitutions 54 and 64 of Figures 2a and 2b are made. In this way, the second multiplexer 22 can be eliminated and the second delay stage 14 can be connected directly to the third delay stage 16.

While the transition enhancement described herein has led to a decrease in the ramp time, the invention is also useful in increasing the ramp time. In this modification, the first multiplexer 20 is inserted before the first delay stage 12 and receives signal samples E and D at its inputs. The second multiplexer 22 is inserted before the fourth delay stage 18 and receives signal samples S1 at its inputs. The first delay stage 12 is connected to the second delay stage 14 and is connected to the third delay stage 16. to cause. That sample C is replaced by sample V and sample

D will be replaced by sample E.

In another exemplary embodiment, the controllable inverter blocks 72, 76, 86, and 9o may be eliminated, and the multi-plexers may be added to reverse the inputs to each of the comparators 7o, 74, 84, and 88. converters, such as the binary complement converter to binary code of FIG. 7, at respective locations in the loo and detector transition detectors.

Claims (2)

SUBJECT OF THE INVENTION 1. A signal processing circuit comprising an input for receiving input signals and an output on which the output signals are generated in response to input signals, and delay stages connected in cascade between the input and output for sequentially delaying the input signals, comprising a detector ( loo) of the transition connected to the delay stages (lo, 12, 14, 16, 18) and secondly to the first multiplexer (2o) connected to the delay stages (lo, 12, 14, 16, 18) and to the detector, (loo) a transition for selectively coupling the input of the first delay stage (12) to the input of the second delay stage (14) in response to the detection of the magnitude transition, and the second multiplexer (22) connected to the delay stages (lo, 12, 14, 16, 1Θ) a transition detector (loo) for selectively coupling the input of the fourth delay stage (18) to the input of the third delay stage (16) in response to the detector The transition detector (loo) comprises a first comparator (42) for detecting a difference in signal sample size from successively delayed input signals that exceeds a predetermined minimum value, wherein the transition detector (loo) further comprises a comparator member consisting of a second comparator (42). 32) and a third comparator (Эб) for detecting a size difference between the other successively delayed input signals, while the first multiplexer (2o) has a first input to which the output of the first delay stage (12) is connected and its output is connected to the input of the third delay steps (14), 2. The circuit of claim 1, comprising a second multiplexer (22) to which a second delay stage output (14) is connected to a first input, a second delay stage output (1б) is connected to a second input, and an output is connected a third delay stage (16).