CS235796B1 - Separating element connection for recording and reading channel of magnetic disk store - Google Patents

Abstract

The goal of the solution is simple connection increase the write-off effect when writing and use all three sections normally produced six-fold switch with field control transistors. This goal is achieved wiring with field-containing switches controlled by transistors and control circuit The switch uses a sixfold switch with field driven transistors from which the two sections are used as write-read switches and a third section as switches in the control circuit. Control circuit, controlled the write current indication circuit, includes not a level converter delayed level converter with inverted input delayed Circuit. Wiring can be used for magnetic recording and reading channels digital recording, especially for disk recorders memoirs.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to the use of a separator for a write-and-read channel of a magnetic disk storage device.

The separator for the write-and-read channel of the magnetic disk memory protects the read-amplifier input from large voltage surges on the magnetic heads as it is written, and ensures the transient event duration in the read-amplifier is as short as possible when switching the channel from write to read. In addition, in the case of channels which work with the erasing of the track, the separating member is required not to transmit interference to the input of the reading amplifier even in the case of the controlled switching off of the erasing current after writing.

Known wiring separators suitable for write and read channels operating with more than one magnetic head are often made up of either diode bridges of varying wiring, which may be part of a diode-transistor matrix for selecting magnetic heads, or a pair of field-controlled transistors, for example, J-FETs which, with the load impedance of the magnetic heads when read, form essentially a voltage divider controlled by the write-read switch signal.

The disadvantage of the first group of wiring isolators is the penetration of a fairly high level of voltage to the input of the reading amplifier during writing. The disadvantage of the second isolation element wiring group, which exhibits a considerable isolation effect of the reading amplifier from the write circuitry, is that there is a relatively large, phase-to-phase shift of the DC voltage levels at the isolator output when switching.

These disadvantages are overcome by the wiring of a separator for the write-and-read channel of the magnetic disk memory of the present invention, which is based on the output of the write-current indication circuit being connected to a control circuit whose delayed output

235 798 steering control. / connected to the control input of the first field controlled transistor of the first switch and to the control input of the second field controlled transistor of the second switch and its output of a delayed control signal is connected to the control input of the second field controlled transistor of the first switch and the input of the first switch is connected to zero potential, possibly via a second bias diode, the second input of the first switch is connected to the cathode of the first separating diode of the write amplifier and to the anode of the second separating diode of the write and read winding of the magnetic head the second separation diodes of the write amplifier and the anode of the first separation diode of the write and read windings of the magnetic head, the second input of the second switch is connected to zero potential, through the first bias diode, the output of the first switch is connected through the first output resistor in the positive voltage backyard of the first source, on the first output terminal wiring, or through the first coupling capacitor, the output of the second switch is connected through the second output resistor on the positive voltage terminal of the first source, on the second output terminal of the wiring, possibly via a second coupling capacitor and the output of the first switch and the output of the second switch are connected by a load resistance of the magnetic head when reading. The first bias resistor is connected to the series with the first bias diode and the second bias resistor is connected to the series with the second bias diode. In the series with the first bias diode and the first bias resistor is further included the collector and the zero potential connected to the emitter of the transistor and into the series with the second bias diode and the second bias resistor is further down the collector and the zero potential connected to the emitter of the transistor.

In the control circuit 3e, its input branches to a non-delayed level transducer, the output of which is both the output of a delayed control signal of the control circuit and a delayed level transducer with an inverted input which includes a delay circuit. . The input of the control circuit is connected to the input of the first open-collector inverter whose output is connected to the control input of the first field-controlled switch transistor and through the first collector resistor to the positive voltage terminal of the second source. inverter with open3

239 798, the output of which is connected to the control input of the second field-controlled switch transistor and through the second collector resistor to the positive voltage terminal of the second source, the first switch input is connected via the first working resistor to the negative voltage terminal. the second input of the switch is connected through the second negative working terminal and simultaneously forms the output of the delayed control signal of the control circuit, the output of the switch is connected to the positive voltage terminal of the second source.

An advantage of the circuitry according to the invention is that, at a relatively low level of circuitry, its separation effect on writing is large. At the same time, a slight differential voltage at the output when switching from write to read does not result in a transient event in the reading amplifier. Another advantage is the possibility of using all three sections of a commonly produced six-channel switch with field-controlled transistors.

An example of a separation member for the magnetic disk storage write and read channel of the present invention is shown schematically in the accompanying drawing, with one magnetic head.

Input terminal clamp. 1 of the write current is connected to the emitter of the first and second terminal transistors 42, 43 of the write amplifier (not shown). Clamp j? The first write current switching signal is connected based on the first write amplifier transistor 42 whose collector is connected to the anode of the second write amplifier diode 68 and through the first load resistor 56 of the magnetic head 14 when writing to the input 19 of the write current indication circuit 12. The terminal J of the second write current switching signal is connected on the basis of the second write amplifier transistor 43 whose collector is connected to the anode of the first write amplifier diode 67 and through the second load resistor 57 of the magnetic head 14 when writing to the input 19 of the write current indication circuit. The cathode of the first diode 66 of the write amplifier is connected to the second input 28 of the first switch 16 and to the anode of the second diode 66 of the write and read windings of the magnetic head 14, the cathode is connected to the second terminal 73 of the write and read windings of the magnetic head 14. the write amplifier diodes 68 are connected to the first input 31 of the second switch 17 and to the anode of the first magnetic diode read / write winding »14, the cathode of which is connected to the first 4 * 35 7M water 72 4, the cathode is connected to the first pin 24 of the magnet wind head 14 and the second pin 23 of the magnetic head 14 is connected to the center of the write and read windings and to the wheel. The first input 27 of the first switch 16 is connected to the anode of the second bias diode 62, the cathode of which is connected to the collector of the selective transistor 44 via the second bias resistor 53. The second input 32 of the second switch 17 is connected to the anode of the first bias diode 61. the positive voltage terminal 8 of the first source is connected via the collector resistor 54 to the collector of the transistor 44. whose emitter is connected to zero potential and whose base is connected to the signal terminal 2 for selecting the magnetic head 14 «Output 20 of the write current indication circuit 12 is connected to the input 21 of the control circuit 15» In the control circuit 15, the input 21 branches to a non-delayed level converter via a first open collector 59 and to a delayed level converter via a second An open collector rtor 60 in series, which is preceded by an inverter 56 with a delay circuit 13 in series. The delay circuit 13 is formed by a delay resistor 49 and a delay capacitor 69. The output of the first open collector 59 is connected to the control input 37 of the first field-controlled switch transistor 18 and via the first collector resistor 47 to the positive voltage terminal 9 of the second source. The output of the second open-collector inverter 60 is coupled to the control input 38 of the second pole-controlled transistor 18b, via the second collector resistor 48 to the positive voltage terminal 9 of the second source. The first input 35 of the switch 18 is connected to the output 26 of the delayed control signal of the control circuit 15 and via the first working resistor 45 to the negative voltage terminal 11. The second input 36 of the switch 18 is connected to the output 25 of the delayed control signal of the control circuit 15 and via the second working resistor 46 to the negative voltage terminal 11. The output 41 of the switch 18 is connected to the positive voltage terminal 6 of the second source. The non-delayed control signal output 26 is connected to control input 30 of the second field-controlled transistor of the first switch 16 and to control input 33 of the first field controlled transistor of the second switch 17. The delayed control signal output 25 is coupled to control input 29 of the first5

23S 79>

The output 39 of the first switch 16 is connected via the first coupling capacitor 70 to the first output terminal 6 of the connection for connection to a read amplifier (not shown) and through the first output resistor 50 to the terminal 8 <

the anode of the first protective diode 63, the cathode of which is connected to the positive voltage terminal 10 of the third source. The output 40 of the second switch 17 is connected via the second coupling capacitor 71 to the second output terminal 7 of the wiring, on the other hand through the second output resistor 51 to the positive voltage terminal 8 of the first source and to the anode of the second protective diode 64. voltage of the third source. The output 39 of the first switch 16 and the output 40 of the second switch 17 are connected by a load resistor 55 of the read head 14.

The delay circuit 13 can also be placed elsewhere in series with the delayed level converter. The delay circuit 13 can also be replaced by parasitic capacitances and by increasing the value of the second working resistor 46, which would be much greater than the value of the first working resistor 45 «Level converters are basically two independent amplifiers to convert the voltage level from TTL logic to the level needed for controlling the gates of the respective field-controlled transistors within switches 16, 17. Two of the three sections of a conventional six-channel monolithic switch are used as switches 16, 17. Its third section is used as the switch 18 in the control circuit 15. way of another magnetic head. Then, only one pair of the first bias diode 61 and the first bias resistor 52 and only one pair of the second bias diode 62 and the second bias resistor 53 can be used for all magnetic heads, both of which are connected directly to zero potential. If the effects of the winding resistance and the winding lead of the magnetic heads are neglected, the pre-bias resistors 52 and 53 can be omitted. If the reading amplifier has a large coefficient suppression factor of the input voltage, in some cases the pairs of the bias diode 61, 62 and the bias resistor 52, 53 may be omitted. The reading resistance of the magnetic head 14 can also be shifted up to the output terminals 6, 7. Coupling capacitors 70, 71 may also be omitted in some cases.

With the signal applied to terminal 6, the selective transmit6 is switched on

239 79β tor 44 to select the desired magnetic head 14 »When writing information, the write current is applied to terminal 1. The control circuit of the end transistors 42, 43 switches this current in accordance with the coded sequence of written information through the write amplifier diodes 67, 68 and through separating diodes 65 «66 of the magnetic head 14 write and read winding into the selected magnetic head 14 write and read winding The high voltage amplitude on the magnetic head 14 write and read winding that occurs during writing does not reach the read amplifier input from the output terminals 6 and 7, since the write current indication circuit 12 having a high voltage level at its output 20 causes the control circuit 15 to cause the channel between the second input 28 and the output 39 of the first switch 16 as well as the channel between the first input 31 and the output 40 The second switch 17 will be closed while the channel between by the first input 27 and the output 39 of the first switch 16, as well as the channel between the second input 32 and the outlet 40 of the second switch 17 will be opened. Despite the resulting dividers, that is, closed channels and open channels in series with biasing diodes 61, 62 and biasing resistors 52, 53 that only the residual voltage, of the order of mV, is input to the read amplifier input. The input amplifier input is thus protected against a large voltage amplitude on the magnetic heads, and the low level of alternating residual voltage at the output of the decoupling element will not cause the read amplifier to be congested. From the positive voltage terminal 8, direct current flows through the open channels and output resistors 50. 51 through diodes 61, 62 and resistors 52, 53 to transistors 46 and to zero potential. After the write function has been terminated and the write circuits have been calmed, a negative voltage is received from the write current indication circuit 12 to isolate the diodes 67, 68, which will close the diodes and disconnect the remaining diode matrix and the isolator from the write amplifier. The output 20 of the write current indication circuit 12 goes from high to low and, via control circuit 15, opens the channel between the second input 28 and the output 39 of the first switch 16 as well as the channel between the first input 31 and the output 40 of the second switch 17 input 27 and output 39 of the first switch 16, as well as a channel between the second input 32 and the output 40 of the second switch 17. Current is now flowing from the positive voltage terminal 8 through the output resistors 50, 51 through open channels, decoupling diodes 65, 66 and write / read winding the magnetic head 14 through the transistor 44 to zero potential. With this current, the separating diodes 65 and 66 are opened and the sensed duty cycle 7 is opened

23S 788, the voltage from the write and read windings of the magnetic head 14 passes through the open channels to the output terminals 6 and 7 of the isolation member wiring. The values of the bias resistors 52, 53 are selected so that the DC voltages at outputs 39 and 40 are the same when read and read, i.e., at the bias resistors 52, 53, the currents flow from the output resistors 50, 51 at write generated the same DC voltages as the flow of the same current between the terminals 72 and 23 and 73 and 23 of the winding of the magnetic head 14 when read. Then, when switching from read to read, there will be virtually no differential voltage jump between the outputs 39 and 40, which would cause an undesired transient event in the reading amplifier, which would have to be wiped off by part of the track of the recording medium. There is no differential voltage jump between the outputs 39 and 40 even when the decoupler switches during a controlled tripping of the clearing current which is delayed after the tripping of the write. The leakage current flows from the terminal 4 through the diode 22 to the sweep winding of the magnetic head 14 when the saturation voltage of the selective transistor 44 can be varied. To maximize the same DC voltages at outputs 39, 40 In addition, a delay circuit 13 is included in the inverted input level path in the control circuit 15. When switching from write to read, when the output current indication circuit 20 goes to a low level, with a cannu the first input 27 and the output 39 of the first switch 16 as well as the channel between the second input 32 and the output 40 of the second switch 17 after opening the channel between the second input 28 and the output 39 of the first switch 16 This will limit when switching a differential voltage peak is generated at the outputs 39 and 40 of both switches 16 and 17, which switching takes place without a transient event in the reading amplifier, which is capable of correctly processing the read voltage immediately after switching.

The invention can be used for write-and-read channels of magnetic digital recording, in particular for disc memories.

Claims (5)

OBJECT OF THE INVENTION 235 7M CLAIMS 1. Connection of a separator for a write-and-read channel of a magnetic disk storage, with switches comprising field-controlled t transistors and a control circuit, characterized in that the output (20) of the write-current indication circuit (12) is connected to a control circuit (15) the delayed control signal output (25) is connected to the control input (29) of the first field-controlled transistor of the first switch (16) and to the control input (34) of the second field-controlled transistor of the second switch (17) and its output (26) of the delayed control signal is connected to the control input (30) of the second field-controlled transistor of the first switch (16) and to the control input (33) of the first field-controlled transistor of the second switch (17), the first input (27) of the first switch (16) the second input (28) of the first switch (16) is connected to the cathode of the first compartment the write-in diodes (67) of the write amplifier and the anode of the second write-in diode (66) of the write / read winding of the magnetic head (14), the first input (31) of the second switch (17) being connected to the cathode of the write-off diode (68) the anode of the first separating diode (65) of the write and read windings of the magnetic head (14), the second input (32) of the second switch (17) being connected to zero potential via the first bias diode (61), the output (39) of the first switch 16) is connected via the first output resistor (50) to the positive voltage terminal (8) of the first source, and to the first output terminal (6) connected via the first coupling capacitor (70), the output (40) of the second switch (17) on the one hand through the second output resistor (51) to the positive voltage terminal (8) of the first source, on the other to the second output terminal (7) of the wiring, or via the second coupling capacitor (71) and the output (39) of the first switch however, the output (40) of the second switch (17) is connected by a load resistance (55) of the magnetic head (14) when read. 2. The circuit according to claim 1 _f, characterized in that a first bias resistor (52) is connected in series with the first bias diode (61) and a second bias resistor (53) is connected in series with the second bias diode (62). 3. Connection according to claim 2, characterized in that in series with the first biasing diode (61) and the first biasing resistor (52) is The collector and the neutral potential connected to the emitter of the selective transistor (44) are further coupled and the collector and the neutral potential connected to the emitter of the selective transistor (44) are in series with the second bias ciodo (62) and the second bias resistor (53). . 4. Connection according to claim 1, characterized in that in the control circuit (15) its input (21) branches to a delayed level transducer, the output of which simultaneously forms the output (25) of the delayed control signal of the control circuit. an inverted input level transducer (in which a delay circuit is connected in series, the output of which also forms a delayed control signal output (26) of the control circuit (15). 5. The circuit according to claim 4, wherein the input of the control circuit (15) is connected to the input of the first open collector (59), the output of which is connected to the control input (37) of the first field controlled transistor of the switch (18); through the first collector resistor (47) to the positive voltage terminal (9) of the diode source, both via the delay circuit (13) and the inverter (58) in series, to the input of the second inverter (60) with open collector, the output is connected to the control input (38) of the second field-controlled switch transistor (18) and through the second collector resistor (48) to the positive voltage terminal (9) of the second source, the first input (35) of the switch (18) is connected through the first working resistor (45) to the negative voltage terminal (11) and simultaneously form an output (26) of the non-delayed control signal of the control circuit (15), the second input (36) of the switch (18) is connected via a second working resistor (46) to the negative terminal Tension and simultaneously form the output (25) of the delayed control signal of the control circuit (15), the output (41) of the switch (18) being connected to the positive voltage terminal (9) of the other source.