CN2888736Y - Soft-switching power converter with energy-saving circuit for light-load operation - Google Patents

Abstract

The utility model relates to a soft switching formula power converter, it includes that a first switch is used for switching a transformer and carries out energy transfer. A second switch switches the energy of a capacitor to the transformer for soft switching in the next switching cycle. A control circuit is coupled to the output of the power converter for regulating the output of the power converter by generating a first signal and a second signal in response to a feedback signal. After the first switch is turned off and before the second signal is enabled, a first delay time is generated. And a second delay time is generated after the second switch is turned off and before the first signal is enabled. In a light load condition, the second delay time is proportionally increased according to the decrease of the feedback signal.

Description

Soft-switching power converter with energy-saving circuit for light-load operation

technical field

The utility model relates to a power converter, in particular to a control circuit of the power converter.

Background technique

A power converter is used to convert an unregulated power source into a constant voltage source. A power converter generally includes a transformer including a primary winding and a secondary winding for providing isolation. A switching device is connected to the primary winding to control the transfer of energy from the primary winding to the secondary winding. While higher operating frequencies allow power converters to be smaller in size and weight, switching losses, component stress, and electromagnetic interference are inherently problematic. In recent developments, a common soft switching phase shift design has been proposed to reduce switching losses in high frequency power conversion. Among these developments, the full-bridge quasi-resonant ZVS technique is described as follows: Proposed by Christopher, P. Henze, Ned Mohan, and John G. Hayes in US Patent No. 4,855,888 on August 8, 1989 "Constant Frequency Resonant Power Converter with Zero Voltage Switching"; proposed by Guichao C.Hua and Fred C.Lee on August 15, 1995 in US Patent No. 5,442,540 "Soft-switching PWM Converters"; and "Soft-switched Full-bridge Converters" proposed by Yungtaek Jang and Milan M. Jovanovic on March 12, 2002 bridge Converters)". Active clamping (active clamp) techniques for forward ZVS power converters are disclosed below, for example by F. Don Tan in U.S. Pat. "Double Forward Converter with Soft-PWM Switching"; the "Active Clamp" proposed by Simon Fraidlin and Anatoliy Polikarpov in US Patent No. 6,191,960 on February 20, 2001 Bit-insulated power converter and its method of operation (Active Clamp Isolated Power Converter and Method of Operating Thereof)". For the half-bridge technology, an asymmetric design for ZVS was developed, namely "Asymmetrical Power Converter and Method of Operation Thereof," U.S. Patent No. 6,069,798, May 30, 2000 by Rui Liu (Assymmetrical Power Converter and Method of Operation Thereof)". In various ZVS converters, the parasitic leakage inductance of the transformer and additional magnetic components are used as resonant inductors or switches to generate ring currents to achieve zero-voltage switching.

Figure 1 illustrates a conventional active clamp power converter. 1A-1D illustrate the four operational phases of the power converter described above. FIG. 1A illustrates when a first signal S ₁ turns on transistor Q ₁ for transferring energy from an input of the power converter to an output of the power converter through a transformer T ₁ . As shown in FIG. 1B, when the transistor _Q1 is turned off, the energy of the transformer _T1 will flow into a capacitor _C1 through a parasitic diode _D2 . At the same time, a second signal S ₂ will turn on a transistor Q ₂ , thereby achieving soft switching of the transistor Q ₂ . As shown in FIG. 1C , when the energy of the transformer _T1 is fully discharged, the capacitor _C1 starts to charge the transformer _T1 through the turned-on transistor _Q2 . FIG. 1D illustrates a fourth phase of operation in which the second signal S ₂ is deactivated to turn off transistor Q ₂ , thereby cutting off the current flowing between transformer T ₁ and capacitor C ₁ . Meanwhile, the energy stored in the transformer _T1 generates a loop current, thereby discharging the parasitic capacitor _Cj of the transistor _Q1 . In order to turn on the parasitic diode _D1 to achieve soft switching of the transistor _Q1 , the charge of the parasitic capacitor _Cj must be completely discharged beforehand.

In order to qualify for conversion the following conditions must be met:

${{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ></span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; \&times;</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}$

where _L is the inductance of the primary winding of transformer _T1 , _I is the current of the transformer primary winding, and V is the _input voltage of the power converter.

The resonant frequency f _r is given by:

f _r ＝1/(2π×L _P ×C _j )

A delay time T _D1 for completing the phase shift (phase shift) of the soft handover is given by the following equation:

T _D1 =1/(4×f _r )

＝π×L _P ×C _j /2

FIG. 2 illustrates a conventional asymmetrical half-bridge forward power converter, where the operation of signals S ₁ and S ₂ is the same as that of the power converter shown in FIG. 1 . Although the aforementioned power converter can perform soft switching to reduce the switching loss under heavy load conditions, its disadvantage is that the power consumption is still relatively high under light load conditions.

Utility model content

The purpose of this utility model is to provide a soft switching power converter, thereby reducing power consumption under light load conditions.

The soft switching power converter includes a capacitor and a transformer. For soft switching operation, the capacitor is connected to the transformer. A first switch is used to switch the transformer, thereby transferring power from an input of the power converter to an output of the power converter. A second switch is used to switch the energy of the capacitor to the transformer, thereby generating a loop current to complete the soft switching operation of the first switch. A control circuit is connected to the output of the power converter to receive a feedback signal. The control circuit responds to the feedback signal to generate a first signal and a second signal for adjusting the output of the power converter. A first signal and a second signal are respectively coupled to the first switch and the second switch for switching operation. A first range of the feedback signal represents a heavy load condition, and as the on-time of the first signal decreases, the on-time of the second signal increases. On-time is defined as the time interval during which a signal is active. A first delay time is generated after the first switch is turned off and before the second signal is enabled. After the second switch is turned off and before the first signal is enabled, a second delay time will be generated. The second delay time is constant within the first range of the feedback signal. The second delay time is variable within a second range of the feedback signal, wherein the second delay time increases proportionally in response to the feedback signal. The second range of the feedback signal represents a light load condition. The control circuit includes a threshold for defining a first range and a second range of the feedback signal. In addition, the control circuit also includes an input terminal and a programming terminal. The input terminal is used to program the second delay time of the first range of the feedback signal. The programming terminal is developed for programming criticality.

The utility model has the advantage of reducing power consumption under light load conditions.

The above description is only an overview of the technical solution of the utility model. In order to understand the technical means of the utility model more clearly and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiment of the utility model with accompanying drawings. back.

Description of drawings

The accompanying diagrams provide further understanding of the utility model and are integrated as a part of this specification. These diagrams illustrate the embodiments of the present invention and explain the principle of the present invention together with the relevant description.

FIG. 1 is a circuit diagram of a conventional active clamp power converter;

1A to 1D are schematic diagrams illustrating four operating stages of the power converter shown in FIG. 1;

Fig. 2 is a circuit diagram of a conventional asymmetrical half-bridge forward power converter;

3 is a circuit diagram of a soft-switching power converter according to an embodiment of the present invention;

4A and 4B are signal waveform diagrams of the power converter shown in FIG. 3;

FIG. 5 is a circuit diagram of a control circuit according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of an oscillation circuit according to an embodiment of the present invention;

FIG. 7 is a circuit diagram of a delay circuit according to an embodiment of the present invention.

Detailed ways

FIG. 3 is a circuit diagram of a soft-switching power converter according to an embodiment of the present invention. It includes a magnetic device (such as a transformer 30). The transformer 30 and a capacitor 35 are connected in series. Capacitor 35 is used for soft switching. A first switch 10 is used to switch the transformer 30 to transfer energy from an input of the power converter to an output of the power converter. A second switch 20 is connected to the capacitor 35 to switch the capacitor 35 for transferring the energy of the capacitor 35 to the transformer 30 . A control circuit 100 is coupled to the output of the power converter in response to a feedback signal V _FB to generate a first signal S ₁ and a second signal S ₂ for regulating the output of the power converter. The first signal S ₁ and the second signal S ₂ are coupled to and switch the first switch 10 and the second switch 20 respectively. An error amplifier 60 with a reference signal _VR is connected to the output of the power converter via resistors 51 and 52 . A resistor 53 and a capacitor 54 establish a frequency compensation network for the error amplifier 60 . The output of error amplifier 60 is connected to a coupler 65 (eg, an optocoupler). The output of the coupler 65 generates the feedback signal V _FB to a feedback terminal FB of the control circuit 100 . The control circuit 100 further includes a threshold, which is used to define whether the feedback signal V _FB is in a first range or in a second range. The first range of the feedback signal V _FB represents a heavy load condition. And the second range of the feedback signal V _FB represents a light load condition. The first signal S ₁ and the second signal S ₂ are generated corresponding to the feedback signal V _FB . In the first range of the feedback signal V _FB the enable time of the second signal S ₂ increases in response to a decrease in the enable time of the first signal S ₁ .

4A and 4B are signal waveform diagrams of the power converter shown in FIG. 3 . FIG. 4A illustrates the waveforms of the first signal and the second signal under heavy load conditions. FIG. 4B illustrates the waveforms of the first signal and the second signal under a light load condition. After the first switch 10 is turned off and before the second signal S ₂ is turned on, a first delay time T _D1 is generated. After the second switch 20 is turned off and before the first signal S ₁ is turned on, a second delay time T _D2 is generated. The second delay time T _D2 is constant within the first range of the feedback signal V _FB . The second delay time T _D2 is variable within the second range of the feedback signal V _FB , wherein the second delay time T _D2 extends proportionally with the decrease of the feedback signal V _FB .

The control circuit 100 shown in FIG. 3 further includes an input terminal RD for programming the second delay time T _D2 in the first range of the feedback signal V _FB . A resistor 56 is connected from the input terminal RD of the control circuit 100 to a ground reference, thereby programming the second delay time T _D2 . Additionally, a resistor 57 is connected from a programming terminal RP to the ground reference, thereby programming the threshold. A current sensing terminal VS of the control circuit 100 is connected to a resistor 50 for detecting a switching current signal V _S of the transformer 30 , so as to implement Pulse Width Modulation (PWM) control of the control circuit 100 .

FIG. 5 is a circuit diagram of the control circuit 100 according to an embodiment of the present invention. The control circuit 100 includes an oscillator circuit 200 for generating a pulse signal PLS, a sawtooth signal RMP, and a maximum duty cycle signal MD. The pulse signal PLS is supplied to a clock input in a flip-flop 85 via an inverter 71 . A comparator 80 is used to reset the flip-flop 85 . Two inputs of the comparator 80 are respectively connected to the feedback terminal FB and an output of a circuit 350 . The circuit 350 generates a slope signal by adding the sawtooth signal RMP and the switching current signal V _S . Once the ramp signal is higher than the feedback signal V _FB , the flip-flop 85 is reset. An output of flip-flop 85 is connected to a third input of an AND gate 91, whereby the first signal _S1 is generated. A second input and a fourth input of the AND gate 91 are respectively connected to an output of the NOT gate 71 and the maximum duty cycle signal MD. A flip-flop 86 with a clock input is coupled to the first signal S ₁ via a delay circuit 300 and a NOT gate 72 . FIG. 7 is a circuit diagram of the delay circuit 300 . The delay circuit 300 determines the first delay time T _D1 . Therefore, the flip-flop 86 is enabled after the first delay time T _D1 has elapsed after the falling edge of the first signal S ₁ . The output of NOT gate 71 is used to reset flip-flop 86 . When the pulse signal PLS is enabled, the flip-flop 86 is reset. An output of flip-flop 86 is connected to a first input of an AND gate 92, whereby the second signal _S2 is generated. A second input of AND gate 92 is connected to the output of NOT gate 71 . Furthermore, an output of the AND gate 92 is connected to a first input of the AND gate 91 via a NOT gate 76 . An output of the AND gate 91 is connected to a third input of the AND gate 92 via a NOT gate 75, thus forming an exclusive circuit to prevent cross conduction between the first switch 10 and the second switch 20 . Since the first signal _S1 and the second signal _S2 are disabled when the pulse signal PLS is enabled, the extension of the pulse width of the pulse signal PLS will cause the first signal _S1 and the second signal S2 to Extension of the off-time of the second signal _S2 . Inactive time is defined as the time period during which a signal is inactive. For the first range of the feedback signal V _FB , the resistor 56 determines the pulse width of the pulse signal PLS via the input terminal RD. For the second range of the feedback signal V _FB , the pulse width of the pulse signal PLS is extended in response to the decrease of the feedback signal V _FB . Therefore, the switching frequency of the first signal S ₁ and the second signal S ₂ is reduced as the output load decreases, thereby reducing the switching loss.

FIG. 6 is a circuit diagram of an oscillation circuit 200 according to an embodiment of the present invention. Wherein, the comparators 201 and 202 respectively have a trip-point voltage V _H and a trip-point voltage V _L . A negative input of the comparator 201 and a positive input of the comparator 202 are both connected to a capacitor 210 . A current source 220 charges the capacitor 210 via a switch 215 . The switch 216 is used to discharge the capacitor 210 . The NAND gates 205 and 206 form a latch circuit for generating the pulse signal PLS. The pulse signal PLS is enabled and disabled by the outputs of the comparators 201 and 202, respectively. Once the voltage of the capacitor 210 is higher than the breakpoint voltage V _H , the pulse signal PLS turns on the switch 216 to discharge the capacitor 210 . When the voltage of the capacitor 210 is lower than the breakpoint voltage V _L , the pulse signal PLS turns on the switch 215 through a NOT gate 211 to charge the capacitor 210 . Thus, the sawtooth signal RMP is generated on the capacitor 210 . A comparator 203 includes a reference voltage V _M . A negative input of comparator 203 is connected to capacitor 210 . An output of the comparator 203 generates a maximum duty cycle signal MD for determining a maximum duty cycle of the first signal _S1 . An operational amplifier 230 has a positive input supplying a reference voltage V _R1 and a negative input connected to the input terminal RD. The operational amplifier 230 and a transistor 250 together with the resistor 56 generate a current I ₂₅₀ . Transistors 251 and 252 form a first current mirror. Transistors 254 and 255 form a second current mirror. A current I ₂₅₅ passing through the transistor 255 is obtained by mirroring the current I ₂₅₀ through the first current mirror and the second current mirror. The current I ₂₅₅ is further coupled to the capacitor 210 , and the capacitor 210 is discharged by turning on the switch 216 .

A current source 235 connected to the programming terminal RP together with the resistor 57 generates a threshold voltage. The programming terminal RP is connected to an operational amplifier 231 . And the feedback terminal FB is connected to an operational amplifier 232 . The operational amplifiers 231 , 232 , a resistor 270 and a transistor 260 constitute a voltage-current converter to generate a current I ₂₆₀ . Current I ₂₆₀ can be represented by the following equation:

I ₂₆₀ =(V _TH -V _FB )/R ₂₇₀

Where V _TH represents the critical voltage value; V _TH ＝I ₂₃₅ ×R ₅₇

The current I ₂₆₀ is generated when the feedback signal V _FB is lower than the threshold voltage V _TH . The transistors 261 and 262 form a third current mirror, and the current I ₂₆₀ is mirrored by the third current mirror to generate a current I ₂₆₂ . The current I ₂₆₂ is further coupled to the transistor 255 , thereby determining a discharge current _ID of the capacitor 210 . The discharge current _ID can be given by the following equation:

I _D =I ₂₅₅ -I ₂₆₂

I _D ＝[k ₁ ×(V _R1 /R ₅₆ )]-{k ₃ ×[(I ₂₃₅ ×R ₅₇ )-V _FB ]/R ₂₇₀ }

Wherein, k ₁ and k ₃ are mirroring ratios of the first current mirror and the third current mirror respectively; R ₅₆ , R ₅₇ , R ₂₇₀ are resistance values of resistors 56 , 57 and 270 .

Therefore, for the first range of the feedback signal V _FB , the resistor 56 determines the current I ₂₅₅ and the discharge current _ID of the capacitor 210 . The resistor 57 determines the threshold, thereby determining the first range and the second range of the feedback signal V _FB . The feedback signal V _FB decreases in response to the decrease in output load. Therefore, for the second range of the feedback signal V _FB , according to the reduction of the output load, the discharge current _ID of the capacitor 210 will be reduced proportionally, so that the second delay time T _D2 will be extended proportionally.

Since the switching frequency of the first switch 10 and the second switch 20 decreases as the output load decreases, the power consumption of the power converter can be reduced under light load conditions. Furthermore, only the second delay time T _D2 is variable. The timing of the first signal S ₁ and the second signal S ₂ remains the same under light load and heavy load conditions, thus ensuring the normal operation of the soft-switching power converter.

The above are only preferred embodiments of the present utility model, and do not limit the utility model in any form. Although the utility model has been disclosed as above with preferred embodiments, it is not intended to limit the utility model. Any Those skilled in the art, without departing from the scope of the technical solution of the present utility model, can use the structure and technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all without departing from the utility model The content of the new technical solution, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present utility model still belong to the scope of the technical solution of the utility model.

Claims (15)

1. A soft-switching power converter having an energy-saving circuit for light-load operation, characterized in that the soft-switching power converter comprises: a transformer; a capacitor coupled to the transformer, the capacitor being used for soft switching; a first switch for switching the transformer, thereby transferring energy from an input of the power converter to an output of the power converter; a second switch for switching energy from said capacitor to said transformer; and a control circuit coupled to the output of the power converter whereby a first signal and a second signal are generated in response to a feedback signal for regulating the power converter the output, wherein the first signal and the second signal are used to switch the first switch and the second switch respectively; Wherein, within a first range of the feedback signal, the activation time of the second signal increases in response to the decrease of the activation time of the first signal; Before the signal is enabled, a first delay time is generated, and after the second switch is turned off and before the first signal is enabled, a second delay time is generated; wherein the second delay time is shorter than the feedback signal The second delay time is constant within a first range, and the second delay time is variable within a second range of the feedback signal, and the second delay time is proportionally increased according to a decrease of the feedback signal. 2. The soft-switching power converter according to claim 1, wherein said control circuit further comprises an input terminal for programming said first range within said first range of said feedback signal 2. Delay time. 3. The soft switching power converter of claim 2, wherein a resistor is coupled from said input terminal of said control circuit to a ground reference, thereby programming said second delay. 4. The soft-switching power converter according to claim 1, wherein the control circuit further comprises a threshold, which is used to define the first range of the feedback signal or the second range. 5. The soft-switching power converter according to claim 4, wherein said control circuit further comprises a programming terminal for programming said threshold. 6. The soft switching power converter of claim 5, wherein a resistor is coupled from said programming terminal of said control circuit to a ground reference, thereby programming said threshold. 7. A soft switching power supply, characterized in that the soft switching power supply includes: a transformer; a capacitor coupled to the transformer, the capacitor being used for soft switching; a first switch for switching the transformer, thereby transferring energy from an input of the power supply to an output of the power supply; a second switch for switching energy from said capacitor to said transformer; and a controller coupled to the output of the power supply whereby responsive to a feedback signal generates a first signal and a second signal for regulating the power supply the output of , wherein the first signal and the second signal switch the first switch and the second switch, respectively; Wherein, a first delay time is generated after the first switch is turned off and before the second signal is enabled, and a second delay time is generated after the second switch is turned off and before the first signal is enabled. The delay time, and the second delay time is variable within a second range of the feedback signal, wherein the second delay time increases proportionally according to the decrease of the feedback signal. 8. The soft-switching power supply as claimed in claim 7, wherein said controller further comprises an input terminal for programming said second delay time within a first range of said feedback signal. 9. The soft-switching power supply of claim 8, wherein a resistor is coupled from the input terminal of the controller to a ground reference, thereby programming the second delay time. 10. The soft-switching power supply according to claim 7, wherein the controller further comprises a threshold for defining a first range of the feedback signal or the first range of the feedback signal Two ranges. 11. The soft-switching power supply according to claim 10, wherein said controller further comprises a programming terminal for programming said threshold. 12. A soft-switching regulator, characterized in that the soft-switching regulator includes: a magnetic device; a capacitor coupled to the magnetic device, the capacitor being used for soft switching; a first switch for switching said magnetic device, thereby transferring energy from an input of said regulator to an output of said regulator; a second switch for switching energy from the capacitor to the magnetic device; and a circuit coupled to the output of the regulator, thereby generating a first signal and a second signal for switching the first switch and the second switch, respectively two switches, wherein said first signal includes a duty cycle for regulating said output of said regulator; Wherein, a first delay time is generated after the first switch is turned off and before the second signal is enabled, and a second delay time is generated after the second switch is turned off and before the first signal is enabled. The delay time, and the second delay time is variable within a second range of the duty cycle, wherein the second delay time increases proportionally according to the decrease of the duty cycle. 13. The soft-switching regulator of claim 12, wherein said circuit further comprises an input terminal for programming said second delay time within a first range of said duty cycle. 14. The soft switching regulator according to claim 13, wherein said circuit further comprises a threshold for defining said first range of said duty cycle or said second range of said duty cycle . 15. The soft-switching regulator according to claim 14, wherein said circuit further comprises a programming terminal for programming said threshold.

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