Data collecting card based on USB2.0
One, technical field
The utility model relates to a kind of data collecting card, particularly based on the USB2.0 interface, and single channel or twin-channel, data collecting card at a high speed.Be used for high speed acquisition one road or two-way simulating signal.
Two, technical background
In the every profession and trade of commercial production and scientific and technical research, often utilize PC or industrial computer to various data, gather as pressure, frequency, liquid level, temperature etc.Acquisition mode commonly used now is to pass through data collecting plate card.Before USB produced, integrated circuit board and communicating by letter of PC mainly were that the various interface by the PC mainboard provides realizes, as ISA, PCI, PS/2, serial line interface, parallel interface etc.Early stage design proposes these old-fashioned interfaces in the eighties in 20th century by IBM Corporation at first, has a lot of defectives, as dismounting capture card inconvenience, and all needs to restart computing machine after each the installation, needs external power supply etc.
The present domestic data acquisition equipment that independent research also occurred based on USB, but, the requirement that these do not satisfy the data high-speed transmission based on the data acquisition and the transmission equipment of USB1.1 agreement, so transmission speed has become the bottleneck of high-speed data acquisition and data processing.And it is also fewer based on the utility device of the data acquisition of USB2.0 agreement and transmission.Therefore, develop data acquisition and transmission equipment based on USB2.0.
Three, utility model content
At the deficiencies in the prior art, a kind of data collecting card based on USB2.0 is proposed, it can overcome the shortcoming of prior art, and realization hot plug, bus power source are powered separately; And can carry out high-speed data acquisition, volume is little, and is in light weight; And can satisfy the demand of scene, real-time data acquisition.
The technical solution of the utility model is as follows: comprise data transmission module, analog-to-digital conversion module and power transfer module three parts.Concrete composition is: PC is connected in the USB controller of data transmission module by USB cable, the USB controller of data transmission module links to each other with analog-to-digital conversion module by its general programmable interface, and the output of power transfer module is connected to USB controller and modular converter.Described data transmission module comprises that the USB2.0 controller chip is connected in crystal oscillator by respective pins respectively, reset circuit and Remote Wake Up circuit and pull-up resistor and pull down resistor.Described analog-to-digital conversion module comprises two modulus conversion chips that connect by parallel mode, and two modulus conversion chips are connected to and the door chip; Described power transfer module is become+the 2.5V power supply with MAX882 general+5V power source conversion by three power conversion chip MX580, LTC1261L ,-2.5V power supply ,-5V power supply and+the 3.3V power supply.
The utility model is because the interface chip CY7C68013 that is based on the USB2.0 agreement that adopts, support to communicate by letter at a high speed with at full speed, chip internal is integrated GPIF (general programmable interface), in data acquisition and transmission course, do not need the intervention of CPU, effectively raise data rate, therefore its transmission speed is fit to the occasion of needs high-speed data acquisition far above the data collecting card based on the USB1.1 agreement.Saved external single-chip microcomputer, SIE (serial interface engine), the trouble of storer makes the total system interface simple, compact conformation, the reliability height, adaptability is strong.
Four, description of drawings
Fig. 1 is the structured flowchart based on the data collecting card of USB2.0.
Designation among Fig. 1: SIE-serial interface engine; The GPIF-general programmable interface
Fig. 2 is the data transmission module circuit theory diagrams.
Designation among Fig. 2: U1-USB2.0 controller chip; The Type B socket of J1-USB
Fig. 3 is the analog-to-digital conversion module circuit theory diagrams.
Designation among Fig. 3: U3, U4-modulus conversion chip; U5-and door chip
Fig. 4 is the power transfer module circuit theory diagrams.
Fig. 5 is a GPIF mode software process flow diagram.
Five, specific embodiments
Further specify concrete enforcement of the present utility model below in conjunction with accompanying drawing.
Fig. 1 is a structured flowchart of the present utility model.Concrete formation is: PC is connected in the USB controller of data transmission module by USB cable, the USB controller of data transmission module links to each other with analog-to-digital conversion module ADC by its general programmable peripheral interface, and the output of power transfer module is connected to USB controller and modular converter.Described USB controller chip has adopted the USB2.0 transceiver integrated, serial interface engine (SerialInterface Engine, be called for short SIE), low-power consumption, enhancement mode 8051 controllers, with a general programmable peripheral interface (General Programmable Peripheral Interface, be called for short GPIF), and the USB2.0 controller chip with program/data RAM; Said modulus conversion chip links to each other with the GPIF interface of USB2.0 controller by parallel connected mode; Said power conversion chip uses special-purpose power conversion chip.Its workflow is as follows: the two-way simulating signal 1 and 2 after conditioning is converted to digital signal through the two-way analog to digital converter respectively, to its internal buffer, whether whether the decision of full scale will transfers data to computing machine according to buffer zone by program by the data after the USB controller collection conversion.After powering on, system discerns driver automatically, and the firmware program of USB controller downloads among its internal processes RAM automatically by USB interface, and starts working after enumerating through twice, and computing machine can be obtained the various configuration informations of system by user software.The USB controller carries out data acquisition and transmission with GPIF Master pattern, and controls the sequential of digital to analog converter collection and reading of data by ' oscillogram '.
Fig. 2 is data transmission circuit module principle figure.This data transmission circuit comprises that the USB2.0 controller chip is connected in crystal oscillator by respective pins respectively, reset circuit and Remote Wake Up circuit and pull-up resistor and pull down resistor.U1 among the figure is the USB2.0 controller chip, employing be the FX2 series USB2.0 controller chip CY7C68013 of CYPRESS company.Because system adopts the mode from main frame download firmware program,, connect pull-up resistor R4 and the R5 of one 2.2 Ω respectively so its SCL and SDA pin are idle.Adopt parallel data communication mode (to call CY7C68013 chip and ADC chip in the following text) between USB2.0 controller chip CY7C68013 and the modulus conversion chip ADC, its data line FD[0: 15] most-significant byte link to each other with the data line of two ADC respectively with least-significant byte, by being programmed for the GPIF pattern, the FD[0 that at every turn reads: 15] 16 bit data, by program separately, be the data of every road ADC high low byte.The XTALIN of CY7C68013 chip and XTALOUT pin are the input and output pin of crystal oscillator, link to each other with the crystal oscillator of a 24MHz, the running clock that produces 480MHz by the inner phaselocked loop of controller (PLL) uses for transceiver, and is the clock of 12MHz as the enhancement mode 8051 of embedding by the internal counter frequency division.The RESET of CY7C68013 chip is a reset pin, is connected to by 100K Ω resistance, 1.0 μ F electric capacity and the reset circuit that switch is formed; The WAKEUP pin of CY7C68013 chip is the Remote Wake Up pin, is connected to a Remote Wake Up circuit same with reset circuit.In addition, the RDY0 of CY7C68013 chip, CTL0 must link to each other with the respective pins of ADC with CTL1, with the collection of control signal and reading of data.The interface clock signal IFCLK of CY7C68013 chip links to each other with ground with R6 by pull down resistor R3 respectively with reservation pin RESERVED.
USB-B among Fig. 2 is the Type B socket of USB, links to each other with main frame by the USB connecting line.The DMINUS of CY7C68013 and DPLUS pin are realized and the communicating by letter of main frame by linking to each other with D-with the D+ of Type B socket.Be the power lead of drawing, as the power supply of total system from main frame.
Fig. 3 is the analog-to-digital conversion module circuit theory diagrams.This analog-to-digital conversion module comprises modulus conversion chip U3 and the U4 that two parallel schemas connect, and two ADC chip U3, U4 are connected to a slice and form with door chip U5.That the ADC chip adopts is the AD7821 of ANALOG company.The MODE pin of AD7821 connects high level to be configured to the WR-RD pattern.The pin WR of ADC, RD link to each other with CTL1 with the CTL0 of CY7C68013 chip respectively, and control it to the collection of signal and reading of data by firmware program.With door chip U5 be 74LS08, the INT pin of two ADC chips produces read data control signal READY respectively through carrying out logic and operation with door chip U5.ADC needs ± and the 2.5V reference voltage is connected with the corresponding power supply of power module respectively with-5V power supply.
Fig. 4 is the power transfer module circuit theory diagrams.This module is by-5V power supply, ± 2.5V reference voltage, and+3.3V power supply three parts form.This system uses bus power source power supply, does not need additional power source, therefore with regard to the system power supply that needs handle+5V be converted to system required-the 5V power supply, ± 2.5V reference voltage, and CY7C68013 required+power supply of 3.3V.U2, U6A are respectively the MAX882 and the MX580 chip of MAXIM company, and U7 is the LTC1261L chip of LINEAR company, and phase inverter (and follower of being organized) UB1 is the LM358 chip of National Semiconductor company.Power source conversion by MX580 chip handle+5V is+2.5V, and follows output by the follower that LM358 forms; The power supply of resulting+2.5V is converted to-2.5V by the phase inverter that LM358 forms again, finally obtain ± the 2.5V reference voltage uses for the ADC chip.By chip LTC1261L, the power source conversion of the circuit handle+5V that shunt capacitance and pot are formed offers the ADC chip for-5V power supply, and pot R8 is in order to finely tune.Power source conversion by chip MAX882 handle+5V is+3.3V uses for chip CY7C68013, and all connect a bypass electric capacity near power supply at each power input of CY7C68013, make power supply more stable.
Fig. 5 is the firmware program process flow diagram.After program begins, at first to carry out the initialization of register, buffer zone and GPIF oscillogram.Initialization finishes, start the ADC chip and begin data acquisition, wait for analog-to-digital end signal then, behind the EOC, read digital signal in buffer zone, judge whether full scale will of buffer zone then here, if it is full, then begin to transmit data, otherwise, proceed above data acquisition.DTD continues to call time gatherer process by principal function, until this data acquisition of host computer control finishes.