CN2836373Y

CN2836373Y - Phase lock loop for TV frequency modulation circuit

Info

Publication number: CN2836373Y
Application number: CN 200520134080
Authority: CN
Inventors: 唐守龙; 宋莹莹; 吴烜; 吴建辉; 陆生礼; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2006-11-08
Anticipated expiration: 2015-12-08

Abstract

The utility model discloses a phase-locked loop used in a television frequency modulation circuit. It relates to a three-band digital TV tuner circuit, especially its internal phase-locked loop circuit and its band switching circuit. It is used to eliminate the abnormal oscillation frequency that may be generated by the voltage-controlled oscillator circuit when the band is switched, so that the phase-locked loop circuit can be normally locked at the specified frequency. The tuning voltage signal output by the active filter is controlled by a voltage-to-current conversion circuit and a tuning voltage boosting circuit used in a phase-locked loop of a TV frequency modulation circuit. At the moment of band switching, the tuning voltage rises to the maximum value, the oscillator oscillates normally, and then the oscillation frequency of the oscillator is controlled by the output of the phase-locked loop circuit. The circuit structure is simple, the circuit scale is small, and the chip is easy to integrate.

Description

The phase-locked loop that is used for the TV FM circuit

Technical field

The utility model relates to a kind of triband Digital Television tuning circuit, relates in particular to the phase-locked loop in a kind of triband Digital Television tuning circuit.

Background technology

The monotropic frequency tuning circuit of the tuning reception of triband becomes the main circuit form of present Digital Television tuning circuit with advantages such as its cost are low, low in energy consumption.Circuit as shown in Figure 1, the triband tuning circuit comprises VHFL, the frequency mixer (101 of VHFH and three wave bands of UHF, 102,103) and voltage controlled oscillator (201,202,203), also comprise a phase-locked loop circuit 300 that is used for frequency lock and channel conversion, at present the triband tuning chip is integrated all circuit of triband frequency mixer, the active circuit part of voltage controlled oscillator and the low-voltage circuit part in the phase-locked loop circuit, the low-voltage circuit of phase-locked loop circuit partly comprises the circuit under all 3.3V work, have: frequency divider, phase discriminator, charge pump and crystal oscillator drive circuit etc., the oscillation circuit (501 of voltage controlled oscillator, 502, the oscillator of 503 respectively corresponding three wave bands) constitutes by the inductance and the varicap that separate, can obtain different frequencies of oscillation by the biasing voltage signal VT that changes on the varicap, thereby can receive different TV signal, the biasing voltage signal VT on the varicap is produced to the active filter with boost function of 33V by phase-locked loop circuit and 3.3V.

In the prior art, because oscillation circuit 501,502, the 503 shared same tuning voltage signal VT of three wave bands, and the effective working region of the varicap difference in three wave band oscillation circuits, therefore, when the tuning receiving circuit of triband carries out the wave band switching, tend to cause pierce circuit to produce abnormal frequency of oscillation, make that phase-locked loop circuit can't operate as normal, correct local oscillation signal frequency can not be provided, thereby cause tuner can't receive the TV channel signal of appointment.

Summary of the invention

The purpose of this utility model is to overcome the deficiency of prior art, and the issuable lopsided frequency of oscillation of voltage-controlled oscillator circuit makes phase-locked loop circuit normally be locked in the metal oxide semiconductor phaselocked loop circuit of assigned frequency when providing a kind of elimination wave band to switch.

Above-mentioned purpose of the present utility model is realized by following technical scheme:

A kind of phase-locked loop that is used for the TV FM circuit, comprise buffer circuit 301, frequency divider 302, phase discriminator 303, crystal oscillator drive circuit 304, parametric frequency divider 305, charge pump 306, the outer quartz crystal 600 of sheet, the outer active filter 400 of sheet, buffer circuit 301 is three commentaries on classics, one buffer circuits, three tunnel difference inputs is respectively from the output of three oscillators, buffer circuit 301 outputs connect the input of frequency divider 302, frequency divider 302 outputs connect the input of phase discriminator 303, the output of parametric frequency divider 305 connects another input of phase discriminator 303, the output of phase discriminator 303 connects the input of charge pump 306, the outer quartz crystal 600 of crystal oscillator drive circuit 304 braces, crystal oscillator drive circuit 304 outputs connect the input of parametric frequency divider 305, the output contact pin of charge pump 306 is an input of active filter 400 outward, and the outer active filter 400 of sheet is discharged and recharged; Charge pump 306 outputs are also connected to the input of current converter circuit 307, the output of current converter circuit 307 is connected to the offset side of triode in the described outer active filter 400 and the output that tuning voltage promotes circuit 308, voltage produces outside the sheets bias current of triode in the active filter 400 to current converter circuit 307 output, make charge pump 306 output signals through voltage produce to current converter circuit 307 conversion with sheet outside the tuning voltage signal (VT) exported of active filter 400 corresponding one by one, tuning voltage promotes the interior digital signal that produces the height change in voltage of input chip termination of circuit 308, tuning voltage promotes and to make under circuit 307 outputs produce the height change in voltage in chip the Digital Signals outside the sheet that triode ends or operate as normal in the active filter 400, when ending, tuning voltage signal (VT) rises to the power end magnitude of voltage of the outer active filter 400 of sheet, during operate as normal, tuning voltage signal (VT) value depends on the control of voltage to current converter circuit 307 outputs.Described voltage is managed M1 to current converter circuit 307 by six NMOS, M2, M5, M6, M10, M11 and five PMOS pipe M3, M4, M7, M8, reference current source IREF forms in M9 and the chip, first, second, third and fourth NMOS manages M1, M2, M5, the source end ground connection of M6, the grid end of the one NMOS pipe M1, the drain terminal of the one NMOS pipe M1, reference current source IREF links to each other with the grid end of the 2nd NMOS pipe M2 in the sheet, first, second, the 3rd PMOS manages M3, M4, the drain terminal of the grid end of M9 and PMOS pipe M3 and the drain terminal of the 2nd NMOS pipe M2 link to each other, first, second, the the 4th and the 5th PMOS manages M3, M4, M7, the source termination power of M8, the drain terminal of the 2nd PMOS pipe M4, the drain terminal of the 3rd NMOS pipe M5, the grid end of the 3rd NMOS pipe M5 links to each other with the grid end of the 4th NMOS pipe M6, the drain terminal of the 4th NMOS pipe M6, the source end of the 5th NMOS pipe M1O links to each other with the source end of the 6th NMOS pipe M11, the drain terminal of the 5th NMOS pipe M10, the drain terminal of the 3rd PMOS pipe M9, the grid end of the 4th PMOS pipe M7 links to each other with the grid end of the 5th PMOS pipe M8, the source end of the 3rd PMOS pipe M9 links to each other with the drain terminal of the 4th PMOS pipe M7, the drain terminal of the 6th NMOS pipe M11, the grid end of the 6th NMOS pipe M11 links to each other with the drain terminal of the 5th PMOS pipe M8, the grid end of the 5th NMOS pipe M10 is connected to the output of charge pump 306, and the grid end of the 6th NMOS pipe M11 is the output of voltage to current converter circuit 307; Reference current source IREF provides bias current for voltage to current converter circuit 307 in the chip, the one NMOS pipe M1 and the 2nd NMOS pipe M2, PMOS pipe M3 and the 2nd PMOS pipe M4, the 3rd NMOS pipe M5 and the 4th NMOS pipe M6 constitute current mirroring circuit respectively, the one NMOS pipe M1 grid leak end short circuit reference current source IREF end in chip forms active load, and the 4th PMOS pipe M7, the 5th PMOS pipe M8, the 3rd PMOS pipe M9, the 5th NMOS pipe M10 and the 6th NMOS pipe M11 constitute the operational amplifier of telescopic cascodes; Described tuning voltage promotes circuit 308 by three NMOS pipe MN1, MN2, M12 and two PMOS pipe MP1, MP2 forms, the digital signal that produces the height change in voltage in the chip connects the input that tuning voltage promotes circuit 308, the one PMOS pipe MP1 links to each other with the grid end of NMOS pipe MN1, promote the input of circuit 308 as tuning voltage, the drain terminal of the one PMOS pipe MP1, the drain terminal of the one NMOS pipe MN1, the grid end of the 2nd PMOS pipe MP2 links to each other with the grid end of the 2nd NMOS pipe MN2, the drain terminal of the 2nd PMOS pipe MP2, the drain terminal of the 2nd NMOS pipe MN2 links to each other with the grid end of the 3rd NMOS pipe M12, the drain terminal of the 3rd NMOS pipe M12 connects the output of voltage to current converter circuit 307, the source end of the one NMOS pipe MN1, the source end ground connection of the source end of the 2nd NMOS pipe MN2 and the 3rd NMOS pipe M12, the source termination power of the source end of the one PMOS pipe MP1 and the 2nd PMOS pipe MP2, PMOS pipe MP1 and NMOS pipe MN1, the 2nd PMOS pipe MP and the 2nd NMOS pipe MN2 constitute the two-stage MOS inverter.

Described outer active filter 400 is made up of a NPN transistor and resistance capacitance, the grounded emitter of NPN transistor Q1, base stage connects voltage promotes circuit 308 to current converter circuit 307 and tuning voltage tie point through a resistance R 1, collector electrode divides through a resistance R 3 connect power supply at three the tunnel: the one tunnel, one the tunnel through a resistance R 4 output tuning voltage signal VT, one the tunnel through one the series connection branch road link to each other with the output of charge pump 306, this series arm is in series with a capacitor C 1 by a capacitor C 2 and resistance R 2 backs in parallel and forms, the phase-locked loop circuit supply voltage of low voltage power supply is 3.3V, and the supply voltage of the outer active filter 400 of the sheet of High Voltage Power Supply is 33V.

Advantage of the present utility model and effect provide a kind of phase-locked loop circuit of eliminating lopsided frequency of oscillation.The utility model adopts voltage issuable abnormal frequency of oscillator when current converter circuit 307 and tuning voltage promote that circuit 308 is common eliminates the wave bands switching on the basis of general phase-locked loop circuit.When wave band switches, tuning voltage promotes and to make under circuit 307 outputs produce change in voltage just in chip the Digital Signals outside the sheet that triode ends in the active filter 400, tuning voltage signal VT rises to the power end magnitude of voltage of the outer active filter 400 of sheet, oscillator normally vibrates, after the operate as normal, control signal in the chip is cancelled, and tuning voltage signal VT value depends on the control of voltage to current converter circuit 307 outputs.Realize the phase-locked loop circuit operate as normal, lock required Frequency point.

The utility model adopts the simple circuit configuration form, the lopsided frequency of oscillation that may cause in the time of can effectively eliminating the wave band switching in the tuning receiving circuit of triband Digital Television, this circuit does not influence tuner wave band switching time, but quick lock in preset frequency point carries out tuning channel selection in the wave band handoff procedure.Simultaneously, the circuit that the utility model proposes have small scale, circuit simple, be easy to advantages such as chip is integrated.

Description of drawings

Fig. 1 is a triband Digital Television tuning circuit block diagram of the present utility model.

Fig. 2 is a phase-locked loop circuit block diagram of the present utility model.

Fig. 3 is that voltage of the present utility model promotes circuit diagram to current converter circuit and tuning voltage.

Fig. 4 is buffer circuit figure of the present utility model.

Fig. 5 is divider circuit figure of the present utility model.

Fig. 6 is phase detector circuit figure of the present utility model.

Fig. 7 is crystal oscillator drive circuit figure of the present utility model.

Fig. 8 is a parametric frequency divider circuit diagram of the present utility model.

Fig. 9 is charge pump circuit figure of the present utility model.

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail.

As shown in Figure 2, the phase-locked loop circuit among Fig. 2 comprises that buffer circuit 301, frequency divider 302, phase discriminator 303, crystal oscillator drive circuit 304, parametric frequency divider 305, charge pump 306, voltage promote circuit 308 to current converter circuit 307, tuning voltage.Buffer circuit 301 is general three commentaries on classics, one buffer circuit, three road

differential input ends

1,2,3,4,5,6 are respectively from the output of oscillator 201,202,203, output 7,8 is delivered to the input of frequency divider 302, carries out frequency division as the input of frequency divider 302.Three pairs of inputs in the buffer circuit 301 once have only a pair of input that signal is arranged, the invalidating signal on other two pairs of inputs.Frequency divider 302 carries out frequency division according to certain frequency dividing ratio to the signal on the input 7,8,

output

9,10 connects the input of phase discriminator 303, for finishing phase discrimination function, phase discriminator 303 also needs to link to each other with the

output

13,14 of parametric frequency divider 305, the

output

15,16 of phase discriminator 303 connects the input of charge pump 306, and charge pump 306 discharges and recharges.The outer quartz crystal 600 of crystal oscillator drive circuit 304 driving chips, produce reference frequency signal accurately on the

output

11,12, the

output

11,12 of the input termination crystal oscillator drive circuit 304 of parametric frequency divider 305, and the signal on its input carried out frequency division, so that phase discriminator carries out phase demodulation.The

output

15,16 of charge pump 306 input termination phase discriminators 303, an input of the outer active filter 400 of output 17 contact pin of charge pump 306, and the outer active filter 400 of sheet discharged and recharged, simultaneously in order to realize the voltage transitions of 3.3V to 33V, adopt a voltage to current converter circuit: voltage produces outside the sheets bias current of triode Q1 in the active filter 400 to current converter circuit 307, it is corresponding one by one with the tuning voltage signal VT that the outer active filter 400 of sheet produces to make charge pump defeated 306 go out signal, realizes boost function.Voltage is to the output 17 of current converter circuit 307 input termination charge pumps 306, another input of the outer active filter 400 of output 18 contact pin.

Buffer circuit 301 in the phase-locked loop circuit, frequency divider 302, phase discriminator 303, crystal oscillator drive circuit 304, parametric frequency divider 305, charge pump 306 all are the circuit execution modes that adopts traditional classical, and the physical circuit implementation is respectively shown in Fig. 4,5,6,7,8,9.

It is control circuits that tuning voltage promotes circuit 308, its input 19 connects chip system and produces the digital control circuit output that height changes, tuning voltage promotes the output 18 of circuit 308 output termination voltages to current converter circuit 307, under the control of control signal on the input 19, tuning voltage promotes circuit 308 can change the operation level of voltage to current converter circuit 307 outputs 18, and whether triode Q1 works in the outer active filter 400 of control strip then.When triode Q1 ended, tuning voltage signal VT can rapidly increase to 33V, and variable capacitance diode all can normally vibrate at ceiling voltage 33V place in the oscillator tuning loop 501,502 and 503, can not produce abnormal frequency, and just frequency of oscillation is lower than predeterminated frequency.When triode Q1 operate as normal, phase-locked loop circuit 300 can change tuning voltage signal VT fast, makes the oscillator vibration at the assigned frequency point.

The utility model adopts voltage issuable abnormal frequency of oscillator when current converter circuit 307 and tuning voltage promote that circuit 308 is common eliminates the wave bands switching on the basis of general phase-locked loop circuit.When wave band switches, by the control signal on system's generation tuning voltage lifting circuit 308 inputs 19, triode Q1 in the outer active filter 400 of sheet is ended, tuning voltage signal VT rises to 33V, oscillator normally vibrates, system cancels the control signal on tuning voltage lifting circuit 308 inputs 19 more then, and phase-locked loop circuit 300 operate as normal lock required Frequency point.

Voltage promotes circuit 308 as shown in Figure 3 to current converter circuit 307 and tuning voltage.IREF is the reference source circuit output that produces the reference current signal in the chip, and the current signal on the IREF end is responsible for voltage and provides bias current to current converter circuit 307.NMOS pipe M1 and NMOS pipe M2, PMOS pipe M3 and PMOS pipe M4, NMOS pipe M5 and NMOS pipe M6 constitute current mirroring circuit respectively.NMOS pipe M1 grid leak short circuit IREF end forms active load, source termination earth potential.NMOS pipe M2 grid termination IREF end, drain terminal connects the drain terminal of PMOS pipe M3, NMOS pipe M2 source end ground connection.The grid leak end short circuit of PMOS pipe M3, the source termination power.The grid end of PMOS pipe M4 grid termination PMOS pipe M3, drain terminal connects the grid leak shorted end of NMOS pipe M5, source termination power.The fixed potential that the PMOS pipe M3 of grid leak short circuit forms provides offset signal for PMOS pipe M9 grid end, and PMOS pipe M9 grid end links to each other with PMOS pipe M3 grid end, PMOS pipe M4 grid end.NMOS pipe M5 and NMOS pipe M6 constitute the NMOS current mirror, and NMOS manages M5 grid leak end short circuit, the grid leak end of NMOS pipe M6 grid termination NMOS pipe M5, and the drain-source current that NMOS pipe M6 produces manages M10 for NMOS and NMOS pipe M11 provides bias current.PMOS pipe M7, PMOS pipe M8, PMOS pipe M9, NMOS pipe M10 and NMOS pipe M11 constitute the amplifier of telescopic cascodes, telescopic cascade amplifier has the speed height, power consumption, the characteristics that noise is low, its gain and output voltage swing are moderate, for improving its output voltage swing, taked the asymmetric form of output simultaneously.The grid end of PMOS pipe M7, PMOS pipe M8 links to each other with the drain terminal of PMOS pipe M9, the drain terminal of PMOS pipe M7 links to each other with the source end of PMOS pipe M9, the source end of NMOS pipe M10 and NMOS pipe M11 is connected to the drain terminal of NMOS pipe M6, the grid end of the grid end of the drain terminal of the drain terminal of NMOS pipe M10 and PMOS pipe M9, PMOS pipe M7, PMOS pipe M8 connects together, and the grid end of NMOS pipe M10 is the output 17 of charge pump 306.NMOS manages the grid leak short circuit of M11 and links to each other resistance R 1 one ends in the outer active filter 400 of output 18 contact pin simultaneously with the drain terminal of PMOS pipe M8.The input 19 that tuning voltage promotes circuit 308 connects the grid end that PMOS manages MP1 and NMOS pipe MN1, the grid end of PMOS pipe MP1 and NMOS pipe MN1 links to each other respectively with drain terminal and constitutes MOS inverter, in like manner, PMOS manages MP2, the grid end of NMOS pipe MN2 links to each other respectively with drain terminal and constitutes MOS inverter, PMOS manages MP1 simultaneously, the drain terminal output of NMOS pipe MN1 meets PMOS pipe MP2, the grid end input of NMOS pipe MN2, PMOS manages MP2, the drain terminal output of NMOS pipe MN2 connects the grid end of NMOS pipe M12, the drain terminal of NMOS pipe M12 connects the output 18 of voltage to current converter circuit 307, PMOS manages MP1, NMOS manages MN1, PMOS pipe MP2 and NMOS pipe MN2 constitute the two-stage MOS inverter, improve the driving force of control signal on the input 19.When control signal was high level on the input 19, NMOS pipe M12 opened, and voltage signal to the output 18 of current converter circuit 307 is an earth potential, and the triode Q1 in the outer active filter 400 of sheet ends, and tuning voltage signal VT rises to 33V rapidly; When control signal was low level on the input 19, NMOS pipe M12 turn-offed phase-locked loop circuit 300 operate as normal.

Claims

1. A phase-locked loop for a TV FM circuit, comprising a buffer circuit (301), a frequency divider (302), a phase detector (303), a crystal oscillator drive circuit (304), a reference frequency divider (305), A charge pump (306), an off-chip quartz crystal (600), an off-chip active filter (400), and a buffer circuit (301) are three-turn-one-buffer circuits, and the three differential inputs come from the output terminals of the three oscillators respectively. The output of the buffer circuit (301) is connected to the input of the frequency divider (302), the output of the frequency divider (302) is connected to the input of the phase detector (303), and the output of the reference frequency divider (305) is connected to the phase detector The other input end of (303), the output end of phase detector (303) connects the input end of charge pump (306), and crystal oscillator drive circuit (304) connects off-chip quartz crystal (600), and crystal oscillator drive circuit (304) outputs terminal is connected to the input terminal of the reference frequency divider (305), and the output terminal of the charge pump (306) is connected to an input terminal of the off-chip active filter (400), and the off-chip active filter (400) is charged and discharged ;

It is characterized in that the output end of the charge pump (306) is also connected to the input end of the current conversion circuit (307), and the output end of the current conversion circuit (307) is connected to the off-chip active filter (400) The bias terminal of the triode and the output terminal of the tuning voltage boosting circuit (308), the output of the voltage to the current conversion circuit (307) generates the bias current of the triode in the off-chip active filter (400), so that the charge pump (306) outputs The signal is converted by the voltage-to-current conversion circuit (307) to generate a one-to-one correspondence with the tuning voltage signal (VT) output by the off-chip active filter (400), and the input terminal of the tuning voltage boosting circuit (308) is connected to the chip to generate high and low voltages Changing digital signal, the output terminal of the tuning voltage boosting circuit (307) makes the triode in the off-chip active filter (400) cut off or work normally under the control of the digital signal that generates high and low voltage changes in the chip. When it is cut off, the tuning voltage signal ( VT) rises to the power supply terminal voltage value of the off-chip active filter (400). During normal operation, the value of the tuning voltage signal (VT) depends on the control of the output of the voltage-to-current conversion circuit (307).

2. The phase-locked loop for TV FM circuit according to claim 1, characterized in that: said voltage-to-current conversion circuit (307) consists of six NMOS tubes (M1, M2, M5, M6, M10, M11) and five PMOS transistors (M3, M4, M7, M8, M9) and on-chip reference current source (IREF), the first, second, third and fourth NMOS transistors (M1, M2, M5, M6 ) source terminal is grounded, the gate terminal of the first NMOS transistor (M1), the drain terminal of the first NMOS transistor (M1), the on-chip reference current source (IREF) and the gate terminal of the second NMOS transistor (M2) are connected. 1. The gate ends of the second and third PMOS transistors (M3, M4, M9) are connected to the drain end of the first PMOS transistor (M3) and the drain end of the second NMOS transistor (M2). The source terminals of the fourth and fifth PMOS transistors (M3, M4, M7, M8) are connected to the power supply, the drain end of the second PMOS transistor (M4), the drain end of the third NMOS transistor (M5), and the third NMOS transistor (M5) The gate terminal of the gate is connected to the gate terminal of the fourth NMOS transistor (M6), the drain terminal of the fourth NMOS transistor (M6), the source terminal of the fifth NMOS transistor (M10) are connected to the source terminal of the sixth NMOS transistor (M11), The drain end of the fifth NMOS transistor (M10), the drain end of the third PMOS transistor (M9), the grid end of the fourth PMOS transistor (M7) are connected to the grid end of the fifth PMOS transistor (M8), and the third PMOS transistor ( The source end of M9) is connected to the drain end of the fourth PMOS transistor (M7), the drain end of the sixth NMOS transistor (M11), the gate end of the sixth NMOS transistor (M11) and the drain end of the fifth PMOS transistor (M8) connected, the grid end of the fifth NMOS transistor (M10) is connected to the output end of the charge pump (306), and the grid end of the sixth NMOS transistor (M11) is the output end of the voltage-to-current conversion circuit (307);

The on-chip reference current source (IREF) provides bias current for the voltage-to-current conversion circuit (307), the first NMOS transistor (M1) and the second NMOS transistor (M2), the first PMOS transistor (M3) and the second PMOS transistor (M4), the third NMOS transistor (M5) and the fourth NMOS transistor (M6) respectively constitute a current mirror circuit, and the gate and drain terminals of the first NMOS transistor (M1) are short-circuited to the on-chip reference current source (IREF) terminal to form an active Load, the fourth PMOS transistor (M7), the fifth PMOS transistor (M8), the third PMOS transistor (M9), the fifth NMOS transistor (M10) and the sixth NMOS transistor (M11) constitute a telescopic cascode structure the operational amplifier;

The tuning voltage boosting circuit (308) is composed of three NMOS tubes (MN1, MN2, M12) and two PMOS tubes (MP1, MP2), and the digital signals that generate high and low voltage changes in the chip are connected to the tuning voltage boosting circuit (308 ), the first PMOS transistor (MP1) is connected to the grid end of the first NMOS transistor (MN1), as the input end of the tuning voltage boosting circuit (308), the drain end of the first PMOS transistor (MP1), the first The drain end of the NMOS transistor (MN1), the gate end of the second PMOS transistor (MP2) are connected to the gate end of the second NMOS transistor (MN2), the drain end of the second PMOS transistor (MP2), the second NMOS transistor (MN2) The drain end of the third NMOS transistor (M12) is connected to the gate end of the third NMOS transistor (M12), the drain end of the third NMOS transistor (M12) is connected to the output end of the voltage-to-current conversion circuit (307), the source end of the first NMOS transistor (MN1), The source terminal of the second NMOS transistor (MN2) and the source terminal of the third NMOS transistor (M12) are grounded, the source terminal of the first PMOS transistor (MP1) and the source terminal of the second PMOS transistor (MP2) are connected to the power supply, and the first PMOS The transistor (MP1) and the first NMOS transistor (MN1), the second PMOS transistor (MP2) and the second NMOS transistor (MN2) form a two-stage metal oxide semiconductor inverter.

3. The phase-locked loop for TV FM circuit according to claim 1 or 2, characterized in that said off-chip active filter (400) is composed of an NPN transistor and a resistor and capacitor, and the NPN transistor (Q1) The emitter is grounded, the base connects the voltage to the connection point of the current conversion circuit (307) and the tuning voltage boosting circuit (308) through a resistor (R1), and the collector is divided into three circuits: one path is connected to the power supply through a resistor (R3), One way outputs the tuning voltage signal (VT) through a resistor (R4), and one way is connected to the output of the charge pump (306) through a series branch, and the series branch is connected in parallel with a capacitor (C2) and a resistor (R2) to a Capacitors (C1) are connected in series, the power supply voltage of the PLL circuit powered by low voltage is 3.3V, and the power supply voltage of the off-chip active filter (400) powered by high voltage is 33V.