CN2774029Y - Easily-extended embedded network terminal - Google Patents

Abstract

The utility model discloses an easily-extended embedded network terminal which comprises a base board module and an extension board module, wherein the base board module and the extension board module are connected by a bus; the base board module is the smallest system and comprises a CPU, a memory unit, power supply and a drive circuit. The extension board module is provided with a function extension unit. The function extension unit is an ethernet interface unit. On the basis of the smallest system, the embedded network terminal can carry out function extension through the extension unit so as to enhance the extensibility of hardware devices.

Description

An Easy-to-Extend Embedded Network Terminal

technical field

The utility model relates to an embedded network terminal, in particular to an easily expandable embedded network terminal comprising a bottom board module and an expansion board module, which belongs to the technical field of computers.

Background technique

Embedded system is a kind of application-centric special-purpose computer system. Generally speaking, it consists of five parts: embedded microprocessor, peripheral hardware, embedded operating system, control and application software, and development and debugging platform. Among them, embedded microprocessors and peripheral hardware devices belong to the hardware category, while embedded operating systems, control and application software, and development and debugging platforms belong to the software category. Different from ordinary computers, the "universality" of software and hardware of embedded systems is not strong, and its software system and hardware platform have the characteristics of on-demand customization, that is, both its software system and hardware platform support software tailoring and hardware tailoring, so as to Adapt to the special requirements of different application environments for its volume, function, reliability, cost, etc. Therefore, in the embedded system, the configuration of the software system and the hardware platform should be coordinated as much as possible, so that the embedded system can achieve the best performance-price ratio and meet the various needs of users.

At present, the general-purpose hardware platforms sold in the market often have the characteristics of many external functions and relatively complex structures, and many of these functions are not needed in practice. This will result in a waste of functions and keep the hardware cost of the entire development system high, which does not conform to the economic principle. On the other hand, although the general-purpose hardware platform has a certain degree of scalability, it is often not enough in practice and cannot fully meet the needs of users. Therefore, it is necessary to develop a scalable embedded hardware platform.

Contents of the invention

Based on the above reasons, the purpose of this utility model is to provide a new type of embedded network terminal that is easy to expand. The embedded network terminal includes the minimum system capable of realizing the basic functions of the embedded system, and has an expansion unit for special applications.

For realizing above-mentioned purpose of the invention, the utility model adopts following technical scheme:

An embedded network terminal, characterized in that:

The embedded network terminal includes a backplane module and an expansion board module, and the backplane module and the expansion board module are connected through a bus;

The base module is a minimum system, including a CPU, a storage unit, a power supply and a drive circuit;

The expansion board module is equipped with a function expansion unit.

The function expansion unit is an Ethernet interface unit.

The Ethernet interface unit adopts RTL8019AS chip.

Described CPU is S3C2410X microprocessor.

The storage unit includes SDRAM chip HY57V641620 and FLASH chip HY29LV160.

The backplane module is also connected with the JTAG component used for program image programming.

There is a level conversion circuit between the bottom board module and the expansion board module.

The level conversion circuit uses a level conversion chip 74LVCC4245.

On the basis of the minimum system, the embedded network terminal described in the utility model expands the function through the expansion unit, thereby greatly improving the expandability of the hardware equipment.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment, the utility model is further described.

Fig. 1 is the circuit principle diagram of CPU bus and clock and analog input channel part A, power supply and interrupt input part C.

Fig. 2 is a schematic circuit diagram of the external extended function part B of the CPU.

Fig. 3 is a schematic circuit diagram of the JTAG component used for program image programming.

Figure 4 is a schematic diagram of the circuit of the power supply.

Fig. 5 is a schematic circuit diagram of SDRAM as a storage unit.

FIG. 6 is a schematic circuit diagram of FLASH as a storage unit.

Figure 7 is a circuit schematic diagram of the bus expansion part.

FIG. 8 is a schematic circuit diagram of a buffer circuit for level conversion.

FIG. 9 is a schematic circuit diagram of an Ethernet interface unit as a function expansion unit.

Detailed ways

The utility model adopts the design idea of providing a basic hardware platform for customizing various special equipments, that is, the embedded network terminal only includes the bottom board module as the minimum system and the expansion board module for realizing function expansion. The expansion board module can be installed with a function expansion unit for special applications, so as to realize the expansion of specific functions. In this way, if a certain function needs to be completed, it is very convenient to just connect the expansion board with this special function and the corresponding interface unit of the bottom board as the minimum system through the data bus and the address bus. Through this design, the size of the embedded network terminal can be reduced to no more than 80 mm x 80 mm, so it is suitable for use in smart devices with strict volume requirements.

Below, the utility model will be described by taking the expansion board module as a communication module and the function expansion unit as an Ethernet interface unit as an example.

In the present invention, the bottom board module as the minimum system includes components such as CPU, storage unit, power supply and drive circuit. Figures 1 to 6 are the schematic circuit diagrams of the backplane module, among which Figure 1 is a schematic circuit diagram of the CPU's bus and clock and analog input channel part A, power supply and interrupt input part C. Fig. 2 is a schematic circuit diagram of the external extended function part B of the CPU. Fig. 3 is a schematic circuit diagram of the JTAG component used for program image programming. Figure 4 is a schematic diagram of the circuit of the power supply. Fig. 5 is a schematic circuit diagram of SDRAM as a storage unit. FIG. 6 is a schematic circuit diagram of FLASH as a storage unit.

In this embedded network terminal, the CPU used is S3C2410X microprocessor, the SDRAM chip is HY57V641620, and the FLASH chip is HY29LV160. Because the S3C2410X microprocessor adopted in the utility model is a chip based on the SoC structure, many additional functions are integrated on it, and these additional functions may be required by some users, but may not be required by other users. Therefore, various systems required by users can be customized by leading out the pins of these additional functions through the expansion unit, thereby greatly improving the scalability of the network terminal.

As shown in Figure 1 and Figure 2, the microprocessor S3C2410X is connected with peripheral circuits through data bus, address bus and control bus. The microprocessor S3C2410X leads to a total of 27 address buses, AD0 and AD16 to AD26 of the address line are GPA0 to GPA11 of the multiplexed I/O port, and the data flow direction is the output direction, which is connected to the address bus. There are 32 data buses. 8 analog channel inputs are connected with analog signal quantities. The width of the data bus of BANK0 can be set to 16 bits or 32 bits. Since BANK0 is used as the BANK to start ROM, the number of bits to read ROM is determined by OM0 and OM1 when restarting. DMA operation is controlled by nXDACK0, nXDACK1, nXDREQ0, nXDREQ1, nXBREQ, nXBACK, and these pins are multiplexed with GPB5 to GPB10. nGCS0 to nGCS5 are used as memory segment selection controls, wherein nGCS1 to nGCS5 are multiplexed with GPA12 to GPA16. In addition nOE, nWE and nWAIT are also used as the control end of the bus. The mode control terminals OM2 and OM3 need to be grounded. XTOp11 and XTIp11 are used as the clock source of the system, connected to a 12MHz crystal oscillator, XTOrtc and XTIrtc are used as RTC clocks, connected to a 32.768KHz crystal oscillator, and OM2 and OM3 are grounded. For further description of the microprocessor, you can refer to its user manual "S3C2410X 32-Bit RISC Microprocessor USER'SMANUAL" (downloadable at http://www.samsungsemi.com), so I won't go into details here. What Figure 3 shows is the JTAG assembly, and what Figure 4 shows is the power supply section of the backplane module, both of which are very conventional circuits. Figure 5 and Figure 6 show SDRAM and FLASH as storage units respectively. In embedded devices, the role of SDRAM is basically the same as that of ordinary PCs. They are all data storage units, while FLASH is equivalent to the hard disk in PCs, where operating systems, control and application software are stored.

The expansion board module in this embodiment is shown in Fig. 7 to Fig. 9, and it is a module for realizing the communication function. Among them, Fig. 7 is the circuit schematic diagram of the bus expansion part, Fig. 8 is the circuit schematic diagram of the buffer circuit used to realize the level conversion between the backplane and the expansion board, and Fig. 9 is the circuit principle of the Ethernet interface unit as the function expansion unit picture.

Figure 7 shows peripheral bus slot U100A, address and data bus slot U100B and LCD bus slot U100C respectively, and their connections to the above-mentioned circuit components are clearly shown in the figure, and will not be repeated here. Figure 8 shows the circuit schematic diagram of the buffer circuit used to realize level conversion, in which three chips 74LVCC4245 that realize level conversion between 3.3V and 5V are used to solve the problem of using 3.3V voltage on the backplane and using 5V Voltage level shifting between expansion boards. Figure 9 mainly shows the connection relationship of the Ethernet interface chip RTL8019AS, and the functions of this chip will be described in detail below.

The following introduces the basic process of the expansion board module to realize Ethernet data communication. The data communication includes two parts: data receiving and data sending, which will be described separately.

The data receiving process starts from the RJ45 slot of the expansion board (namely CN700), its function is to receive external electrical signals or transmit electrical signals to external devices. It first passes through the network transformer (that is, U705, which plays an isolation role), and converts the voltage of the signal to the Ethernet interface chip RTL8019AS. RTL8019AS restores the received electrical signal to data, and stores it in the chip RAM according to the specified format. The function of this chip is to complete the mutual conversion between data packets and electrical signals. The Ethernet protocol is automatically completed by the chip hardware, and it is transparent to the programmer. After the Ethernet chip puts the data packet in the chip's RAM, it sends an interrupt to notify the processor S3C2410X that a data packet has arrived. Processor S3C2410X and RTL8019AS connect the data line and address line from the processor to RTL8019AS through the level conversion chip 74LVCC4245, which mainly plays the role of bus matching and buffering. The processor S3C2410X finds the corresponding address unit of the RTL8019AS input buffer through the address line, and then takes the data away through the data line, and puts it in a buffer of the HY57V641620SDRAM memory unit, and finally processes the data through the network protocol stack and gives it to the program for use.

The process of data sending is the opposite. It is to address the data of a unit of the memory buffer through the address bus, find the address unit of the corresponding RAM of RTL8019AS, and then transfer the data to be sent to the RAM of the RTL8019AS chip through the data bus. This also requires bus matching and buffering of 74LVCC4245. The RTL8019AS network chip converts data and electrical signals, and then sends the electrical signals to the network transformer, and after voltage conversion, sends them to the RJ45 slot, and finally sends the signals out.

The above is a detailed description of the easily expandable embedded network terminal described in the present invention. For those skilled in the art, various obvious changes to the method without departing from the spirit of the method described in the present invention and the scope of claims are within the protection scope of the present invention.

Claims (8)

1. An embedded network terminal, characterized in that: The embedded network terminal includes a backplane module and an expansion board module, and the backplane module and the expansion board module are connected through a bus; The base module is a minimum system, including a CPU, a storage unit, a power supply and a drive circuit; The expansion board module is equipped with a function expansion unit. 2. The embedded network terminal as claimed in claim 1, characterized in that: The function expansion unit is an Ethernet interface unit. 3. The embedded network terminal as claimed in claim 2, characterized in that: The Ethernet interface unit adopts RTL8019AS chip. 4. The embedded network terminal as claimed in claim 1, characterized in that: Described CPU is S3C2410X microprocessor. 5. The embedded network terminal as claimed in claim 1, characterized in that: The storage unit includes SDRAM chip HY57V641620 and FLASH chip HY29LV160. 6. The embedded network terminal as claimed in claim 1, characterized in that: The backplane module is also connected with the JTAG component used for program image programming. 7. The embedded network terminal according to claim 1, characterized in that: There is a level conversion circuit between the bottom board module and the expansion board module. 8. The embedded network terminal as claimed in claim 7, characterized in that: The level conversion circuit uses a level conversion chip 74LVCC4245.

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