CN2772130Y - Asymmetrical high-speed half-duplex communication device - Google Patents

Abstract

The utility model relates to a high-speed half-duplex communication device which is used for asymmetric high-speed digital signal communication among embedded devices. Communication signals use LVDS signals, a signal path uses an unshielded twisted pair and a physical interface uses an RJ45 socket and an RJ45 plug. A data line is defined according to the asymmetrical characteristic of communication data, and the data line gives an integrated communication control method. The utility model can realize the handshake, the collision detection and the signal path preemption of both communication sides. The device and the method have the advantages of simplicity and practicality.

Description

An asymmetric high-speed half-duplex communication device

technical field

The utility model relates to the technical field of communication, in particular to an asymmetric high-speed half-duplex communication device.

Background technique

In embedded devices such as mobile robots, digital monitoring, and home digital equipment, a large amount of high-speed data communication is often required, and there is a large difference in the amount of bidirectional communication data. The amount of data in one direction is much larger than that in the other direction. Communication Sometimes the distance between the two parties is far away, up to several meters or even tens of meters, and only board-level communication often cannot meet the requirements. Moreover, the existing application environment not only requires extremely high speed and low power consumption, but also requires as little noise as possible to meet the increasingly stringent EMI (electromagnetic radiation) requirements.

When the transmission distance is long, it is obviously not feasible to directly use TTL or COMS signals (TTL and COMS are commonly used digital signal standards) for data transmission, because TTL and COMS signals not only consume a lot of power, but also have poor anti-interference ability. The bit error rate is high, the mutual interference is very serious, and the electromagnetic radiation is also large; the traditional serial port and parallel port cannot meet the requirements of communication speed. One possible option is to use the interface and protocol of the LAN, so that the quality of the signal is guaranteed, but now the commonly used LAN is 10M and 100M (the upper limit of 100M is difficult to reach), and a pair of signal lines are used for two-way communication. It is suitable for asymmetrical data communication, and the communication speed cannot fully meet the requirements; moreover, a dedicated LAN physical electrical interface and complex communication protocols are used in the device, and the interface logic between the LAN and the device needs to be designed, which increases the complexity and design difficulty of the device .

Low-voltage differential signal LVDS (low-voltage differential signal) is a small-amplitude differential signal technology that uses very low-amplitude signals (about 350mV) to transmit data through a pair of differential PCB (Print Circuit Board: printed circuit board) traces or balanced cables. It allows individual channel transfer rates of hundreds of megabits per second (Mbps). And it has the characteristics of low power consumption, high speed, strong anti-interference ability and small electromagnetic radiation. The transmission distance on the twisted pair can reach 100 meters, and the speed can reach 100M. Utilizing LVDS to transmit signals on twisted-pair wires can meet the basic requirements of communication lines and communication speed, but there is currently no dedicated signal line definition and simple and practical communication protocol for using twisted-pair wires to transmit LVDS signals in embedded devices.

Contents of the invention

In order to solve the problem that there is no dedicated communication device and simple and practical communication method to realize high-speed asymmetric digital signal communication between embedded devices, the utility model designs a device for transmitting high-speed asymmetric digital signal using twisted pair.

In order to achieve the above purpose, the LVDS signal is used to communicate on the twisted pair, and the twisted pair signal is defined according to the asymmetrical communication characteristics, and a complete communication method is given to realize the communication handshake logic and channel Conflict detection and preemption.

The utility model can be used for middle-distance real-time transmission of digital video signals, and the communication between special embedded devices whose two-way transmission data volume is unequal.

The utility model defines the data line according to the asymmetry of the amount of communication data, can reasonably use the channel to increase the speed, provides a simple and practical communication method, can effectively ensure that the communication is carried out correctly and effectively, saves complicated communication protocols, and has simple Practical advantages.

Technical solutions

An asymmetric high-speed half-duplex communication device, including: communication party A and communication party B;

The communication party A and the communication party B are composed of sockets, interface circuits, communication protocols, control circuits and embedded devices. communication party B,

Use unshielded twisted pair as the communication medium;

Digital signals are transmitted using low-voltage differential signaling.

The physical interface between the twisted pair and the communication parties uses an RJ45 socket and plug, and the two-legged wire is a category 5 or super category 5 unshielded twisted pair.

The data lines are defined according to the asymmetry of communication data, and the number of data lines used in the two directions is not equal.

The LVDS interface circuits of the two communication parties use DS90LV019, MAX9637, MAX9638 chips or other LVDS interface chips.

The communication protocol and its control can be implemented by MCU programming in the embedded system; it can also be implemented by an FPGA, or use an FPGA that supports LVDS interface to implement the communication protocol, control circuit and LVDS interface circuit in an FPGA, and then communicate with Bus connection for embedded systems.

The interface circuit, the communication protocol and the control circuit are integrated together, and then connected with the embedded device through the bus.

The communication data between two embedded systems (an embedded system is a device or system that performs a dedicated function and is controlled by an internal computer.) is asymmetrical, and the amount of data in one direction is much larger than that in the other direction.

Description of drawings

Fig. 1 is a schematic diagram of an asymmetric high-speed half-duplex communication device;

Fig. 2 is a structural diagram of an asymmetric high-speed half-duplex communication device;

Fig. 3 is the LVDS interface circuit on the communication party A;

Fig. 4 is the LVDS interface circuit on the communication party B;

Fig. 5 is a sequence diagram of asymmetric high-speed half-duplex communication control;

Detailed ways

For ease of description, as shown in Figure 1, the two parties in communication are defined as communication party A and communication party B, the communication from communication party B to communication party A is defined as uplink communication, and the communication from party A to party B is defined as downlink communication. Among them, the amount of uplink communication data is large (usually digital video data), and the amount of downlink communication data is small (usually command or status information). The communication between the two parties is realized on the twisted pair with LVDS signals. There are dedicated LVDS conversion chips or FPGA (Field Programmable Logic Array) chips supporting LVDS interfaces on both sides of the communication. The twisted pair is connected to the two sides of the communication using RJ45 sockets and plugs.

In order to improve the communication speed, the method of synchronous communication is adopted, and the four pairs of twisted pairs are defined as follows: one pair is defined as the clock signal CLK, regardless of uplink and downlink communication, CLK is controlled by Party B; due to the large amount of uplink communication data, two pairs of lines are used As an uplink communication data line (UpData, hereinafter referred to as UD0-1), it is controlled by Party B; as a pair of downlink data lines (DownData, hereinafter referred to as DD), it is controlled by Party A.

Since the uplink and downlink communication share the same CLK, the communication is half-duplex. In the idle state, all signal lines are in the high level state, and the communication request and response are realized through the signals CLK and DD.

Figure 2 is a structural diagram of the device. The structure of the communication parties is basically symmetrical, connected by twisted pair, but the signal definition of the twisted pair is asymmetric. A1 and B1 are RJ45 sockets for connecting twisted-pair cables. A2 and B2 are LVDS interface circuits, which are used to realize signal level conversion, and convert COMS and TTL signals in embedded devices into LVDS signals. The specific connection relationship of the circuit is shown in Figure 3 and Figure 4, where A2 corresponds to Figure 3, B2 corresponds to Figure 4. A3 and B3 are communication protocol and control circuit, the control of communication protocol can be realized by software and hardware. When using hardware implementation, the control of the protocol is completed through FPGA, and the control of the communication protocol and the corresponding interface logic are implemented in an FPGA. It is also possible to use an FPGA that supports the LVDS interface to integrate A2 and A3 (B2 and B3) together. Then it is connected with the embedded device through the bus; the control of the communication protocol can also be realized by programming the MCU (microcontroller) in the embedded device, and the LVDS interface circuit is connected with the bus of the embedded device. A4 and B4 are embedded devices that need to communicate.

Figure 3 and Figure 4 are the LVDS interface circuits of both sides of the communication respectively. DS90LV019 of NC Company and MAX9637 and MAX9638 chips of MAX Company are used in this device (other LVDS interface chips can also be used), and the connection relationship is shown in the figure.

The uplink communication process is shown in Figure 5a: in the idle state, when Party B sends an uplink communication request, first set the CLK signal to low level, and apply for communication; Set DD to low level as a response. After receiving the response, Party B sets CLK to high level, then DD is set to high level, and Party A enters the state of receiving data; Party B controls the synchronous clock CLK, through the uplink data line UD Upload data; after the data transmission is completed, transmit an end character, and the communication module of Party A will exit the acceptance state after receiving the end character, and end this communication; each signal line is in an idle state.

The process of downlink communication is shown in Figure 5b. Communication Party A first sets DD to low level to send an application. After receiving the application, Party B will set CLK to low level as a response. Party A monitors the state of CLK after T2 time. After waiting for the response, DD is set to high Level, then CLK is set high to complete the handshake. Party A enters the sending state, and under the control of Party B's synchronous clock CLK, downloads commands through the data line DD. The downloaded commands are of fixed length. After the transmission, the communication line enters an idle state.

When the communication is idle, both communication parties can apply for communication. The first applicant obtains the communication right, and the next communication can only be carried out after this communication is completed. The communication process cannot be interrupted. But if under idle state, both sides send communication application simultaneously (CLK and DD are set as low level simultaneously) just there is the conflict of communication, have adopted following method to solve this conflict in the invention. First of all, it is agreed that the priority of downlink communication is higher than that of uplink communication. When both parties apply at the same time, downlink communication will seize the channel. The specific process is (as shown in Figure 5c): Party A and Party B set CLK and DD to low level at the same time, and Party B will detect the state of the DD line at T1 (T1<T2). If DD is found to be low, then Indicates that Party A has also sent an application at this time, because under normal circumstances, DD can only respond after T2 time, at this time Party B suspends this communication request, sets CLK as high, and responds to The downlink communication responds. After the handshake signal is completed, the communication starts. After this communication is completed, the suspended upload communication is resumed.

Claims (7)

1. an asymmetric high speed half duplex communicator is characterized in that, comprising: the communication Party A and the Party B that communicates by letter; The communication Party A forms by socket, interface circuit, communication protocol and control circuit and embedded equipment with the Party B that communicates by letter, and socket, interface circuit, communication protocol and control circuit and embedded equipment are interconnected, connect the communication Party A and the Party B that communicates by letter by twisted-pair feeder again,

Use unshielded twisted pair as communication media;

Utilize Low Voltage Differential Signal to come transmission of digital signals.

2. asymmetric high speed half duplex communicator according to claim 1 is characterized in that, the physical interface of described twisted-pair feeder and communicating pair uses RJ45 socket and plug, and double-legged line is 5 classes or surpasses 5 class unshielded twisted pairs.

3. asymmetric high speed half duplex communicator according to claim 1 is characterized in that described data wire defines according to the asymmetric of communication data, and the data wire number that both direction uses is unequal.

4. asymmetric high speed half duplex communicator according to claim 1 is characterized in that, the LVDS interface circuit of communicating pair uses DS90LV019, MAX9637, MAX9638 chip or other LVDS interface chip.

5. asymmetric high speed half duplex communicator according to claim 1 is characterized in that, communication protocol and control thereof can be realized by the programming of the MCU in the embedded system; Also can realize, or use the FPGA that supports the LVDS interface, communication protocol, control circuit and LVDS interface circuit be realized in a slice FPGA, and then be connected with the bus of embedded system by a slice FPGA.

6. asymmetric high speed half duplex communicator according to claim 1 is characterized in that interface circuit and communication protocol and control circuit are integrated together, and is connected with embedded equipment by bus then.

7. asymmetric high speed half duplex communicator according to claim 1 is characterized in that, the communication data between two embedded systems is asymmetric, and the data volume of a direction is much larger than the data volume of another direction.

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