CN2746535Y - Semiconductor chip on insulator - Google Patents

Abstract

A Semiconductor-On-Insulator (SOI) chip provides Mesa Isolation (Mesa Isolation) On a portion of a silicon-On-Insulator covered Semiconductor-On-Insulator chip to isolate a silicon film. The Isolation structure of the present invention may further comprise an Isolation structure of a transmission system, such as Shallow Trench Isolation (STI), to isolate a silicon film.

Description

semiconductor-on-insulator chip

technical field

The utility model relates to the field of semiconductor components, and in particular to an SOI component on a silicon-on-insulator (Silicon-On-Insulator; SOI) region with an uneven thickness of the active layer, and an SOI component in a selected active region Platform (Mesa) Quarantine.

Background technique

The integrated circuit made by applying the silicon-on-insulator technology on the traditional system is to form an integrated circuit on the SOI substrate. Generally speaking, the SOI substrate deposits a thinner silicon film (Silicon Film) on an insulating layer, such as a buried oxide layer (Buried Oxide Layer; BOX Layer), which is generally known as an active layer (Active Layer). ). An insulating layer or buried oxide layer is formed on the silicon substrate. Active devices (Active Devices), such as transistors (Transistor), are formed in the active region in the active layer. As for the size and position of the active region, it is defined by the isolation region, such as the shallow trench isolation (Shallow Trench Isolation; STI) region. The active components in the active region are insulated from the substrate by the buried oxide layer. Compared with stacked silicon components (Bulk Silicon Device), components formed on SOI substrates have many advantages, including no reverse body effect (Reverse Body Effect), no latch-up (Latch-Up) effect, soft-error (Soft- Error) immunity, and reduce junction capacitance (Junction Capacitance). Therefore, SOI technology can improve the performance of component speed, make the structure density higher, and reduce energy consumption.

There are generally two types of SOI transistors: Partially-Depleted (PD) SOI transistors and Fully-Depleted (FD) SOI transistors. The PD-SOI transistor is formed in the active region, and the active layer thickness of the active region is larger than the maximum depletion width (Depletion Width), so the PD-SOI transistor has a partially depleted body. The advantage of the PD-SOI transistor is that it is highly feasible to manufacture, but the PD-SOI transistor will have a floating body effect (Floating Body Effect). Digital circuits are more resistant to floating body effects, so PD-SOI transistors can be used. FD-SOI transistors are formed in the active region where the thickness of the active layer is smaller than the maximum depletion width. FD-SOI transistors use thinner active layers, or use lighter body doping, so the problem of floating body effect is avoided. Generally speaking, the analog circuit system (Analog Circuitry) using FD-SOI components in the design performs better than the analog circuit system using PD-SOI components. Since analog and digital circuits may be fabricated on the same SOI chip, it would be beneficial to provide SOI chips for areas of digital circuitry as well as analog circuitry. Therefore, on SOI chips, it is quite practical to provide at least two different thicknesses of the silicon film or active layer. FD-SOI components can use areas with very thin silicon films, while PD-SOI components use areas with relatively thick silicon films. Of course, using at least two silicon films or active layers with different thicknesses also increases the flexibility in circuit and device design.

Ellis-Monaghan et al. disclosed a SOI double-layer film structure in U.S. Patent No. 5,952,695. After the device isolation region is formed, the selected region of the active layer is epitaxy Grow to second thickness. In this design, since the epitaxial layer tends to grow laterally into the isolation region and cause the isolation region to fail, the thickness of the epitaxial layer is limited and cannot be too large.

Imai disclosed a method for forming PD-SOI and FD-SOI components on a general substrate in US Patent Publication No. 6,222,234 B1. In this design, the active layer region with two different thicknesses is formed after the device isolation region is formed. The active region with thinner silicon layer is used to make FD-SOI components, while the active region with thicker silicon layer is used to make PD-SOI components.

An et al. disclosed in US Patent No. 6,414,335B1 a structure of an SOI chip with non-uniform active layer thickness. An et al. disclosed several methods of forming SOI chips with non-uniform active layer thicknesses in U.S. Patent No. 6,448,114 B1. Before providing the isolation structure, active layers with different thicknesses are formed first. In one embodiment of this design, specific areas of the active layer are etched to form thinner areas of the active layer. In another embodiment, epitaxial growth is performed on a specific area of the active layer to form a thicker area of the active layer. However, in the two patents of US Patent Announcement No. 6,414,335 B1 and US Patent Announcement No. 6,448,114 B1, there is no discussion on forming an isolation structure in an active region with multiple active layer thicknesses on the same SOI chip.

1a to 1b are cross-sectional views of a conventional SOI structure. Please refer to FIG. 1a, which is a cross-sectional view of a conventional SOI substrate. Wherein, the SOI substrate 10 is sequentially stacked by the silicon substrate i00 , the insulating layer 102 and the active layer 104 , so the active layer 104 is electrically isolated from the silicon substrate 100 by the insulating layer 102 . Please refer to FIG. 1b, which shows a cross-sectional view of a conventional SOI chip. Wherein, after the silicon substrate 100 is processed, several active regions 106 are formed in the active layer 104 . Then, active components 108 , such as transistors and diodes (Diodes), can be formed in the active region 106 . The active regions 106 are electrically isolated from each other by the isolation region 110 , and the isolation region 110 can be formed by shallow trench isolation, for example. In the conventional SOI chip 11 shown in FIG. 1 b , the thickness of the active layer 104 is uniform. The uniform thickness of the active layer 104 and the flat surface of the silicon substrate 100 simplifies the process of forming the isolation region 110 . Currently commercially available SOI technology products use active layers with uniform thickness and shallow trench isolation.

There are many advantages to providing at least two different thicknesses of silicon films on SOI substrates. Please refer first to FIG. 2 a , which shows a cross-sectional view of an SOI substrate having two different thicknesses of silicon films or active layers after processing. Please refer to FIG. 2a. Before forming the isolation region, the SOI substrate 12 is sequentially stacked from a silicon substrate 100, an insulating layer 102, and an active layer 104. In the SOI substrate 12, an active layer 104 with different thicknesses is first formed on the insulating layer. on layer 102. In the first region 120 of the active layer 104, the active layer 104 has a first thickness tSi1, and in the second region 130 of the active layer 104, the active layer 104 has a second thickness tSi2. Certainly, the active layer 104 may also have other regions with different silicon film thicknesses. For example, in the third region 140 of the active layer 104, the active layer 104 has a third thickness tSi3, and so on. The active layer 104 having at least two different thicknesses provides more options, the thinner region of the active layer 104 can be used to make components such as FD-SOI transistors, and the thicker region of the active layer 104 can be used to make components such as PD - Components of SOI transistors. In addition, the thicker region of the active layer 104 can also be used to form, for example, diodes or lateral unidirectional bipolar insulated gate transistors (Lateral Unidirectional Bipolar Insulated Gate Type Transistor; Lubistor), the current drive of these components (Drive) and the active layer 104 proportional to the thickness. For example, diodes or side unidirectional bipolar insulated gate transistors are used for electrostatic discharge protection (Electrostatic Discharge; ESD) in SOI circuits.

However, using active layers of at least two thicknesses may result in an uneven surface of the SO1 substrate 12, as shown in FIG. 2a. Since the surface of the SOI substrate 12 is uneven, it is quite difficult to provide isolation regions in the active region where the thickness of the active layer 104 is different. That is to say, the isolation region as shown in the cross-sectional view of FIG. 2b cannot be easily or directly formed. First, as shown in Figure 2b, the isolation trenches in different regions have different depths. Secondly, the upper surfaces of the isolation regions also have different heights. Since the isolation structure such as shallow trench isolation uses chemical mechanical polishing (CMP) to achieve the flatness of the upper surface of the isolation region, it is impossible to directly apply chemical mechanical polishing to complete the isolation structure shown in FIG. 2b.

Invention content

Therefore, the purpose of this utility model is to provide a semiconductor-on-insulator chip, which provides platform isolation (Mesa Isolation) in a part of the SOI chip with multiple active layer thicknesses.

Another object of the present invention is to provide a semiconductor-on-insulator chip that provides existing isolation regions, such as shallow trench isolation regions, for a part of the SOI chip with multiple active layer thicknesses.

Another object of the present invention is to provide a semiconductor-on-insulator chip, which provides platform isolation for multiple active regions with different active layer thicknesses.

According to the above purpose of the present utility model, a semiconductor-on-insulator (Semiconductor-On-Insulator) chip is proposed, at least comprising: a semiconductor layer covering the insulating layer; a first region of the semiconductor layer having a first thickness, and the first region At least including several first active regions defined by shallow trench isolation method; and a second region having a semiconductor layer with a second thickness, and the second region includes at least several second active regions defined by platform isolation method .

According to a preferred embodiment of the present invention, the above-mentioned first thickness is greater than the second thickness.

According to another object of the present utility model, a semiconductor-on-insulator chip is proposed at least comprising: a semiconductor layer covering the insulating layer; a first region of the semiconductor layer having a first thickness, and the first region includes at least a plurality of first active regions defined; and a second region having a semiconductor layer with a second thickness, and the second region at least includes a plurality of second active regions defined by the platform isolation method.

According to a preferred embodiment of the present invention, the above-mentioned first thickness is greater than the second thickness.

The utility model discloses an isolation structure for an active area with a thinner active layer, wherein the isolation structures are separate and simple, and can avoid the disadvantages of the prior art. Therefore, the problem of using a specific isolation process in regions with different active layer thicknesses can be avoided. Furthermore, in the present invention, the active area with a thinner active layer is provided with platform isolation, while the active area with a thicker active layer is provided with shallow trench isolation.

Therefore, the advantage of the present invention is to provide platform isolation for a portion of an SOI chip with multiple active layer thicknesses.

Another advantage of the present invention is to provide existing isolation regions, such as shallow trench isolation regions, to a portion of an SOI chip with multiple active layer thicknesses.

Yet another advantage of the present invention is to provide platform isolation in multiple active regions with different active layer thicknesses.

Description of drawings

The preferred embodiment of the present utility model is described in more detail with the following figures in the aforementioned explanatory text, wherein:

Fig. 1a is a cross-sectional view of a conventional SOI substrate.

FIG. 1b is a cross-sectional view of an existing SOI chip with uniform thickness of the active layer. The active components are formed in the active region, and the active regions are insulated by isolation regions.

Fig. 2a is a cross-sectional view of SOI substrates with different active layer thicknesses before isolation regions are formed.

Figure 2b is an isolation region on a silicon substrate with an uneven surface.

Figure 3a is a plan view of a semiconductor-on-insulator substrate with multiple active layer thicknesses and isolation structures.

Fig. 3b is a cross-sectional view of a semiconductor-on-insulator substrate taken along the line A-A in Fig. 3a.

4 is a cross-sectional view of a semiconductor-on-insulator chip having multiple silicon film thicknesses.

5 is a flow chart of a method for manufacturing an SOI chip with multiple active layer thicknesses using two different isolation methods according to a preferred embodiment of the present invention.

6a to 6i are cross-sectional views of the manufacturing process according to a preferred embodiment of the present invention.

7 is a flow chart of a method for manufacturing an SOI chip with multiple active layer thicknesses using two different isolation methods according to another preferred embodiment of the present invention.

8a to 8i are cross-sectional views of the manufacturing process according to another preferred embodiment of the present invention.

Detailed ways

Please refer to Figure 3a, which is a plan view (Plan View) of a semiconductor-on-insulator substrate with multiple active layer thicknesses and isolation structures, and please also refer to Figure 3b, Figure 3b is obtained along the A-A section line of Figure 3a Cross-sectional view of a semiconductor-on-insulator substrate. The semiconductor-on-insulator substrate 15 is sequentially stacked by a silicon substrate 150 , an insulating layer 152 and an active layer 154 , wherein the above-mentioned insulating layer 152 can be buried in an oxide layer, for example. The active layer 154 can be divided into a first region 170, a second region 180 and a third region 190, and the first region 170 is provided with several active regions 170a, the second region 180 is provided with several active regions 180a, and the third region 190 is provided with several active regions 170a. There are several active regions 190a. Wherein, the active layer 154 in the first region 170 has a first thickness tSil, and the active layer 154 in the second region 180 has a second thickness tSi2. Of course, the active layer 154 may also have other regions with different silicon film thicknesses. For example, the active layer 154 in the third region 190 has a third thickness tSi3, and so on.

Active regions with a thinner silicon film, such as several active regions 180 a in the second region 180 of the active layer 154 , form trenches 157 to insulate each active region 180 a. The trenches 157 divide the active layer 154 into silicon islands or silicon mesa structures, such as the structure of several active regions 180a in the second region 180 of FIG. 3b. The platform isolation method cuts off the electrical connection between adjacent active regions 180 a by removing a portion of the active layer 154 in the SOI substrate 15 .

Please refer to FIG. 4 , which is a cross-sectional view of a semiconductor-on-insulator chip with multiple silicon film thicknesses. Wherein, the active component 195 is formed in various active regions 170a, 180a and 190a. The active devices 195 formed on the thinner active region 180 a of the active layer 154 are isolated from each other by, for example, platform isolation defined by the trench 157 . In a preferred embodiment, the second thickness tSi2 of the thinner active layer 154 ranges from 5 Angstrom (Angstrom; Å) to 200 Å. The semiconductor material constituting the active layer 154 is preferably silicon, and can also be a semiconductor of any other element, such as germanium (Germanium; Ge), any alloy semiconductor such as silicon-germanium, or any compound semiconductor such as gallium arsenide (Gallium Arsenide; GaAs) or iodine phosphide (IndiumPhosphide; IP). In the present invention, the material of the active layer 154 is silicon, but the silicon can be relaxed state (Relaxed State) or tight (strained) silicon. The active devices 195 formed in the thicker active region 170a of the active layer 154 are insulated from each other by the isolation region 160 formed, for example, by shallow trench isolation. The active layers 154 are isolated from each other by shallow trench isolation, for example, wherein the first thickness tSi1 is in the range of 100 Å to 2000 Å.

In order to make the description of the present utility model more detailed and complete, the following describes several methods of forming platform isolation and shallow trench isolation on the same SOI substrate with multiple thicknesses of the active layer or silicon film, and please cooperate with Fig. 5 to Fig. 8 illustrations.

In a first embodiment, an SOI substrate having multiple active layer thicknesses is first provided. Please refer to FIG. 5 , which shows a flowchart of a method for manufacturing an SOI chip with multiple active layer thicknesses by using two different isolation methods according to a preferred embodiment of the present invention. Please refer to FIG. 6a to FIG. 6i together, which illustrate the cross-sectional view of the manufacturing process of the first embodiment of the present invention. First, as described in step 202, an SOI substrate 30 having at least two different thicknesses of the active layer 304 is provided, as shown in FIG. 6a. Wherein, the SOI substrate 30 is formed by sequentially stacking an insulating layer 302 and an active layer 304 on a silicon substrate 300, and wherein the insulating layer 302 can be buried in an oxide layer, and at least two different thicknesses of the active layer 304 include a first The first region 310 has a thickness, and the second region 320 has a second thickness. Of course, the SOI substrate 30 can also have a third region 330 with a third thickness, and so on.

Then, as described in step 204 , a first isolation mask 305 is formed on the active layer 304 of the SOI substrate 30 , wherein the first isolation mask 305 is used to form subsequent platform isolation. The material of the first isolation mask 305 can be any known mask material used in the prior art, such as photoresist, silicon oxide, silicon nitride, or a combination of the above materials. The first isolation mask 305 may or may not be a conformal shape (Conformal Topology), that is, when the thickness of the first isolation mask 305 is consistent, the first isolation mask 305 is conformal, but when the thickness of the first isolation mask 305 is consistent, When the thickness of one isolation mask 305 is not uniform, the first isolation mask 305 is not conformal. After the first isolation mask 305 is patterned, several openings 306 are exposed, as shown in FIG. . Next, as described in step 206, using an etching process, such as reactive ion etching (Reactive Ion Etching; RIE), several trenches 308 are etched in the second region 320 of the active layer 304 and part of the insulating layer 302 is exposed, A cross-sectional view of the SOI chip is formed as shown in FIG. 6 c , wherein the trench 308 divides the second region 320 of the active layer 304 into isolated platforms 312 . In addition, the mixed gas used for reactive ion etching at least includes sulfur hexafluoride (Sulfur Hexafluoride; SF6), helium (Helium; He), and oxygen (Oxygen; O2).

According to the first preferred embodiment of the present invention, the first isolation mask 305 is used to define platform isolation. As described in step 208, the first isolation mask 305 is removed to form a structure as shown in FIG. 312 is also called silicon island (Silicon Island), which is used as the active area 320a.

Subsequently, a second isolation structure is to be formed. The second isolation structure can be formed using a shallow trench isolation process known in the art. The commonly used shallow trench isolation process is described next. As described in step 210, a second isolation mask 315 is formed on the active layer 304 of the SOI substrate 30, wherein the material of the second isolation mask 315 can be any known mask material used in the prior art, such as silicon oxide or silicon nitride. A preferred material of the second isolation mask 315 is an anti-oxidation material, such as a silicon nitride layer covering the pad silicon oxide layer. A layer of pad silicon oxide layer can be formed first by dry thermal oxidation (DryThermal Oxidation), and then a silicon nitride layer can be stacked on the silicon oxide layer by chemical vapor deposition (Chemical Vapor Deposition; CVD). The chemical vapor deposition method uses Dichlorosilane (Dichlorosilane) and ammonia (Ammonia) were used as reaction gases. Next, the second isolation mask 315 is patterned using a lithography process, and then the second isolation mask 315 is etched using a reactive ion etching process, wherein the reactive ion etching process utilizes sulfur hexafluoride, helium and trifluoromethane (Trifluoromethane) as an etching reaction gas. The patterned second isolation mask 315 exposes openings 316 where trench structures, such as shallow trench isolations, are to be formed, as shown in FIG. 6e.

Again as described in step 212, use the second isolation mask 315 to etch trenches 318 in the openings 316 exposed by the first region 310 and the third region 330 of the active layer 304, and expose part of the insulating layer 302, forming The structure shown in FIG. 6 f clearly shows that the first region 310 and the third region 330 of the active layer 304 are separated into an active region 310 a and an active region 330 a by trenches 318 . Next, a layer of silicon oxide 318 a is grown on the sidewall of the trench 318 by thermal oxidation, and then the trench 318 is filled with the silicon oxide 318 a. Silicon oxide 318a may also be deposited by chemical vapor deposition. The filled silicon oxide 318a can be densified through a tempering step. The SOI substrate 30 is planarized by chemical mechanical polishing (CMP) to form a cross-sectional view as shown in FIG. 6g. The remaining second isolation mask 315 can be removed using a suitable etchant. If the second isolation mask 315 is a stack structure in which the silicon nitride layer is located on the silicon oxide layer, it can be etched in hot phosphoric acid first, and then etched in hydrofluoric acid to remove the second isolation mask 315, so The process of forming shallow trench isolation is completed, and the cross-sectional view shown in FIG. 6h is obtained. Then, as described in step 214, an active device 340 is fabricated on the active layer 304 to form a structure as shown in FIG. 6i.

In the second embodiment, the shallow trench isolation is formed first, and then the platform isolation is formed. Please refer to FIG. 7 , which is a flow chart of a method for manufacturing an SOI chip with multiple active layer thicknesses by using two different isolation methods according to another preferred embodiment of the present invention. Please refer to FIG. 8a to FIG. 8i together, which illustrate the cross-sectional view of the manufacturing process of the second embodiment of the present invention. First, as described in step 402, an SOI substrate 50 having at least two different thicknesses of the active layer 504 is provided, wherein the SOI substrate 50 is formed by sequentially stacking an insulating layer 502 and an active layer 504 on the silicon substrate 500, and wherein the insulating The layer 502 can be, for example, buried in an oxide layer, and the at least two different active layer 504 thicknesses include a first region 510 having a first thickness and a second region 520 having a second thickness. Of course, the SOI substrate may also have a third region 530 with a third thickness, and so on, as shown in FIG. 8 a .

Then, as described in step 404 , a first isolation mask 505 is formed on the active layer 504 of the SOI substrate 50 , wherein the first isolation mask 505 is used to form a subsequent shallow trench isolation region. The material of the first isolation mask 505 is preferably a silicon nitride layer covering a silicon oxide layer. The shallow trench isolation process is as described in the first embodiment above, and is used to insulate the first region 510 and the third region 530 of the active layer 504 , and the cross-sectional views of the shallow trench isolation process are shown in FIGS. 8 b to 8 e . The first isolation mask 505 can utilize a thermal oxidation method to form a pad silicon oxide layer first, and then use a chemical vapor deposition method to stack a silicon nitride layer on the silicon oxide layer, wherein the chemical vapor deposition method uses dichlorosilane and ammonia as a reactive gas. Next, the first isolation mask 505 is patterned by a lithography process, and then the first isolation mask 505 is etched by a reactive ion etching process, wherein the reactive ion etching process utilizes sulfur hexafluoride, helium and trifluoromethane as an etching reaction gas. The patterned first isolation mask 505 exposes openings 506 where trench structures, such as shallow trench isolations, are to be formed, as shown in FIG. 8b.

Next, as described in step 406, trenches 508 are etched in the openings 506 exposed by the first isolation mask 505 in the first region 510 and the third region 530 of the active layer 504, and part of the insulating layer 502 is exposed, A structure as shown in Figure 8c is formed. Next, a layer of silicon oxide 512 is grown on the sidewall of the trench 508 by thermal oxidation, and then the trench 508 is filled with the silicon oxide 512 . Silicon oxide 512 may also be deposited by chemical vapor deposition. Filled silicon oxide 512 may undergo a tempering step to densify it. The SOI substrate 50 is planarized by chemical mechanical polishing to form a cross-sectional view as shown in FIG. 8d. The remaining first isolation mask 505 can be removed with a suitable etchant. If the first isolation mask 505 is a stack structure in which the silicon nitride layer is located on the silicon oxide layer, it can be etched in hot phosphoric acid first, and then etched in hydrofluoric acid to remove the first isolation mask 505, as in the step As described in 408 , the process of forming shallow trench isolation is completed in this way, and the cross-sectional view shown in FIG. 8e is obtained.

Therefore, in the second embodiment, the first isolation mask 505 is used to define the shallow trench isolation structure. Next, as described in step 410, a second isolation mask 515 is deposited and patterned, wherein trenches 516 are used to define mesa (silicon island) structures, as shown in FIG. 8f. Then, as described in step 412, using an etching process, a platform (silicon island) isolated by the trench 518 is defined by forming a trench 518, and a part of the insulating layer 502 is exposed, as shown in FIG. 8g, wherein the trench 518 This is platform isolation. Then, the second isolation mask 515 is removed, as shown in FIG. 8h , it can be clearly shown that the first region 510 and the third region 530 of the active layer 504 are respectively separated by silicon oxide 512 into an active region 510a and an active region 530a. , and the second region 520 of the active layer 504 is separated into several active regions 520 a by the trench 518 . Subsequently, as described in step 414, an active device 540 is fabricated on the active layer 504 to form a structure as shown in FIG. 8i.

In yet another embodiment, platform isolation can also be applied to multiple active regions with different thicknesses. For example, platform isolation can be applied to multiple active regions with at least two different thicknesses, and is not limited to the application of active regions with a single thickness. In this embodiment, the thickness of the active region isolated by the mesa isolation is in the range of 5 Å to 1000 Å.

It can be seen from the preferred embodiments of the utility model described above that the application of the utility model has the following advantages. The utility model is provided with platform isolation in the active area with thinner active layer, and with shallow ditch isolation in the active area with thicker active layer. Furthermore, the present invention teaches an isolation structure for an active region with a thin active layer and a manufacturing method thereof, wherein the isolation structures are separate and simple, and can avoid the disadvantages of the prior art. Therefore, the problem of using a specific isolation process in regions with different active layer thicknesses is avoided.

Therefore, it can be seen from the above-mentioned preferred embodiments of the present invention that the advantage of applying the present invention is to provide platform isolation in a part of the SOI chip with multiple active layer thicknesses.

Another advantage of the present invention is to provide existing isolation regions, such as shallow trench isolation regions, for a portion of an SOI chip with multiple active layer thicknesses.

Yet another advantage of the present invention is to provide platform isolation for multiple active regions having different active layer thicknesses.

However, the above descriptions are only detailed descriptions and accompanying drawings of specific embodiments of the present utility model, and are not intended to limit the utility model and its features. All equivalent modifications or changes should be included in the claims of the present utility model.

Claims (10)

1. A semiconductor-on-insulator chip, characterized in that it comprises at least: A semiconductor layer covers an insulating layer; A first region with a first thickness is located in the semiconductor layer, and the first region includes at least a plurality of first active regions, and the first active regions are defined by a shallow trench isolation method; and A second region with a second thickness is located in the semiconductor layer, and the second region includes at least several second active regions, and the second active regions are defined by a platform isolation method. 2. The semiconductor-on-insulator chip as claimed in claim 1, wherein the material of the semiconductor layer includes at least silicon. 3. The semiconductor-on-insulator chip as claimed in claim 1, wherein the material of the semiconductor layer includes at least silicon and germanium. 4. The semiconductor-on-insulator chip as claimed in claim 1, wherein the insulating layer is made of at least silicon oxide. 5. The semiconductor-on-insulator chip as claimed in claim 1, wherein the first thickness is greater than the second thickness. 6. A semiconductor-on-insulator chip, characterized in that it comprises at least: A semiconductor layer covers an insulating layer; A first region with a first thickness is located in the semiconductor layer, and the first region includes at least a plurality of first active regions, and the first active regions are defined by a mesa isolation method; and A second region with a second thickness is located in the semiconductor layer, and the second region includes at least several second active regions, and the second active regions are defined by the platform isolation method. 7. The semiconductor-on-insulator chip as claimed in claim 6, wherein the material of the semiconductor layer includes at least silicon. 8 . The semiconductor-on-insulator chip as claimed in claim 6 , wherein the semiconductor layer is made of at least silicon and germanium. 9. The semiconductor-on-insulator chip as claimed in claim 6, wherein a material of the insulating layer includes at least silicon oxide. 10. The semiconductor-on-insulator chip as claimed in claim 6, wherein the first thickness is greater than the second thickness.

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