CN2612071Y - Package structure for chip - Google Patents

Abstract

A chip packaging structure, at least comprising: a multilayer interconnection structure, with a top surface and a corresponding bottom surface, and the multilayer interconnection structure also has an internal circuit, and the internal circuit also has a plurality of joints a pad located on the bottom surface of the multilayer interconnect structure; at least one chip configured on the top surface of the multilayer interconnect structure and electrically connected to the internal circuit of the multilayer interconnect structure; and a The support base plate is made of insulating material, and the support base plate is disposed on the bottom surface of the multilayer interconnection structure, and the support base plate further has a plurality of first openings, which respectively expose the corresponding bonding pads one.

Description

Chip package structure

technical field

The utility model relates to a chip packaging structure, and in particular to a chip packaging structure using a hard support base plate made of insulating material.

Background technique

Flip Chip Interconnect Technology (FC for short) uses an area array to arrange multiple die pads on the active surface of the die. And form bumps (bumps) on the chip pad, and then flip the chip (flip), and then use these bumps to electrically and mechanically connect the chip pad of the chip to the contact on the carrier (carrier), The chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the internal circuit of the carrier. It is worth noting that because the flip-chip bonding technology (FC) is applicable to high-pin-count (High Pin Count) chip packaging structures, and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, the flip-chip bonding Technology has been widely used in the field of chip packaging. Commonly used chip packaging structures of flip chip bonding technology include flip chip ball grid array (Flip Chip Ball Grid Array, FC/BGA) and flip chip pin grid array (Flip Chip Pin Grid Atray, FC/PGA) and other types of chip packaging structures.

Please refer to FIG. 1 , which shows a schematic cross-sectional view of a conventional flip-chip ball array chip packaging structure. The chip package structure 100 includes a substrate 110 , a plurality of bumps 120 , a chip 130 , and a plurality of solder balls 140 . Wherein, the substrate 110 has a top surface 112 and a corresponding bottom surface 114, and the substrate 110 further has a plurality of bump pads 116a and a plurality of ball pads 116b. In addition, the chip 130 has an active surface (active surface) 132 and a corresponding back surface 134, wherein the active surface 112 of the chip 130 generally refers to the side of the chip 130 with active components (active device) (not shown) , and the chip 130 has a plurality of chip pads 136, which are disposed on the active surface 132 of the chip 130, and are used as the medium of the signal input and output of the chip 130, wherein the positions of these bump pads 116a correspond to these chip pads respectively 136 position. In addition, the bumps 120 are respectively electrically and mechanically connected to one of the chip pads 136 and one of the corresponding bump pads 116a. Moreover, the solder balls 140 are respectively disposed on the solder ball pads 116b for electrical and mechanical connection to external electronic devices.

Please also refer to FIG. 1, the existing chip packaging manufacturing process is to complete the internal circuit 118 and the contacts 116a, 116b of the substrate 110, then assemble the chip 130 on the surface of the substrate 110, and then apply an underfill 150 Fill the space enclosed by the top surface 112 of the substrate 110 and the active surface 132 of the chip 130 to protect the exposed parts of the bump pad 116a, the chip pad 136 and the bump 120, and buffer the substrate 110 and the chip at the same time The phenomenon of mismatch of thermal strain (thermal strain) generated between 130 and 130 when heated. Therefore, the chip pad 136 of the chip 130 will be electrically and mechanically connected to the bump pad 116a of the substrate 110 through the bump 120, and then routed down to the bottom of the substrate 110 through the internal circuit 118 of the substrate 110. The solder ball pads 116b on the bottom surface 114 are finally electrically and mechanically connected to external electronic devices through the solder balls 140 on the solder ball pads 116b.

In consideration of improving the operation speed of the chip and reducing the manufacturing cost of the chip, both the area of the chip and the gap between the chip pads must be gradually reduced, which means that the density of the chip pad will be relatively gradually increased. Therefore, when a chip with a high-density chip pad adopts a flip-chip (FC) type and is packaged with a ball grid array (BGA) or pin grid array (PGA) at the same time, due to the adjacent chips of the chip The pitch of the pads is very small. At this time, a substrate with high-density bump pads and fine circuits must be used, so that the chip can be arranged on the top surface of the substrate in a flip-chip bonding manner, and the internal circuit of the substrate can be rewound. The chip pads of the chip are extended and distributed to the bottom surface of the substrate, and then through contacts such as balls or pins located on the bottom surface of the substrate, the chip can finally be electrically connected to external electronic devices.

As mentioned above, the current common materials of flip-chip ball grid array (FC/BGA) or flip-chip pin grid array (FC/PGA) substrates include ceramics and organic materials. An organic substrate (organic substrate) in which an organic material is used as a material of a dielectric layer is relatively common. It is worth noting that since the organic substrate is severely affected by the thermal expansion of the dielectric layer, the line width and line spacing of the organic substrate that can be mass-produced today can only reach 25 microns and 25 microns, respectively. At the same time, the panel size of the uncut organic substrate that can be mass-produced today can only reach 610×610 square millimeters. However, as the density of die pads of chips increases gradually, under the consideration of large-scale mass production, how to package such chips with high-density die pads with low-cost substrates is an urgent need for the current chip packaging industry. One of the major issues to be solved.

Utility model content

In view of this, the task of the present utility model is to provide a chip packaging structure, which can provide a multilayer interconnection structure of high-density solder pads (bump pads) and fine lines, and can effectively reduce the manufacturing cost of the chip packaging structure. .

In order to accomplish the above tasks, the utility model provides a chip packaging structure, which at least includes: a multilayer interconnection structure with a top surface and a corresponding bottom surface, and the multilayer interconnection structure also has an internal circuit, And the internal circuit also has a plurality of bonding pads, which are located on the bottom surface of the multilayer interconnection structure; at least one chip is arranged on the top surface of the multilayer interconnection structure, and is electrically connected to the multilayer interconnection structure. The internal circuit of the wire structure; and a supporting base plate, the material of which is insulating material, and the supporting base plate is arranged on the bottom surface of the multi-layer interconnection structure, and the supporting base plate further has a plurality of first openings, which respectively expose one of the bond pads to which it corresponds.

In order to achieve the above purpose of the utility model, the utility model proposes a chip packaging structure, which mainly includes a multi-layer interconnection structure (multi-layer interconnection structure), at least one chip, and an isolation base layer ) and a support base plate. Wherein, the multilayer interconnection structure has a top surface and a corresponding bottom surface, and the multilayer interconnection structure further has an inner circuit (inner circuit), and the inner circuit further has a plurality of bonding pads, which are located in the multilayer The bottom surface of the wiring structure. In addition, the chip is arranged on the top surface of the multilayer interconnection structure, and is electrically connected to the internal circuit of the multilayer interconnection structure. In addition, the isolation bottom layer and the support base plate are arranged on the bottom surface of the multilayer interconnection structure, and the isolation base layer further has a plurality of second openings, and the support base plate further has a plurality of first openings, which are respectively connected to the corresponding ones. One of the second openings respectively exposes one of the corresponding bonding pads.

In order to achieve the above purpose of the utility model, the utility model proposes a chip packaging manufacturing process, including (a) providing a support base plate, the support base plate has a top surface and a corresponding bottom surface; (b) forming a multi-layer interconnection The line structure is on the support base plate, and the multilayer interconnection structure has an internal circuit, and the internal circuit further has a plurality of bonding pads, which are located on a side of the multilayer interconnection structure close to the support base plate; (c) disposing at least A chip is on the side of the multilayer interconnect structure away from the support base, and the chip is electrically connected to the internal circuit of the multilayer interconnect structure; (d) forming a plurality of first openings on the support base, and these first The openings respectively expose one of the corresponding bonding pads.

According to the preferred embodiment of the present utility model, the material of the above-mentioned support base plate is a hard insulating material such as glass (glass), quartz (quartz) or ceramic (ceramic), and the method of forming the first opening on the support base plate, Including ultrasonic perforation, laser burning or etching, etc. In addition, in the chip packaging structure, the chip is electrically connected to the internal circuit of the multilayer interconnection structure by means of flip chip bonding, wire bonding or thermocompression bonding. Moreover, a plurality of contacts can be formed on the side of the support base far away from the chip, and these contacts are respectively connected to one of the corresponding bonding pads, wherein the contacts are solder balls, pins or electrode bumps, for example.

Therefore, the utility model utilizes the manufacturing technology and production machine of thin film transistor liquid crystal display panel (TFT-LCD panel) or integrated circuit (IC), in the large-area and high flatness that take glass, quartz or pottery as material Form a multilayer interconnection structure with high-density solder pads (bump pads) and fine lines on the support base plate, and then place the chip on the top surface of the multilayer interconnection structure by flip-chip bonding, and A plurality of openings are formed on the bottom surface of the supporting base, and finally the contacts are arranged in the openings of the supporting base and electrically connected to the bonding pads of the multilayer interconnection structure, thereby completing the chip packaging manufacturing process of the present invention.

In order to make the above and other purposes, features, and advantages of the present utility model more obvious and understandable, a preferred embodiment is specifically cited below, and is described in detail as follows in conjunction with the accompanying drawings:

Description of drawings

FIG. 1 shows a schematic cross-sectional view of a conventional flip-chip ball array chip packaging structure; and

2A-2G sequentially illustrate a schematic flow chart of a chip packaging manufacturing process according to a preferred embodiment of the present invention.

Explanation of reference numbers

100: Chip package structure 110: Substrate

112: top surface 114: bottom surface

116a: bump pad 116b: solder ball pad

120: Bump 130: Chip

132: active surface 134: back

136: chip pad 140: solder ball

150: primer

200: Chip package structure 202: Support base plate

202a: First opening 204: Isolate the bottom layer

204a: Second opening 206: Multi-layer interconnection structure

206a: top surface 206b: bottom surface

208: wire layer 208a: bump pad

208b: bonding pad 210: dielectric layer

212: Conductive plug 214: Internal wiring

216: chip 216a: active surface

216b: Back side 218: Chip pad

220: Bump 230: Contact

Detailed ways

2A-2G sequentially illustrate a schematic flow chart of a chip packaging manufacturing process according to a preferred embodiment of the present invention. First, as shown in FIG. 2A , a support base 202 is provided, which is made of an insulating material, such as glass, quartz or ceramics, and the surface of the support base 202 must have a relatively high level of co-planarity. Then, as shown in FIG. 2B , an isolation bottom layer 204 is formed on the support base plate 202, and the surface of the isolation bottom layer 204 can be selectively planarized, so that the surface of the isolation bottom layer 204 also has a higher level of flatness, wherein the isolation bottom layer The material of 204 is, for example, polymer (polymer), polyester (polyestet), polyamide (PolyImide, PI), epoxy resin (epoxy resin), acrylic and benzo (and) cyclobutene (BenzoCycloButene, BCB ), etc., and the isolation bottom layer 204 can be formed on the support base plate 202 by means of film attachment or thin layer coating.

Next, as shown in FIG. 2C , a multilayer interconnection structure 206 is formed on the isolation bottom layer 204 . Wherein, the multilayer interconnection structure 206 mainly includes a plurality of patterned wiring layers 208, at least one dielectric layer 210 and a plurality of conductive plugs 212, and these wiring layers 208 are sequentially overlapped on the isolation bottom layer 204 , and the dielectric layer 210 is disposed between two adjacent wire layers 208, and these conductive plugs 212 respectively penetrate through the dielectric layer 210 and electrically connect the two adjacent wire layers 208, and these wire layers 208 and these The conductive plug 212 constitutes an internal circuit 214 . Wherein, the internal circuit 214 forms a plurality of bonding pads 208 b on the bottom surface 206 b of the multilayer interconnection structure 206 . In addition, the material of the wiring layer 208 is, for example, copper, aluminum and the alloys thereof, usually aluminum or copper, and the material of the dielectric layer 210 is, for example, silicon nitride, silicon oxide or epoxy resin. (epoxy resin) and other polymers. It is worth noting that the isolation bottom layer 204 can be selectively disposed on the support substrate 202. Therefore, when the multilayer interconnection structure 206 can be directly formed on the support substrate 202, it is not necessary to configure the isolation bottom layer 204 on the support substrate 202. on the support base 202 , but such a situation is not shown in FIGS. 2B˜2G .

Also as shown in FIG. 2C, since the utility model utilizes related manufacturing techniques such as liquid crystal display panels or integrated circuits, to form this multilayer interconnection structure 206 on the isolation bottom layer 204, so that the multilayer interconnection The line width and line pitch of the internal lines 214 of the line structure 206 can be in the range of 1-50 microns, and especially in the range of 1-several microns. Therefore, compared with the existing substrate 110 that uses organic materials as the dielectric layer material shown in FIG. block pad) and finer lines. In addition, when forming the multilayer interconnection structure 206 on the isolation bottom layer 204, a passive component (not shown) may be disposed inside or on the top surface 206a of the multilayer interconnection structure 206, And electrically connected to the internal circuit 214 of the multilayer interconnection structure 206, or use the special winding design of the internal circuit 214 to form passive components such as capacitors and inductors.

Next, as shown in FIG. 2D, after completing the manufacturing process of the multilayer interconnection structure 206, a grinding machine can also be used to thin the thickness of the supporting base plate 202. Then, as shown in FIG. At least one chip 216 is on the side of the multilayer interconnect structure 206 away from the support base 202 , and the chip 216 is electrically connected to the internal circuit 214 of the multilayer interconnect structure 206 . Of course, the above-mentioned step of thinning the support base plate 202 can also be performed after disposing the chip 216 on the multilayer interconnection structure 206 . In addition, the chip 216 has an active surface 216 a and a back surface 216 b, and the chip 216 further has a plurality of chip pads 218 located on the active surface 216 a of the chip 216 . In addition, a plurality of bumps 220 are electrically and mechanically connected to one of the chip pads 218 and one of the corresponding bump pads 208a, so that the chips 216 can be arranged in multiple layers in the way of flip-chip bonding. above the interconnection structure 206 , and electrically connect the chip 216 to the internal circuit 214 of the multilayer interconnection structure 206 . Of course, the chip 216 can also be electrically connected to the internal circuit 214 of the multilayer interconnection structure 206 by wire bonding or thermal compression bonding.

Next, as shown in FIG. 2F , a plurality of first openings (opening) 202a are formed on the support base plate 202 by means of ultrasonic perforation, laser burning or etching, and after the formation of the plurality of first openings 202a, the same can be done. The second opening 204a is formed on the insulating bottom layer 204 in a manner. Wherein, the second openings 204a communicate with the corresponding ones of the first openings 202a respectively, and respectively expose the corresponding ones of the bonding pads 208b. Finally, as shown in FIG. 2G, a plurality of joints 230 are formed on the side of the support base 202 away from the chip 216, and these joints 230 are respectively connected to one of the corresponding bonding pads 208b, wherein the pins can be solder balls, Conductive structures such as pins or electrode bumps are arranged on the bottom surface of the chip package structure 200 in an area array.

In addition, as shown in FIG. 2G , after the contacts 230 are arranged on the bonding pads 208 b, the singulation operation can be performed to separate the single chip package structure 200 . Next, as shown in FIG. 2F , before disposing the contact 230 on the bonding pad 208 b, a singulation operation may be performed to separate the single chip package structure 200 . It is worth noting that since the chip packaging structure 200 of the present invention is suitable for packaging multiple chips 216 and can be electrically connected to each other through the internal circuit 214 of the multilayer interconnection structure 206, the chip packaging structure 200 will be able to Applied to multiple chip modules (Multiple ChipModule, MCM) and system in a single package (System In Package, SIP). Furthermore, the back surface 216b of the chip 216 can also be optionally configured with a heat sink (not shown), which is made of a material with good heat dissipation, such as copper, aluminum and these alloys, to increase the chip packaging. Heat dissipation performance of the structure 200 .

To sum up, the present invention can integrate the manufacturing technology and production machine of liquid crystal display panels or integrated circuits into the chip packaging manufacturing process of the present invention. It is worth noting that since the manufacturing technology of liquid crystal display panels and integrated circuits is very mature, under the condition of large-scale mass production, the chip packaging manufacturing technology of the present invention will be able to make the plane size larger than 610×610 On the support base plate with a square millimeter or more, a multi-layer interconnection structure with high-density solder pads (bump pads) and fine lines is formed at the same time, and then flip-chip bonding, or even wire bonding or thermocompression bonding In this way, the chip is arranged on the multilayer interconnection structure of the interconnection layer, so that the cost of the chip package using the glass substrate of the present invention is lower than that of the existing chip package using the organic substrate.

In addition, because the line width and line spacing of the wires that can be produced by the manufacturing technology of the liquid crystal display panel can reach 1 micron, or even less than 1 micron, so under the situation that the density of the chip pad is gradually increasing, this The utility model chip packaging manufacturing process will fully match the density of the chip pad, and provide high-density solder pads (bump pads) and a multi-layer interconnection structure with fine lines, and it is easier to control the multi-layer interconnection The unit electrical impedance of the wires of the structure, and these characteristics cannot be easily achieved by the existing chip packaging manufacturing process using organic substrates.

In addition, also because the line width and line spacing of the wires that can be produced by the manufacturing technology of the liquid crystal display panel can reach 1 micron, or even less than 1 micron, so the chip packaging manufacturing process of the present utility model can fully match the chip of the chip. The density of the pad corresponds to the multi-layer interconnection structure that provides high-density solder pads (bump pads) and fine lines, so the density of the chip pad of the chip will gradually increase, thus relatively reducing the area of a single chip, making The total number of chips that can be cut out of the same wafer will be relatively increased, so this will help to reduce the production cost of a single chip, thereby reducing the overall production cost of the chip package structure.

Although the utility model has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the utility model, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the utility model, so The protection scope of the present utility model should be defined by the appended claims.

Claims (10)

1. A chip packaging structure, characterized in that the structure at least includes: A multilayer interconnection structure has a top surface and a corresponding bottom surface, and the multilayer interconnection structure also has an internal circuit, and the internal circuit also has a plurality of bonding pads, which are located on the multilayer interconnection the bottom surface of the line structure; at least one chip, disposed on the top surface of the multilayer interconnection structure, and electrically connected to the internal circuit of the multilayer interconnection structure; and A support base plate, the material of which is an insulating material, and the support base plate is disposed on the bottom surface of the multilayer interconnection structure, and the support base plate further has a plurality of first openings, which respectively expose the corresponding joints pad one. 2. The chip packaging structure as claimed in claim 1, further comprising an insulating bottom layer made of an insulating material, wherein the insulating bottom layer is disposed between the multilayer interconnection structure and the supporting base plate, And the isolation bottom layer further has a plurality of second openings, which respectively expose one of the corresponding bonding pads. 3 . The chip packaging structure according to claim 1 , wherein the support base is made of one of glass, quartz, and ceramics. 4 . 4 . The chip package structure according to claim 1 , further comprising a plurality of contacts, which are respectively connected to one of the corresponding bonding pads through the corresponding first openings. 5 . The chip package structure as claimed in claim 4 , wherein the contact points are one of solder balls, pins and electrode bumps. 5 . 6. The chip packaging structure according to claim 1, wherein the chip is electrically connected to the multilayer interconnect structure by one of flip chip bonding, wire bonding and thermocompression bonding. internal wiring. 7. The chip package structure according to claim 1, wherein the line width of the internal circuit is in the range of 1-50 microns. 8 . The chip package structure according to claim 1 , wherein the pitch of the internal circuit is in a range of 1-50 microns. 9. The chip packaging structure according to claim 1, further comprising at least one passive component disposed inside the multilayer interconnection structure and electrically connected to the multilayer interconnection structure of the internal line. 10. The chip package structure according to claim 1, further comprising at least one passive component disposed on the top surface of the multilayer interconnection structure and electrically connected to the multilayer interconnection structure. This internal line of the line structure.

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