CN2588451Y - 8-bit new structured microprocessor and multi-purpose chip circuit using same - Google Patents

Abstract

The utility model relates to an 8-bit novel framework microprocessor and an on-chip system multi-purpose chip circuit which takes the 8-bit novel framework microprocessor as a core. The core adopts a two-stage flow line and a Hafford-type structure. The number of an instruction set is 35, and the coding efficiency is high. The expansion of the instruction can be carried out very easily. The utility model is also integrated with a plurality of peripheral devices, such as an LCD controller, a driving circuit, a FLASH structural module converter, a hardware watch dog, an 8-bit scaling time keeping /an external counter, two 16-bit scaling timings, an external counter, a path CCP (capture/ comparison/ pulse width modulation). The utility model supports low power consumption sleep and awake modes, supports external interruption, and supports B port high 4-bit change interruption. The utility model has strong capability of processing interruption, and can process eight level interruption. A data storage device adopts a one port and an asynchronous low power consumption SRAM, and the storage depth is 256 * 8. A program storage device adopts an embedded type FLASH, and the storage depth is 4K * 16 bits. Addressing modes have modes of direct addressing, indirect addressing, immediate number addressing, etc. An electrified reset circuit and 22 bi-directional ports (the bi-directional ports can be expanded) are arranged in the chip. The utility model adopts an LQFP encapsulation, supports DFT design, and can operate in DC to 40 MHZ. The utility model can be used for the field of household electrical appliances.

Description

8 novel framework microprocessors and the multi-usage chip circuit that uses this processor

Technical field

The application belongs to the semiconducter IC design field generally, relates to the risc microcontroller field, have complete independent intellectual property right with 8 RISC, two stage pipeline structure CPU are core, the SOC of integrated numerous peripheral components (SOC (system on a chip)) chip.

Background technology

From current development of integrated circuits, the deep-submicron CMOS technology can make complicated microprocessor and some other module be integrated in on the chip piece, as: program storage, data-carrier store and peripheral complex logic device, can effectively utilize the most frequently used project organization and method in high-end 32 RISC (reduced instruction set computer) machine, and it is applicable to 8-bit microprocessor system cheaply, it is the SOC chip of core with the 8-bit microprocessor that this high performance-price ratio has been arranged, and can carry out more efficient code with the form of hardware.

In recent years, popularized round the SOC chip that with the risc architecture is core, they all have some common features: (1) most of instruction set scales are less and can not expand; (2) the great majority instruction all is an one-cycle instruction, is convenient to realize streamline like this; (3) the great majority instruction has set form, and order number and decoding are relatively simplified; (4) data channel height pipelining; (5) bigger register file has avoided the mistake degrees of data of round RAM to transmit; (6) integrated numerous peripheral components have reduced application system plate level complexity.But they some intrinsic complexity and defectives have also occurred: (1) instruction set can not be expanded; (2) pipelining segment and progression are more, have brought pipelining segment data dependence criterion complicacy, sometimes even have influence on the pipeline data throughput; (3) great majority make the systems programming flexibility ratio reduce greatly with SOC chip employing MASKROM (mask program storage) or OTP (but one-time programming program storage) that risc architecture CPU is core; (4) data-carrier store is multiplexing with program storage, does not have special register file.Even have, the specified register heap is not separated with general-purpose register yet, so just limited the raising of chip speed; (5) peripheral resource is less, and particularly performance is particularly outstanding aspect household electrical appliances; (6) do not support DFT design (towards the design of test).Therefore, most of chips have the instruction complexity, and structure is loaded down with trivial details, and travelling speed is lower, and the instruction extensibility is relatively poor, and characteristics such as compiler complexity are difficult to satisfy High-speed Control and the requirement of communicating by letter.

Summary of the invention

It is a kind of with 8 novel frameworks that the utility model provides, and two level production lines, reduced instruction microprocessor are the SOC chip of core, improve the 8-bit microprocessor travelling speed to reach, reduction instruction also has extensibility, realizes simplifying system architecture, simplifies the purpose of compiler.

First aspect of the present utility model is a kind of 8 novel framework microprocessors, and described processor comprises the storage of order register group, data channel, and wherein said processor also comprises:

Command decoder is used for the instruction of order register group the inside is deciphered, and makes relevant instruction operands and operational code effective;

Controller is used for producing various processing and control signal according to from described operational code of command decoder and operand.

Internal register stack relates to more inner registers commonly used, is convenient to controller and by data channel it is carried out fast access and read-write;

Arithmetic logical unit is used for carrying out arithmetic logical operation and shifting function according to operand and operational code from command decoder to the arithmetic logical operation operational code with from the data of register.

Second aspect of the present utility model is a kind of as the described microprocessor of first aspect, wherein also comprises clock generator, is used to produce four required phase clocks of streamline operation.

The third aspect of the present utility model is a kind of as the described microprocessor of first aspect, wherein also comprises internal stack, and instruction and internal interrupt result that it can be deciphered out according to command decoder are automatically carried out pop down and the processing of popping.

Fourth aspect of the present utility model is a kind of SOC multi-usage chip circuit, described chip circuit comprises program storage, asynchronous static data storer, clock generator, analog to digital converter, wherein, described chip circuit also comprises as described 8 the novel framework microprocessors of first aspect.

The 5th aspect of the present utility model is a kind ofly wherein also to comprise the LCD driving circuit as the described SOC multi-usage of fourth aspect chip circuit, is used for the AC driving liquid crystal display.

The 6th aspect of the present utility model is a kind ofly wherein also to comprise the CCP circuit as the described SOC multi-usage of fourth aspect chip circuit, is used for external signal is caught, relatively, width modulation.

Description of drawings

Fig. 1 represents the utility model chip system structural drawing.

Fig. 2 illustrates the realization reduced instruction set computer, two stage pipeline structure schematic diagrams.

Fig. 3 illustrates and realizes DFT design concept figure.

Fig. 4 illustrates the utility model chip system block diagram.

Fig. 5 illustrates this chip register heap mapping graph.

Fig. 6 illustrates ADC (digital-to-analog conversion) channel selecting figure.

Fig. 7 illustrates this chip analog-digital conversion control circuit figure.

Fig. 8 illustrates this chip core CPU block diagram.

Fig. 9 illustrates ALU (arithmetic logical unit) circuit diagram.

Figure 10 illustrates the Tmr0 counting circuitry.

Embodiment

It is a kind of reliable that the utility model provides, effective system architecture, adopt 35 can expand reduced instruction set computer (can expand to 70 as required), two level production lines, Harvard's type structure has realized that travelling speed is fast, instruction is simple, system architecture is distinct, and the simple purpose of compiler can satisfy High-speed Control and the requirement of communicating by letter fully in good time.This chip system block diagram as shown in Figure 4,8 novel frameworks 7 are RISC, two stage pipeline structure CPU nuclear, are cores of the present utility model.

Specifically with reference to figure 8, wherein, clock generator 14 and reset circuit 15 produce four phase clocks and various reset signal respectively.43 pairs of internal stack 29 of clock generator 14 generation clock signals, internal interrupt processor 28, instruction pointer counter 27 carry out clock synchronization; The 59 pairs of command decoders of clock signal 32 that produce carry out clock synchronization; Go back clocking 38,39,41 simultaneously and respectively arithmetic logical unit ALU37, internal register stack 35, work register W36 are carried out clock synchronization.These clock signals have just constituted two level production lines operation rhythm as shown in Figure 2, constitute four sections pipelining segments, and the data dependence that has significantly reduced pipelining segment is judged, has also reduced the streamline complexity simultaneously.Reset circuit 15 produces reset signal 42, instruction pointer counter 27, internal interrupt processor 28, internal stack 29, MUX 30 are resetted, it also produces reset signal 62, order register group 31 is resetted, the utility model chip order register group 31 is under reset situation, always pointing to 0 address is first address, and reset circuit 15 also produces reset signal 60,52,61, respectively command decoder 32, internal register stack 35, work register W36 is resetted.

Resetting has original state, and chip can more effectively be worked.At first, reset circuit 15 produces reset signal, at this moment, instruction pointer counter 27 is 0, and MUX 30 selection instruction pointer counters 27, instruction pointer counter 27 output signals 57 (this signal is 13 bit address pointers), this moment, signal 57 was 0, the first address place of directional order registers group 31, take out first address place instruction code, send signal 58 to, at this moment, signal 58 is 14 routine data codes, the pipelining segment operation of representing CPU to finish to get finger.Command decoder 32 receives signal 58 routine data codes and begins decoding, and the decoding back produces three major types control signal 56, that is: register manipulation class control signal, bit manipulation class control signal, count immediately and control class signal, at this moment, CPU has finished the pipelining segment operation of decoding.Controller 33 is according to this three major types signal, produce positive logic control signal 47,50,55,48,49,51, difference control data passage 34, internal register stack 35, arithmetic logical unit ALU 37, instruction pointer counter 27, internal interrupt processor 28, internal stack 29, MUX 30, work register W36.These control signals are very important.Sort out with regard to the related control signal of the utility model below, it is fout_re that signal 47 mainly contains two, fin_we.Wherein fout_re represents that from register file sense data enable signal, fin_we represents data are write in the register file, and these two signals have been finished getting the register manipulation number and writing the action of register manipulation number in the pipelining segment jointly.

Register file is referring to Fig. 5, the general-purpose register that it comprises special D type register file and realizes with SRAM.Signal 50 is used for distinguishing special D type register file and general-purpose register, its signal is: special_reg_flag, when its value is " 1 ", the visit of its presentation directives be that the inner specified register of realizing with special D flip-flop is piled, when its value when " 0 ", its presentation directives's visit be outside general-purpose register.Signal 51 expressions are write into work register 36 enable signals with data.Signal 48 be illustrated in execute judged whether earlier after the instruction to interrupt and whether have instruction pointer internally storehouse 29 eject and be pressed into, do not enable if there is above-mentioned situation to take place just to provide counter 27, allow instruction pointer point to next bar instruction.Signal 49 is illustrated in internal interrupt processor 28 interruption, and internal stack 29 has under the situation that ejects the address carries out the internal address pointer priority ordering, determines MUX 30 one of them address pointer of selection.The various operands that arithmetic logical unit ALU37 is given in signal 55 expressions comprise logic and Arithmetic Operator.ALU37 carries out arithmetic logical operation according to signal 55 operands, and calculated result arrived data channel 34 by 8 position datawires, according to various control signals, the result is write back register file 35 (comprising general-purpose register and specified register heap) or work register W36 through data channel 34.

Arithmetic sum arithmetic logic unit 37 is specifically with reference to figure 9: it mainly finishes the operation of the pipelining segment of arithmetic logical operation among the CPU.2 select 1 MUX 63, be input as work register value W36 and constant 8 ' h1, MUX 63 is output as alub, equally, 2 select 1 MUX 66, its input k represents several immediately from what instruct direct decoding to come, fout represents the data exported in register file, the selection of these inputs need be judged according to the instruction of current execution, MUX 66 is output as alua, and it imports into arithmetic logical operation part on the one hand, on the other hand, select 1 MUX 64 by 2, the arithmetic logical operation part is advanced in input, and MUX 64 selects signal to select with alubf, and the alubf signal is mainly produced by clear command, if have reset signal to produce, import into arithmetic logical operation part 65 with regard to gating alua.Arithmetic logical operation part 65 is the most crucial parts of arithmetic logical operation, and it includes: shift operation, and with non-, or non-, XOR, logical operation such as non-grade also has addition, subtraction, multiplication, comparison operation simultaneously.These computings are according to opcode[3: 0] select, 3-8 code translator 67, it is mainly used to carry out bit manipulation.The another one signal " status[2] " be that carry or borrow are used for carrying out addition, subtraction, shift operation.65 outputs of arithmetic logical operation part have three kinds of signals promptly: operation result aluout, computing zero flag aluz, computing carry flag alucout.

The utility model also provides a kind of SOC multi-usage circuit that uses above-mentioned 8 novel framework microprocessors.Specify the structure of this chip below in conjunction with accompanying drawing.

At first with reference to figure 4: this is the utility model chip top figure.

Asynchronous static data storer 1, storage depth are 176, and figure place is 8, and it is the part of register file, represents general-purpose register, and it separates with the specified register heap, and specified register forms with D-type edge-trippered flip-flop.Asynchronous static data storer 1 has been formed the general-purpose data register circuit with Sram interface circuit 3.Owing to asynchronous static data storer 1 is to generate with standard RAM COMPILER, its address is continuous between 0～175, and simultaneously, the register file addressing space is continuous between 0～255 in the CPU nuclear, and the utility model register file is divided into two districts: 0 district and 1 district.There are 128 registers in each district, comprises specified register and general-purpose register.Because in CPU nuclear, specified register is distributed in different districts and data space, therefore need to carry out map addresses with a kind of interface circuit 3, see Fig. 5.In the register file, 0 district is from 8 ' h00 to 8 ' h1f, and 1 district all realizes with D flip-flop from 8 ' h80 to 8 ' haf.0 district is mapped to asynchronous data storer heap 1 from 8 ' h20 to 8 ' h7f: from 8 ' h00 to 8 ' h5f, 1 district is mapped to asynchronous data storer heap 1 from 8 ' hb0 to 8 ' hff: from 8 ' h60 to 8 ' haf.

Program storage 2, its storage depth are 8K, and program storage 2 element lengths are 14.

This program storage 2 adopts asynchronous system and CPU nuclear to carry out exchanges data.It adopts third party FLASH storer, and adopting the benefit of FLASH is repeatedly to programme, and is easy to wipe and reprogrammed, can improve application system programming flexibility ratio.As can see from Figure 4, the utility model adopts separately Harvard's type structure of program storage 2 and data-carrier store 1.

ADC channel to channel adapter 4, it and analog to digital conversion interface 5, FLASH structural module converter 6 can be finished the conversion from the analog quantity of outside input to digital quantity together, and the data after will changing are sent to 8 novel framework 7 (RISC, two stage pipeline structure CPU nuclear), simultaneously, CPU nuclear 7 is with control signal: break discharge signal, ADC channel selecting signal, ADC reset signal, ADC enabling signal, ADC cut-off signals and pass to analog to digital converter 6 by A/D interface 5.ADC channel selecting 4 is with reference to figure 6, and it mainly is 8 to select 1 selector switch, but only uses wherein five of outer perisotomice.Analog to digital conversion interface 5 is with reference to figure 7, it mainly is made up of three registers, analog to digital conversion control register 0 17, analog to digital conversion control register 1 18, analog to digital conversion result register 19, the clock that these special D type registers adopt clock generator 14 to produce triggers, and clock generator 14 produces clock 25 (the 4th phase clock) and 26 (major clocks) arrive analog to digital conversion control register 0 17, modulus control transformation register 1 18, modulus result translation register 19 by MUX 16.Analog to digital conversion control register 0 17 and analog to digital conversion control register 1 18 produces control signals: analog to digital converter enabling signal 20, break discharge signal 21, analog to digital conversion channel selecting signal 22, analog to digital conversion reset signal 23, remove to control FLASH structural module converter 6 with these signals.Behind FLASH structural module converter 6 EOCs, will send a look-at-me to analog to digital conversion control register 017, the result after will changing simultaneously sends into analog to digital conversion result register 19.

Lcd controller 8 and lcd driver 9 have been formed the LCD driving circuit jointly, lcd controller 8 major functions are: storage is from the CPU nuclear 7 code-point logic levels that send and control signal such as LCD cut-off signals, reset signal, clock signal and some register read write signals, simultaneously some digital signals such as COM signal and SEGMENT signal are sent into lcd driver 9, the lcd driver 9 main outputs that realize simulating signal COM and SEGMENT signal.For fear of the damage of liquid crystal, adopt AC driving method usually.

In Fig. 4, Tmr0/wdt 10, Tmr1 11, Tmr2 12, ccp 13 is exterior I/O circuit, they are examined 7 by control signals such as read-write bus and read-writes with CPU and contact directly, visiting these I/O circuit is the same when piling with access register, by read-write control signal, they are carried out read-write operation.TMR0/WDT10 mainly realizes 8 bit timings counting and outside rising edge; the negative edge counting; independently carry out simultaneously the house dog counting; when counting; can realize the calibration counting; when realizing the calibration counting; TMR0 and WDT can only choose one of them and that is to say that scaler can only uniquely be used; physical circuit is seen Figure 10; " 68 "; " 69 "; " 70 " all are 2 to select 1 MUX; the signal of these selector switchs is all controlled by specified register option; it is outside rising edge counting and outside negative edge counting that MUX 68 is used for selecting the external counting triggering mode; MUX 69 is used for selecting counting mode to count or external counting with internal clocking; when being used for selecting counting, MUX 70 adopt scaler still not adopt scaler; synchronizing circuit 71 usefulness internal clockings carry out synchronously count value; after carrying out synchronously; value is sent into specified register TMR0, overflow interruption, just change over to and overflow Interrupt Process 74 if counting takes place tmr0; the WDT counting mode is similar with TMR0; different is after the WDT counting overflows, can produce reset signal, and chip circuit is played a protective role." 12 " expression TMR2 among Fig. 4, it mainly realizes 8 calibration countings, the same TMR0 of method of counting, " 11 " expression TMR1, it mainly realizes 16 calibration countings, the same TMR2 of method of counting, " 13 " expression CCP device, it mainly realizes the catching of external signal, relatively and realize pulse-width signal.

In Fig. 4, " 14 " and " 15 " label is represented clock generator circuit and reset circuit respectively, and clock generator 14 provides all clock signals for the utility model, as: CLK1, CLK2, CLK3, CLK4, test_clk.Reset circuit 15 provides the reset signal that is necessary for chip: as electrify restoration circuit, startup back off timer, WDT reset signal, external reset signal.

With reference to Fig. 1, the following describes the working condition of this chip.At first, instruction counter PC (13) takes out instruction from the FLASH program storage, then instruction is delivered among the order register IR and stored, correspondingly decipher then, because instruction divides three major types: the instruction of byte manipulation class, bit manipulation instruction, number operation immediately and the instruction of control operation class, so during decoding, also can be divided into three major types, with reference to figure 8, after decoding is finished, carry out read register or be sent to ALU (arithmetic logical unit), finish the arithmetic sum logical operation at ALU then, then operation result is transmitted back to work register and data-carrier store (8) counting immediately, simultaneously the PC pointer is added one, take out next bar instruction, so constantly circulation forms pipelining.

Because the instruction set major part is an one-cycle instruction, than being easier to realize streamline, realize the streamline basic circuit as shown in Figure 2: at first external clock is divided into four phase clocks to external clock through clock generator, is respectively: Q1, Q2, Q3, Q4.In the Q1 phase clock, get finger and decoding, and carry out Interrupt Process.In the Q2 phase clock, carry out the read register operation, in the Q3 phase clock, carry out the arithmetic sum logical operation, in the Q4 phase clock, calculated result is write back work register and general-purpose register, simultaneously with next bar instruction of PC pointed and open the interruption.Because the utility model adopts full Synchronization Design, timing closure compares faster, and does not have the coupling on the sequential each other, has introduced the clock trees method of adjustment in Front-end Design and layout design stage, has improved the chip travelling speed greatly.

For improving chip reliability, when design, introduced the DFT method for designing, specifically realize with scan chain, specific implementation principle such as Fig. 3: because the utility model design is to adopt synchronous design method, the level latch is seldom arranged, at this moment all triggers in the circuit can be transformed into multiplexing trigger, when TEST_EN is logic level " 1 ", at this moment MUX is chosen the scan chain data input, simultaneously, all sweep triggers are linked at form scan chain together, at this moment testable fault, when TEST_EN is logic level " 0 ", at this moment MUX is selected the normal data input, this chip adopts the DFT design, and test coverage can reach 99%, and fault coverage reaches more than 98%, the realization concrete steps are: at first at system design stage, must adopt Synchronization Design and the design of pure combinational circuit, avoid the level latch design as far as possible, this chip mainly adopts synchronizing circuit and the design of pure combinational circuit, the level latch design seldom appears, secondly, in synthesis phase, Scan Architecture is set, scan clock need add-scan at compile option.

At this moment, chip circuit process sequential, speed, area-constrained.At last, in integrated environment, carry out to insert the scan chain order, carry out test simulation simultaneously, can produce the report of dependence test coverage rate and test failure coverage rate, with this as estimate chip reliability according to one of.

In sum, be the multi-usage chip of core by 8-bit microprocessor, can be widely used in field of household appliances: as air-conditioning, refrigerator, washing machine, televisor.

The description to preferred embodiment that the front provided is in order to make those skilled in the art can finish or use the utility model.For those skilled in the art, various modifications will be conspicuous to these embodiment, and not use under the creationary situation, can be applied to other embodiment in this defined General Principle.Like this, the utility model is not to be confined to the embodiment that goes out shown here, but meet with at principle and novel feature the wideest related category that this disclosed.

Claims (7)

1, a kind of 8 novel framework microprocessors, described processor comprises order register group, data channel, it is characterized in that, described processor also comprises:

Command decoder is used for the instruction of order register group the inside is deciphered, and makes operand and operational code relevant in the instruction effective;

Controller is used for producing various processing and control signal according to described operational code and operand from command decoder;

Internal register stack relates to more inner registers commonly used, is convenient to controller and by data channel it is carried out fast access and read-write;

Arithmetic logical unit is used for carrying out logic and arithmetical operation operation according to operand and operational code from command decoder to the arithmetic logical operation operational code with from the data of register file.

2, microprocessor as claimed in claim 1 is characterized in that, also comprises clock generator, is used to produce four phase clocks of streamline operation.

3, microprocessor as claimed in claim 1 is characterized in that, also comprises internal stack, and instruction and internal interrupt result that it can be deciphered out according to command decoder are automatically carried out pop down and the processing of popping.

4, a kind of SOC multi-usage chip circuit, described chip circuit comprises program storage, asynchronous static data storer, clock generator, analog to digital converter, it is characterized in that described chip circuit also comprises 8 novel framework microprocessors as claimed in claim 1.

5, SOC multi-usage chip circuit as claimed in claim 4 is characterized in that, also comprises the LCD driving circuit, is used for the AC driving liquid crystal display.

6, SOC multi-usage chip circuit as claimed in claim 4 is characterized in that, also comprises the CCP circuit, be used for external signal is caught, relatively, width modulation.

7, SOC multi-usage chip circuit as claimed in claim 5 is characterized in that, also comprises the CCP circuit, be used for external signal is caught, relatively, width modulation.

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