CN2582331Y - Circuit board able to inspect order of laminate - Google Patents
Circuit board able to inspect order of laminate Download PDFInfo
- Publication number
- CN2582331Y CN2582331Y CN 02282616 CN02282616U CN2582331Y CN 2582331 Y CN2582331 Y CN 2582331Y CN 02282616 CN02282616 CN 02282616 CN 02282616 U CN02282616 U CN 02282616U CN 2582331 Y CN2582331 Y CN 2582331Y
- Authority
- CN
- China
- Prior art keywords
- circuit board
- conductive layer
- cue mark
- verified
- observation hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003825 pressing Methods 0.000 claims description 18
- 238000003475 lamination Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 3
- 238000012795 verification Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 69
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Images
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model relates to a circuit board which can verify the order of superposed layers, which is a multilayer circuit board. The utility model is characterized in that the same relative positions of surface conductive layers at the top and at the bottom of the multilayer circuit board are respectively provided with one viewing hole. At least one viewing region is arranged in the viewing holes. One verification structure is respectively arranged in the viewing region. The same positions of every three continuous conductive layers are respectively provided with one upper shielding block, one index mark and one lower shielding block in order except for the top and the bottom surface conductive layers according to the order of the superposed conductive layers of the circuit board. After the circuit board is pressed and processed, the utility model can judge whether the order of the superposed layers of the circuit board is correct through the shielding state samples which are displayed by the index marks in the viewing holes.
Description
Technical field
The utility model relates to a kind of circuit board, and particularly a kind of multilayer circuit board can be in order to distinguish the circuit board of the verified laminated layer sequence that laminated layer sequence is whether correct after pressing is made.
Background technology
Board design manufacturer is after circuit is finished design at present, often need the design picture and text are fabricated to the circuit board finished product by circuit board manufacturer, especially the present multilayer circuit board of widespread on the market is made 6-layer circuit board or 8-layer printed circuit board by the conductive layer pressing of six layers or eight layers usually; And on the whole multilayer circuit board is made of the pressing of a plurality of conductive layer institute, this conductive layer is respectively in order to constitute signal lead layer (Signal), ground plane (Ground) and bus plane (Power), wherein between aforesaid each conductive layer and be provided with an insulating barrier, to prevent the interference of each interlayer power supply short circuit or signal; Certainly, for multilayer circuit board, because the circuit board order of each conductive layer lamination during fabrication has relevant with the design of circuit mutually, so when laminated layer sequence is wrong, tend to cause the mistake in the circuit connection and open circuit, the interruption of circuit signal, even the interference of electromagnetism between circuit, cause the flaw of product on producing, and because of the circuit board of lamination mistake also can produce the interruption of power supply signal or the possibility of electromagnetic interference after assembling processing, can't be as the raw material on producing, and then waste a large amount of production costs and time, therefore how in the manufacture process of circuit board, after pressing processing, can judge in advance simply whether the laminated layer sequence in its circuit board is correct, to avoid the meaningless in the use waste of circuit board, promptly be subjected to relevant industry for a long time and think deeply about, and be eager improvement and improvement.
Summary of the invention
The utility model is the circuit board that a kind of verified laminated layer sequence will be provided, make multilayer circuit board by pressing with solution after, can easily verify the technical problem that laminated layer sequence is whether correct.
It is such solving the problems of the technologies described above the technical scheme that is adopted:
A kind of circuit board of verified laminated layer sequence is to be a multilayer circuit board, it is characterized in that:
The conductive layer on the top layer of this multilayer circuit board offers at least one observation hole; Constitute at least one sight viewed area in this observation hole;
One checking structure is the conductive layer order according to circuit board institute lamination, and the conductive layer of skim-coat is sequentially provided with occlusion areas in outer every continuous three layers conductive layer same position place, a cue mark reaches occlusion areas;
Wherein be respectively arranged with this checking structure in this each sight viewed area, and adjacent checking structure staggers one deck conductive layer one by one downwards all in regular turn and is provided with, through the circuit board of pressing processing, with the laminated layer sequence that covers aspect decision circuitry plate of cue mark demonstration in the observation hole;
This observation hole is the same relative position of the conductive layer place that is opened in the top layer up and down of multilayer circuit board, and constitutes at least one sight viewed area in each observation hole;
Each be positioned at cue mark up and down on the conductive layer of one deck set upper and lower occlusion areas just can be shielded in half of this sights viewed area area, and be to be mutually to misplace and be provided with;
Occlusion areas and cue mark are respectively that conductive layer is constituted with etching mode up and down;
This cue mark is to be made of one of the two of literal and pattern, and each cue mark is required to be inequality;
The correct circuit board of this lamination carries out pressing processing, and it is that occlusion areas is covered respectively up and down that the cue mark that shows in its observation hole upper and lower just can have part cue mark zone;
This sight viewed area is to be one vertically to arrange;
This observation hole is rectangular aspect setting.
The utility model is to provide a kind of circuit board of verified laminated layer sequence, it mainly is respectively to offer an observation hole in the circuit board upper and lower surface, and constitute an identification pattern or mark respectively being positioned in the middle of the circuit board to be on the signal lead layer (Signal), ground plane (Ground), bus plane (Power) at same position place with observation hole, whether make circuit board after carrying out pressing processing, can be correct by the pattern state identification circuit plate laminated layer sequence in the observation hole; Avoid circuit board simultaneously after assembling electronic component, mistake because of laminated layer sequence, and cause flaw and the electromagnetic interference of circuit signal in transmission, thereby solved make multilayer circuit board by pressing after, can easily verify the technical problem that laminated layer sequence is whether correct.
The utility model is simple in structure, it mainly is respectively to offer an observation hole in the same relative position place of top layer conductive layer up and down at circuit board, and in observation hole, constitute at least one sight viewed area, be respectively arranged with a checking structure in this sight viewed area, it is conductive layer order according to circuit board institute lamination, be sequentially provided with occlusion areas in every continuous three layers conductive layer same position place, one cue mark reaches occlusion areas, make when circuit board after pressing is processed, can by this cue mark in the observation hole shown whether cover the laminated layer sequence that aspect comes the decision circuitry plate correct, and tool practicality.
Description of drawings
Fig. 1 is the generalized section of known six layers of motherboard.
Fig. 2 is that the utility model is used in the three-dimensional exploded view on the 6-layer circuit board.
Fig. 3 is that Fig. 2 sees the schematic diagram of looking by the circuit board top after pressing processing.
Fig. 4 is that the utility model is used in the three-dimensional exploded view on the 8-layer printed circuit board.
Fig. 5 is that Fig. 4 sees the schematic diagram of looking by the circuit board top after pressing processing.
Embodiment
Seeing also shown in Figure 1ly, is to be the present generalized section of 6-layer circuit board.Present embodiment is an example with known 6-layer circuit board mainly, it mainly includes six layers is the conductive layer S1 of material with the Copper Foil, S2, S3, S4, S5, S6, respectively in order to constitute signal lead layer (Signal), ground plane (Ground), the use of bus plane (Power) etc., and each conductive layer S1, S2, S3, S4, S5, between S6 and pressing be provided with an insulating barrier L1, L2, L3, L4, L5, to avoid each conductive layer S1, S2, S3, S4, S5, signal between S6 and electromagnetic interference, wherein this insulating barrier L1, L2, L3, L4, L5 is constituted with the glass epoxy resin of the shape that is translucent (Glass Epoxy).
Other sees also shown in Figure 2, the utility model respectively offers a rectangle observation hole 10 in the same relative position place of top layer conductive layer S1, S6 up and down at 6-layer circuit board, this observation hole 10 is to divide two groups and the identical sight viewed area 12,14 of its area size into its centre five equilibrium, and wherein each is seen viewed area 12,14 and respectively is provided with one group of checking structure 30; This checking structure 30 mainly is to remove the conductive layer S1 on top layer up and down, outside the S6, order per three layers of continuous conducting layers S2 from top to bottom from circuit board institute lamination, S3, S4 and S3, S4, respectively be sequentially provided with occlusion areas 31 on the S5, one cue mark 33 reaches occlusion areas 35, and two adjacent sight viewed area 12,14 checking structure 30 staggers one deck conductive layer one by one downwards all in regular turn and is provided with, wherein aforesaid occlusion areas 31 up and down, 35 and cue mark 33, be respectively conductive layer S2, S3, S4, S5 is constituted in modes such as etchings, and this cue mark 33 can be made of any literal or pattern, each cue mark 33 is required to be different literal or figure, and each is positioned at the conductive layer S2 of cue mark one deck about in the of 33, S4 and S3, the last set occlusion areas up and down 31 of S5,35 just can be shielded in half of these sight viewed area 33 areas, and be mutually the dislocation and be provided with; Make after the correct circuit board of lamination is carrying out pressing processing, by the cue mark 33 that is shown in observation hole 10 upper and lowers just can have part cue mark 33 zones by about occlusion areas 31,35 covered, as shown in Figure 3; When the laminated layer sequence of circuit board is wrong, it carries out, and result of being produced after the pressing is not covered for the cue marks 33 that manifested in the observation hole 10 will produce or the aspect of complete crested, so will help the user in order to identification and judge whether the laminated layer sequence of this circuit board is wrong.
Other sees also Fig. 4, shown in 5, be that the utility model is applied in the embodiment on the 8-layer printed circuit board, it is to be positioned at the circuit board conductive layer S1 on top layer up and down equally, S8 same position place respectively is provided with a rectangle observation hole 20, this observation hole 20 is can be divided into four groups to be vertical arrangement and sight viewed area 22 of the same area, 24,26,28, and each sees viewed area 22,24,26,28 respectively are provided with this checking structure 30, and adjacent sight viewed area 22,24,26,28 checking structure 30 staggers one deck conductive layer one by one downwards all in regular turn and is provided with, thus when circuit board after pressing processing, can come whether the laminated layer sequence of decision circuitry plate is mistake by these cue mark 33 shown aspects in the observation hole 20, certainly the lamination along with circuit board increases, this sees viewed area 22,24,26,28 can increase progressively one by one, with the lamination number of cooperation checking multilayer circuit board, and aforesaid observation hole 20 can be according to required sight viewed area 22,24,26,28 number and cooperate this sight viewed area 22,24,26,28 position and being provided with separately.
Hence one can see that, advantage of the present utility model promptly be to be convenient to the user can be immediately by the correctness of covering aspect decision circuitry plate laminated layer sequence of cue mark 33, avoiding the misapplying wrong multilayer circuit board of lamination, and form the waste on manufacturing.
The above, it only is a preferred embodiment of the present utility model, be not to be used for limiting the scope that the utility model is implemented, all equalizations of doing according to the described shape of the utility model claim, structure, feature and spirit change and modify, and all should be included in the utility model claim.
Claims (8)
1, a kind of circuit board of verified laminated layer sequence is to be a multilayer circuit board, it is characterized in that:
The conductive layer on the top layer of this multilayer circuit board offers at least one observation hole; Constitute at least one sight viewed area in this observation hole;
One checking structure is the conductive layer order according to circuit board institute lamination, and the conductive layer of skim-coat is sequentially provided with occlusion areas in outer every continuous three layers conductive layer same position place, a cue mark reaches occlusion areas;
Wherein be respectively arranged with this checking structure in this each sight viewed area, and adjacent checking structure staggers one deck conductive layer one by one downwards all in regular turn and is provided with, through the circuit board of pressing processing, with the laminated layer sequence that covers aspect decision circuitry plate of cue mark demonstration in the observation hole.
2, the circuit board of verified laminated layer sequence according to claim 1 is characterized in that: this observation hole is the same relative position of the conductive layer place that is opened in the top layer up and down of multilayer circuit board, and constitutes at least one sight viewed area in each observation hole.
3, the circuit board of verified laminated layer sequence according to claim 1 and 2, it is characterized in that: each be positioned at cue mark up and down on the conductive layer of one deck set upper and lower occlusion areas just can be shielded in half of this sights viewed area area, and be to be mutually to misplace and be provided with.
4, the circuit board of verified laminated layer sequence according to claim 1 and 2 is characterized in that: being somebody's turn to do occlusion areas and cue mark up and down, is respectively that conductive layer is constituted with etching mode.
5, the circuit board of verified laminated layer sequence according to claim 1 and 2 is characterized in that: this cue mark is to be made of one of the two of literal and pattern, and each cue mark is required to be inequality.
6, the circuit board of verified laminated layer sequence according to claim 2, it is characterized in that: the correct circuit board of this lamination carries out pressing processing, and it is that occlusion areas is covered respectively up and down that the cue mark that shows in its observation hole upper and lower just can have part cue mark zone.
7, the circuit board of verified laminated layer sequence according to claim 1 and 2 is characterized in that: this sight viewed area is to be one vertically to arrange.
8, the circuit board of verified laminated layer sequence according to claim 1 and 2 is characterized in that: this observation hole is rectangular aspect setting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02282616 CN2582331Y (en) | 2002-10-24 | 2002-10-24 | Circuit board able to inspect order of laminate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02282616 CN2582331Y (en) | 2002-10-24 | 2002-10-24 | Circuit board able to inspect order of laminate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2582331Y true CN2582331Y (en) | 2003-10-22 |
Family
ID=33744662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02282616 Expired - Lifetime CN2582331Y (en) | 2002-10-24 | 2002-10-24 | Circuit board able to inspect order of laminate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2582331Y (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223751A (en) * | 2010-04-15 | 2011-10-19 | 华通电脑股份有限公司 | Multilayer circuit board and assembly thereof |
| CN102271462A (en) * | 2010-06-02 | 2011-12-07 | 楠梓电子股份有限公司 | Manufacturing method of identifiable printed circuit board |
| CN102301837A (en) * | 2011-05-27 | 2011-12-28 | 华为技术有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN102325425A (en) * | 2011-09-14 | 2012-01-18 | 聚信科技有限公司 | Detecting method for lamination error of printed circuit board, printed circuit board and detecting device |
| CN102387664A (en) * | 2010-09-06 | 2012-03-21 | 富葵精密组件(深圳)有限公司 | Circuit board printing method |
| CN102513630A (en) * | 2011-12-20 | 2012-06-27 | 北京航科发动机控制系统科技有限公司 | Positioning and laminating method for steel plates of cleaning start valve |
| US8595925B2 (en) | 2010-04-28 | 2013-12-03 | Wus Printed Circuit Co., Ltd | Manufacturing method of identifiable print circuit board |
| CN103415141B (en) * | 2013-08-29 | 2016-08-10 | 东莞市若美电子科技有限公司 | A kind of multiple-plate core material and multiple-plate lamination error proof |
| CN108770240A (en) * | 2018-05-03 | 2018-11-06 | 江门崇达电路技术有限公司 | The tool and method of item number are quickly recognized after a kind of PCB pressing |
-
2002
- 2002-10-24 CN CN 02282616 patent/CN2582331Y/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223751B (en) * | 2010-04-15 | 2012-10-10 | 华通电脑股份有限公司 | Multilayer circuit board and assembly thereof |
| CN102223751A (en) * | 2010-04-15 | 2011-10-19 | 华通电脑股份有限公司 | Multilayer circuit board and assembly thereof |
| US8595925B2 (en) | 2010-04-28 | 2013-12-03 | Wus Printed Circuit Co., Ltd | Manufacturing method of identifiable print circuit board |
| CN102271462A (en) * | 2010-06-02 | 2011-12-07 | 楠梓电子股份有限公司 | Manufacturing method of identifiable printed circuit board |
| CN102271462B (en) * | 2010-06-02 | 2015-03-11 | 楠梓电子股份有限公司 | Method of manufacturing identifiable printed circuit boards |
| CN102387664A (en) * | 2010-09-06 | 2012-03-21 | 富葵精密组件(深圳)有限公司 | Circuit board printing method |
| CN102387664B (en) * | 2010-09-06 | 2013-10-09 | 富葵精密组件(深圳)有限公司 | Circuit board printing method |
| WO2011127867A3 (en) * | 2011-05-27 | 2012-05-03 | 华为技术有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN102301837B (en) * | 2011-05-27 | 2013-03-20 | 华为技术有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN102301837A (en) * | 2011-05-27 | 2011-12-28 | 华为技术有限公司 | Multi-layer circuit board and manufacturing method thereof |
| US9018531B2 (en) | 2011-05-27 | 2015-04-28 | Huawei Technologies Co., Ltd. | Multilayer circuit board and manufacturing method thereof |
| CN102325425A (en) * | 2011-09-14 | 2012-01-18 | 聚信科技有限公司 | Detecting method for lamination error of printed circuit board, printed circuit board and detecting device |
| CN102325425B (en) * | 2011-09-14 | 2015-04-29 | 华为机器有限公司 | Detecting method for lamination error of printed circuit board, printed circuit board and detecting device |
| CN102513630A (en) * | 2011-12-20 | 2012-06-27 | 北京航科发动机控制系统科技有限公司 | Positioning and laminating method for steel plates of cleaning start valve |
| CN102513630B (en) * | 2011-12-20 | 2013-09-11 | 北京航科发动机控制系统科技有限公司 | Positioning and laminating method for steel plates of cleaning start valve |
| CN103415141B (en) * | 2013-08-29 | 2016-08-10 | 东莞市若美电子科技有限公司 | A kind of multiple-plate core material and multiple-plate lamination error proof |
| CN108770240A (en) * | 2018-05-03 | 2018-11-06 | 江门崇达电路技术有限公司 | The tool and method of item number are quickly recognized after a kind of PCB pressing |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20121024 Granted publication date: 20031022 |