CN2428919Y - Satellite multi-media data receiver for computer - Google Patents

Abstract

The utility model relates to a satellite multimedia data receiver for a computer, which is composed of a tuner, a demodulation and channel processing module, a frame synchronization and address detection module, a data cache module, a PCI bus interface and a power supply module. The utility model has the advantages that: the lowest receiving rate is 1M symbol rate per second, can effectively isolate interference, can receive MPEG-2 code stream conforming to DVB-S standard, input signal frequency range: L band 950-2150MHz, input signal level : -25dBm ~ -65dBm, input interface: F-type connector, PCI bus, plug and play.

Description

Satellite multimedia data receiver for computer

The utility model relates to a satellite multimedia data receiver used for computers, which belongs to the technical field of communication.

Since the International Satellite Communications Organization launched the first "International Telecommunications Satellite" (INTELSAT-I) into the geostationary orbit and put it into international communication business in 1965, satellite communication has been widely used in international and domestic communication, radio and television and other fields. With the development of communication technology, computer technology and ultra-large-scale integrated circuit technology, satellite communication technology has been continuously improved and improved, and satellite communication equipment has become smaller and smaller in size and more convenient to use.

In order to realize two-way communication in traditional satellite communication, two-way stations must be established. However, the two-way stations currently available in the market cannot well meet the application requirements, and they mainly have the following disadvantages:

1. Low transmission efficiency. The current two-way station system is mainly based on a symmetrical channel transmission mode. However, the actual network statistics show that a large amount of business traffic is asymmetrical, and the uplink capacity is greatly wasted, so the transmission efficiency of two-way stations is very low.

2. Expensive. The current two-way satellite Ku-band stations are all imported from abroad, and the minimum price is about 5,000 US dollars. Once a failure occurs, the maintenance cost each time is also very high. In a satellite communication system, the number of users is generally relatively large, and the price is an important factor to be considered when building a network.

3. High equipment requirements. In order to prevent transponder interference, the satellite operating company puts forward high requirements on the directivity and polarization isolation of the antenna of the two-way station. In order to ensure that the main station can receive the signal from the small station, the antenna of the small station should generally be between 1.8 and 2.4m; and in a one-way transmission system, as long as the transmission power of the main station is increased, the antenna can be Dropped below 1.2m, it is easy to install.

4. The site building environment has high requirements. At present, my country's satellite communication two-way stations have high requirements on the application environment. For example, the personal earth station (PES) of Hughes Corporation of the United States requires a power supply voltage of 200V~240V, a ground wire of less than 2 ohms, uninterrupted power supply, and an air-conditioned environment. This requirement is not easy to meet in many places in our country, even if it can be met, the cost of additional equipment required is relatively high.

In view of the above factors, in recent years, domestic and foreign countries have begun to develop satellite single-receiver stations with high integration and low price, and various forms of products have appeared, such as set-top boxes and plug-in cards inserted in computers. Especially with the formulation of Digital Video Broadcasting-Satellite DVB-S (Digital Video Broadcast-Satellite) standard, a dedicated large-scale integrated circuit has appeared, which has greatly improved the system integration. At present, many domestic and foreign companies such as HughesNetwork System, Scientific Atlanta, and Taiwan Qiancheng Video have launched their own computer-based products. They can meet the requirements to a certain extent, but there are the following problems:

1. The minimum rate of receiving data is 2M symbol rate per second (see the manual of each product), which is suitable for broadband video broadcasting, because the MPEG-2 video stream of one channel is generally at 2M bit per second. But in multimedia data broadcasting, the data rate can be lower than 2M bits per second, and the minimum required bandwidth is too high, which means that the system operation cost is increased. Generally speaking, the annual rent for a satellite transponder with a bandwidth of 1MHz is about 400,000 yuan, and the existing satellite receiver must invest at least 800,000 yuan a year to open and operate. When the system starts to operate, user requirements are relatively small, and 2MHz bandwidth may be wasted.

2. The satellite receiver inserted into the computer has relatively high requirements for the computer. In foreign countries, users generally use original brand computers, so the satellite receivers can work normally, but in my country, a large number of compatible computers and self-assembled machines are used, and some computers cannot meet the requirements of satellite receivers. Therefore, it is necessary to design a new type of satellite receiver with a wide range of applications for computers.

The purpose of this utility model is to design a satellite multimedia data receiver for computers, to reduce the minimum speed requirement of the satellite receiver, improve the adaptability of the satellite receiver, and thus meet the needs of China's national conditions. In addition, the current satellite computer receivers meeting the DVB-S standard are basically foreign products, and the utility model has better design performance and fills up the gap in China.

The satellite multimedia data receiver for computer designed by the utility model is composed of a tuner, a demodulation and channel processing module, a frame synchronization and address detection module, a data cache module, a PCI bus interface and a power supply module. Among them, the tuner, demodulation and channel processing module is the component U14, which is used to amplify, filter and frequency-convert the L-band signal (950-2150MHz) received from the satellite to obtain two orthogonal baseband signals, and perform A /D sampling, digital demodulation, channel decoding, deinterleaving and descrambling; the frame synchronization and address detection module is the component U3, which is used to detect the synchronization word of the descrambled signal to obtain frame synchronization, and detect the destination address of the data; The data buffer module is component U1, which is used to buffer the data received by itself for reading when the computer is idle; the PCI bus interface is component U4, which is used to process the bus interface between the computer and the receiver; the receiver power supply is Components U10, U11, U12, U8, and U7 respectively provide corresponding power supplies to other modules of the receiver.

The utility model has the advantages of:

1. The minimum receiving rate is 1M symbol rate per second.

2. The power supply on the board is completely independent design, which effectively isolates interference.

3. It can receive MPEG-2 code stream conforming to DVB-S standard.

4. Input signal frequency range: L-band 950~2150MHz.

5. Input signal level: -25dBm ~ -65dBm.

6. Input interface: F-type connector.

7. PCI bus, plug and play.

8. Provide vertical/horizontal polarization voltage to LNB: 13/18V.

Description of drawings:

Figure 1 is a functional block diagram of a satellite receiver.

Fig. 2 is the schematic diagram of the circuit of the tuner, demodulation and channel processing modules.

Figure 3 is a functional block diagram of the tuner.

Figure 4 is a functional block diagram of the demodulation and channel processing modules.

FIG. 5 is a schematic diagram of a frame structure.

Figure 6 is a schematic diagram of the frame synchronization and address detection circuit.

FIG. 7 is a schematic diagram of a data cache circuit.

Figure 8 is a schematic diagram of the PCI bus interface circuit.

Figure 9 is a schematic diagram of the power module circuit.

Introduce the content of the utility model in detail below in conjunction with accompanying drawing.

As shown in Figures 2, 3, and 4, the L-band signal first passes through a band-pass filter to filter out out-of-band clutter and interference, and then is amplified by a first-stage amplifier controlled by the automatic gain control AGC voltage. The signal undergoes a frequency conversion after passing through the second-stage band-pass filter, and the signal is transferred to the intermediate frequency, and then passes through the corresponding band-pass filter and the second-stage amplifier controlled by AGC. The second local oscillator generates two mutually orthogonal carrier waves, which are mixed and filtered with the second-stage amplified signal to obtain two orthogonal baseband signals I and Q. In Figure 2, U8 is the power amplifier, which increases the 18V power supply for the tuner. The two quadrature baseband signals I and Q become digital signals through A/D sampling, and then QPSK demodulation. In order to ensure the reliability of data transmission, the data must be channel coded. In the DVB-S standard, what is adopted is the concatenated code with the convolutional code as the inner code and the RS code as the outer code. At the same time, in order to resist burst errors in the channel, it is also necessary to interleave the data. Therefore, the demodulated data is firstly decoded by Viterbi convolution, and the coding rate is variable from 1/2 to 7/8; By decoding, basically error-free data can be obtained. In order to solve the problem of 01 code asymmetry in data transmission, the source is usually scrambled before transmission, and accordingly we need to descramble at the end.

Figure 5 shows the frame structure of the data after channel processing and descrambling, which consists of synchronization word, destination address, data length and data. As shown in Figure 6, in order to realize the correct identification of the data, it is first necessary to find the synchronous word, and then judge whether the destination address is the same as the address of the receiver, if it is the same, receive it, otherwise discard the data. Since the data is a variable-length frame, it is necessary to correctly receive subsequent data according to the data length indication.

As shown in Figure 7, in order to realize that the computer and the satellite receiver can work asynchronously, that is, the computer can read data from the satellite receiver when it is idle, so we need to buffer the data received by the satellite receiver, here we use Dual-port RAM, that is, there are two sets of data and address buses for reading and writing of the computer and the satellite receiver respectively, and these two sets of reading and writing can be operated at the same time. The management of the buffer adopts a ring queue, which has two pointers, one is a read pointer, and the other is a write pointer, indicating the addresses of the current read and write buffers respectively. In this way, when the satellite receiver receives the data it needs, it writes the data into the buffer according to the write pointer, and sends an interrupt to the computer. The computer does not have to respond to interrupts immediately, it can read data when it is idle, which can reduce waiting time and improve efficiency.

As shown in Figure 8, the PCI bus interface is a "bridge" between the satellite receiver and the PCI bus interface, and it fully complies with the PCI2.1 specification. The satellite receiver is plugged into the computer and can be plugged and played, which can automatically obtain system resources, and the maximum data transmission rate is 133Mbyte/s.

As shown in Figure 9, there are multiple sets of power supplies on the satellite receiver, including 3.3V, 5V, 14/18V, and 30V. Since the satellite receiver is plugged into the computer, the power is supplied by the computer. However, the power levels of various computers in our country are uneven, and some power supply ripples and clutter are very large, which makes satellite receivers that can work on some computers not work on other computers. So we design the power supply very carefully, and take effective isolation for each group of power supplies. Each power supply with different functions either adopts a DC/DC conversion module or a voltage stabilization module, so that the ripple of each power supply is controlled below 20 millivolts, which greatly improves the adaptability of the satellite receiver in different computers. Among them, U7, U10, U11 are DC/DC conversion modules, which provide 30V, 18V, and 5V power supplies respectively, and U12, U13, U15 are voltage stabilizing modules, which provide 3.3V, 5V, and 5V power supplies respectively.

Claims (1)

1, a kind of satellite multimedia data receiver for computer, it is characterized in that, this receiver is made of tuner, demodulation and channel processing module, frame synchronization and address detection module, data cache module, PCI bus interface and power supply module Composition; Wherein said tuner, demodulator and channel processing module are element U14, are used for amplifying, filtering and frequency-converting the L-band signal received from the satellite to obtain two-way orthogonal baseband signals, and performing A /D sampling, digital demodulation, channel decoding, deinterleaving and descrambling; wherein the frame synchronization and address detection module is a component U3, which is used to perform synchronization word detection on the descrambled signal to obtain frame synchronization and detect data The destination address; wherein the data buffer module is a component U1, which is used to cache the data received by itself for reading when the computer is idle; it is that the PCI bus interface is a component U4, which is used to process the computer A bus interface with the receiver; wherein the receiver power supply is components U10, U11, U12, U8, U7, which respectively provide corresponding power supplies to other modules of the receiver.

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