CN222485185U

CN222485185U - Semiconductor device

Info

Publication number: CN222485185U
Application number: CN202323486213.3U
Authority: CN
Inventors: 钱洪途; 吴星星
Original assignee: Dynax Semiconductor Inc
Current assignee: Dynax Semiconductor Inc
Priority date: 2023-12-20
Filing date: 2023-12-20
Publication date: 2025-02-14
Anticipated expiration: 2033-12-20

Abstract

The utility model discloses a semiconductor device, which comprises a source field plate extending from an active area to a passive area, and extending until bypassing a gate to be electrically connected to a source, so as to reduce the facing area between the gate and the source field plate; a second subsection of the source field plate located in the passive area is spaced from a second subsection of the gate located in the passive area, that is, the source field plate and the gate are arranged in the passive area along the extension direction of the gate without overlapping and satisfying a certain distance, so as to further reduce the facing area between the gate and the source field plate, and improve the performance and reliability of the semiconductor device.

Description

Semiconductor device

Technical Field

The utility model relates to the technical field of microelectronic devices, in particular to a semiconductor device.

Background

With the further development of the microelectronics industry, the operating frequency of electronic products is also higher and higher, and the requirements on the bandwidth and the operating frequency of semiconductor chips are also higher and higher, wherein a gallium nitride high electron mobility transistor (High electron mobility transistor, HEMT) is a high electron mobility device formed by utilizing two-dimensional electron gas at an AlGaN or GaN heterojunction, and can be better applied to the fields of high frequency, high voltage and high power.

In order to improve the breakdown voltage of the high electron mobility transistor and fully exert the advantage of high output power, researchers at home and abroad propose a plurality of methods, and the source field plate structure is one of the most obvious effects and the most widely applied.

The source field plate is a conductive structure interposed between the gate and the drain and connected to the source. The structure has the effects of inhibiting the maximum electric field intensity of the channel region, increasing the breakdown voltage, inhibiting the trapping effect of defects in the device and improving the performance of the device. However, the current design for the source field plate is to make the electrical connection of the source field plate and the source across the gate by connecting lines. This design requires the source field plate to be thick enough to ensure that the connection lines of the source field plate do not break when climbing at the gate. But this design introduces additional gate-source capacitance that in turn affects the frequency response of the device.

Disclosure of utility model

The embodiment of the utility model provides a semiconductor device, which is used for reducing the opposite area between a source electrode field plate and a grid electrode so as to reduce parasitic capacitance and improve the frequency response of the semiconductor device.

The embodiment of the utility model provides a semiconductor device, which comprises:

An active region and an inactive region surrounding the active region;

A substrate arranged in the active region and the passive region and an epitaxial structure positioned on one side of the substrate;

a source electrode, a drain electrode and a grid electrode, wherein the source electrode and the drain electrode are positioned on one side of the epitaxial structure away from the substrate;

The source electrode field plate is arranged on one side of the grid electrode far away from the substrate and is insulated from the grid electrode, extends from the active region to the passive region and extends until the source electrode field plate bypasses the grid electrode to be electrically connected with the source electrode.

Optionally, the gate includes a first gate portion located in the active region and a second gate portion located in the inactive region, the source field plate includes a first portion located in the active region, a second portion located in the inactive region, and a third portion located in the active region and overlapping the source, and the second portion extends to a side, away from the active region, of the second gate portion along an extending direction of the gate, and is spaced from the second gate portion.

Optionally, the maximum width W1 of the third subsection is greater than the maximum width W2 of the second subsection.

Optionally, the widths of the second sections are set equal or the widths of the second sections are increased along the direction in which the source field plate points to the source.

Optionally, the interval between the second subsection and the second grid subsection is D1, and D1 is 0< 200 μm or less.

Optionally, the distance D2 between the second subsection and the active region is D1< D2 ∈300 μm.

Optionally, a source through hole is formed in the source electrode;

And the orthographic projection of the third part on the surface of the substrate is not overlapped with the orthographic projection of the source through hole on the surface of the substrate, or the overlapped area is smaller than 1/2 of the orthographic projection of the third part on the surface of the substrate.

Optionally, the source electrode comprises at least two source electrode field plates, wherein the at least two source electrode field plates comprise a first source electrode field plate and a second source electrode field plate which are respectively positioned at two sides of the source electrode and are adjacently arranged;

The second part of the first source electrode field plate and the second part of the second source electrode field plate are connected into an integrated structure to form a source electrode field plate interconnection structure, the first source electrode field plate and the second source electrode field plate share a third part, and the source electrode field plate interconnection structure is connected with the third part.

Optionally, the first portion of the first source field plate and the first portion of the second source field plate are symmetrical about a first symmetry axis;

The source electrode field plate interconnection structure is symmetrical about a second symmetry axis, and the second symmetry axis and the first symmetry axis are the same symmetry axis.

Optionally, the epitaxial structure includes:

a nucleation layer located on one side of the substrate;

A buffer layer located on a side of the nucleation layer away from the substrate;

a channel layer located at one side of the buffer layer away from the substrate;

And the barrier layer is positioned on one side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

According to the technical scheme, the semiconductor device comprises the source electrode field plate extending from the active region to the passive region and extending to bypass the grid electrode to be electrically connected with the source electrode so as to reduce the opposite area between the grid electrode and the source electrode field plate, wherein the second part of the source electrode field plate, which is positioned in the passive region, is arranged at intervals with the second part of the grid electrode, which is positioned in the passive region, namely, the source electrode field plate and the grid electrode are arranged in the passive region and are not overlapped in the extending direction along the grid electrode, so that the opposite area between the grid electrode and the source electrode field plate is further reduced, and the performance and the reliability of the semiconductor device are improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present utility model;

FIG. 2 is a schematic cross-sectional view of a semiconductor device along section line A-A' as provided in FIG. 1;

fig. 3 is a schematic top view of another semiconductor device according to an embodiment of the present utility model;

Fig. 4 is a schematic top view of another semiconductor device according to an embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

HEMT is a wide band gap semiconductor device with high concentration Two-dimensional electron gas (Two-Dimensional Electron Gas,2 DEG), has the advantages of high output power density, high temperature resistance, strong stability, high breakdown voltage and the like, and has great application potential in the fields of radio frequency and power electronic devices. In order to achieve high performance at high frequencies, it is desirable to minimize parasitic capacitance of the device in the structural design of semiconductor devices.

The parasitic capacitance of the semiconductor device is mainly divided into a gate-source capacitance, a gate-drain capacitance and a source-drain capacitance. Wherein the gate-source capacitance has the greatest effect on the device frequency. The gate-source capacitance of a semiconductor device mainly comes from two sources, one is parasitic capacitance of gate metal and channel, and the other is capacitance between gate metal and source field plate.

When the semiconductor device works, the source electrode field plate and the source electrode are both at zero potential, at the moment, the source electrode field plate can increase the area of a depletion region on one side of the grid electrode, which is close to the drain electrode, so that the drain-source voltage born by the depletion region is improved, the breakdown voltage of the device is improved, and meanwhile, the source electrode field plate is utilized to modulate the distribution of electric field lines in the depletion region of the barrier layer, so that the leakage current of the grid electrode is reduced. The technical scheme of the embodiment of the utility model aims to reduce parasitic capacitance between the grid electrode and the source electrode field plate by designing the source electrode field plate, improve the performance and the reliability of the semiconductor device, and is explained in detail.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present utility model, fig. 2 is a schematic cross-sectional structure of the semiconductor device according to fig. 1 along a cross-sectional line A-A', and as shown in fig. 1 and 2, the semiconductor device further includes a source 301, a drain 302 and a gate 303 located in the active area aa and a source area bb surrounding the active area aa, an epitaxial structure 20 located on one side of the substrate 10, a source 301, a drain 302 and a gate 303 located between the source 301 and the drain 302 and located on a side of the epitaxial structure 20 away from the substrate 10, and a source field plate 40 located on one side of the gate 303 away from the substrate 10 and insulated from the gate 303, wherein the source field plate 40 extends from the active area aa to the source area bb and extends to bypass the gate 303 and is electrically connected to the source 301.

Further, as shown in fig. 1, the gate 303 includes a gate first portion 3031 located in the active region aa and a gate second portion 3032 located in the inactive region bb, the source field plate 40 includes a first portion 401 located in the active region aa and a second portion 402 located in the inactive region bb, the second portion 402 extends to a side of the gate second portion 3032 away from the active region aa along an extending direction of the gate 303, and the second portion 402 and the gate second portion 3032 are spaced apart from each other. The source electrode field plate and the grid electrode are arranged in the passive region, do not overlap in the extending direction of the grid electrode and have a certain distance, the opposite area between the grid electrode and the source electrode field plate can be further reduced, and the performance and the reliability of the semiconductor device are improved.

It is to be understood that the semiconductor device includes, in the thickness direction, the substrate 10, the epitaxial structure 20, the electrode structure 30, the dielectric layer 50, the field plate 40, and the like, and is not particularly limited as long as the requirements of the present utility model are satisfied in the top view structure.

The substrate 10 may be aluminum gallium nitride, aluminum gallium arsenic, silicon carbide, or silicon, and the type of the material of the substrate 10 is not particularly limited in the embodiments of the present utility model. The epitaxial structure 20 on one side of the substrate 10 may be formed of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

By way of example, the epitaxial structure 20 may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked on one side of the substrate 10, wherein a heterojunction structure may be formed between the channel layer and the barrier layer. It will be appreciated that the epitaxial structure 20 may also include a cap layer located on the surface of the barrier layer remote from the substrate 10. The cap layer may reduce surface states, reduce surface leakage of subsequent semiconductor devices, and inhibit current collapse, thereby improving performance and reliability of epitaxial structure 20 and the semiconductor devices.

Further, the electrode structure 30 on the side of the epitaxial structure 20 remote from the substrate may include a source 301, a drain 302, and a gate 303 between the source 301 and the drain 302. The source 301 and drain 3021 may each form ohmic contact with the epitaxial structure 20. Illustratively, the source 301 may serve as an input terminal of the semiconductor device, the drain 302 may serve as an output terminal of the semiconductor device, the gate 303 may serve as a control terminal of the semiconductor device, and current flow between the source 301 and the drain 302 may be achieved by controlling the voltage of the gate 303. That is, when a certain voltage is applied to the gate electrode 303, a current is generated between the source electrode 301 and the drain electrode 302, and the current between the source electrode 301 and the drain electrode 302 can be controlled by changing the voltage of the gate electrode 303.

Specifically, the source field plate 40 is located at a side of the gate 303 away from the substrate 10 and is insulated from the gate 303, that is, the source field plate 40 is not directly contacted with the gate 303, but the dielectric layer 50 is disposed on the upper surface and the side of the gate 303, so as to realize insulation between the gate 303 and the source field plate 40. It will be appreciated that in the direction in which the source 301 points to the drain 302, the source field plate 40 may overlap with the gate 303 or may not overlap with the gate 303, and the source field plate 40 and the gate 303 may be disposed in the inactive region bb along the extending direction of the gate and at a certain distance, so as to reduce the facing area between the gate and the source field plate and reduce the parasitic capacitance of the gate and source.

Specifically, the active area aa is understood to be an area under which two-dimensional electron gas, electrons or holes exist, and the working state and characteristics of the active area aa are affected by an external circuit, and are active working areas of the semiconductor device. The inactive region bb participates in the operation of the semiconductor device, but its operation state is not affected by an external circuit, for example, an extraction structure of an electrode in the active region aa may be provided in the inactive region bb, and the inactive region bb may be provided around the active region aa.

It will be appreciated that as shown in fig. 3, the semiconductor device may further include a gate pad 304, where the gate pad 304 is connected to the gate 303 in the active area aa, and provides a gate voltage signal to the gate 303, so as to ensure that the semiconductor device operates normally. Illustratively, the materials of the source 301, drain 302, gate 303, and source field plate 40 may be gold, silver, copper, iron, aluminum, indium, platinum, titanium, nickel, or any combination thereof.

As a possible embodiment, fig. 3 is a schematic top view of another semiconductor device, where the spacing between the second portion 402 of the source field plate 40 and the gate second portion 3032 is D1, where D1 satisfies 0< D1+.200 μm. The provision of the spacing between the second subsection 402 and the gate second subsection 3032 is advantageous in ensuring reduced area alignment while optimizing device area and improving performance.

For example, the spacing D1 between the second portion 402 of the source field plate 40 and the gate second portion 3032 may be d1=50 μm, d1=100 μm, d1=150 μm, or d1=180 μm.

Optionally, the second portion 402 of the source field plate 40 is spaced apart from the active region aa by a distance D2, D2 satisfying D1< D2.ltoreq.300 μm. In the layout design of the semiconductor device, on the basis that a certain interval needs to be kept between the second part 402 of the source field plate 40 and the second part 3032 of the gate, the distance between the second part 402 of the source field plate 40 and the active region aa can affect the area and the performance of the whole semiconductor device, and setting D2 to satisfy D1< D2 is not more than 300 μm, which is beneficial to reducing the area of the whole semiconductor device and improving the performance of the integrated circuit.

Illustratively, the distance D2 between the second portion 402 of the source field plate 40 and the active region aa may be d2=50 μm, d2=100 μm, d2=150 μm, or d3=200 μm.

Optionally, the source field plate 40 further includes a third portion 403 disposed in the active area aa and overlapping the source 301, where the three portions of the source field plate 40 are sequentially connected by the first portion 401, the second portion 402, and the third portion 403. The maximum width of the third subsection 403 is W1, the maximum width of the second subsection 402 is W2, and the ratio of W1 to W2 is satisfied between the third subsection and the second subsection, so that the connection stability between the source electrode field plate and the source electrode can be further improved while the facing area between the gate electrode and the source electrode field plate is reduced as much as possible, and the reliability of the device is improved.

Optionally, the widths of the second sections 402 of the source field plate 40 are arranged equally, or the widths of the second sections 402 of the source field plate 40 are increased in a direction along the source field plate 40 pointing towards the source 301. The width of the second portion 402 of the source field plate 40 is equal in the extending direction of the source field plate 40 from the active region aa to the inactive region bb, which is beneficial to improving the stability of the source field plate 40 in the inactive region and avoiding affecting the device performance. Or the width of the second section 402 increases in the direction along the source field plate 40 toward the source 301, the stability of the source field plate and source electrical connection can be improved, and the reliability can be improved.

As a possible implementation, referring to fig. 3, the source field plate 40 further includes a third subsection 403, and the third subsection 403 is located within the active region aa and overlaps the source 301. Alternatively, source via holes 11 are correspondingly disposed in the source electrodes 301, and the source electrodes 301 may be connected to the back surface of the semiconductor device through the source via holes 11, which may extend through the substrate 10 and the epitaxial structure 20, for example.

Optionally, the orthographic projection of the third portion 403 on the surface of the substrate 10 does not overlap with the orthographic projection of the source via 11 on the surface of the substrate 10, or the overlapping area is less than 1/2 of the orthographic projection of the third portion 403 on the surface of the substrate 10.

It should be further noted that the semiconductor device may be a single-cell structure, for example, including only one source 301, drain 302, gate 303, and source field plate 40. The semiconductor device may also be a multiple unit cell structure, i.e. comprising at least two gates 303 and two source field plates 40. The structure of the source field plate 40 described above may be applied to either a single cell structure or a multiple cell structure.

As one possible implementation, fig. 4 is a schematic top view of another semiconductor device. The semiconductor device comprises at least two source field plates 40, the at least two source field plates 40 comprising a first source field plate 41 and a second source field plate 42 located adjacent to each other on both sides of the source 301. The first source field plate 41 and the second source field plate 42 each comprise a first subsection 411 (421), a second subsection 412 (422) and a third subsection 413 (423), wherein the first subsection 411 (421) is located in an active area aa, the second subsection 412 (422) is located in a passive area bb, and the third subsection 413 (423) is located in the active area aa and overlaps the source 301. The second portion 412 of the first source field plate 41 and the second portion 422 of the second source field plate 42 are connected to form a unitary structure to form a source field plate interconnection structure 44, the third portion 413 of the first source field plate 41 and the third portion 423 of the second source field plate 42 are completely overlapped, or the first source field plate 41 and the second source field plate 42 share one third portion 413, and the source field plate interconnection structure 44 is connected to the third portion 413.

Optionally, the first portion 411 of the first source field plate 41 and the first portion 421 of the second source field plate 42 are symmetrical about a first symmetry axis, and the source field plate interconnection structure 44 is symmetrical about a second symmetry axis, wherein the second symmetry axis and the first symmetry axis are the same symmetry axis. The symmetrical arrangement of the source field plate interconnect structures 44 is advantageous for improving the radio frequency characteristics of the semiconductor device.

The semiconductor device of the present utility model may further comprise a gate pad 304, the gate pad 304 being connected to the gate 303 in the active region aa, the second and third sections 402, 403 of the source field plate 40 being located on the opposite side of the gate pad 304. It will be appreciated that in a semiconductor device having a source field plate interconnect structure 44, the source field plate interconnect structure 44 is located on the opposite side of the gate pad 304.

It will be appreciated that with continued reference to fig. 2, epitaxial structure 20 includes nucleation layer 201 on the side of substrate 10, buffer layer 202 on the side of nucleation layer 201 away from substrate 10, channel layer 203 on the side of buffer layer 202 away from substrate 10, barrier layer 204 on the side of channel layer 203 away from substrate 10, barrier layer 204 forming a heterojunction structure with channel layer 203 forming a two-dimensional electron gas at the interface.

Illustratively, with continued reference to fig. 2, the material of nucleation layer 201 may be aluminum nitride, located between substrate 10 and buffer layer 202, and nucleation layer 201 affects parameters such as crystal quality, surface morphology, and electrical properties of the overlying heterojunction material. The nucleation layer 201 varies with different substrate materials and primarily serves to match the substrate material and the semiconductor material layers in the heterojunction structure.

Illustratively, with continued reference to fig. 2, the buffer layer 202 is located on one side of the substrate 10, the material of the buffer layer 202 may be gallium nitride, and iron atoms may be included in the buffer layer 202, which is beneficial to realizing high resistance of the buffer layer 202, ensuring that vertical leakage can be blocked, and improving pinch-off performance of the semiconductor device. Buffer layer 202 may serve to adhere to a layer of semiconductor material that may be subsequently grown, and may also protect substrate 10 from some metal ions. The material of the buffer layer 202 may be a group iii nitride material such as AlGaN, gaN, or AlGaInN.

Illustratively, with continued reference to FIG. 2, the channel layer 203 may be a group III nitride, such as Al _xGa_1－x N, where 0+.x <1, i.e., the energy at the interface between the channel layer 203 and the barrier layer 204, i.e., the conduction band edge of the channel layer 203, is less than the conduction band edge of the barrier layer 204. Illustratively, x=0 indicates that the channel layer 203 is GaN. The channel layer 203 may also be other group III nitrides, such as InGaN, alInGaN. The channel layer 203 may be undoped or unintentionally doped. The channel layer 203 may also be a multi-layer structure, such as a combination of superlattice, gaN, or AlGaN.

Illustratively, with continued reference to fig. 2, the barrier layer 204 may be AlN, alInN, alGaN or AlInGaN. The barrier layer 204 has a sufficient thickness and has a high enough Al composition to cause doping to form a significant carrier concentration at the interface between the channel layer 203 and the barrier layer 204.

Illustratively, with continued reference to fig. 2, the channel layer 203 may include GaN, while the barrier layer 204 may include AlGaN, i.e., the material of the barrier layer 204 has a higher bandgap than the material of the channel layer 203, and the channel layer 203 may also have a greater electron affinity than the barrier layer 204. Due to the difference in band gap between the barrier layer 204 and the channel layer 203 and the piezoelectric effect at the interface between the barrier layer 204 and the channel layer 203, two-dimensional electron gas is formed at the channel layer 203 and the barrier layer 204.

It will be appreciated that epitaxial structure 20 may also include a cap layer located on the surface of barrier layer 204 remote from substrate 10. The cap layer may reduce surface states, reduce surface leakage of subsequent semiconductor devices, and inhibit current collapse, thereby improving performance and reliability of epitaxial structure 20 and the semiconductor devices.

It should be understood that, from the standpoint of layout design of the semiconductor device, the embodiments of the present utility model can reduce the capacitance between the source field plate and the gate and improve the frequency response of the semiconductor device by providing the connection structure of the source field plate and the source to bypass the gate from the inactive region. The semiconductor device includes, but is not limited to, a high power high electron mobility transistor (High Electron Mobility Transistor, HEMT), a Silicon-On-Insulator (SOI) structure transistor On an insulating substrate, a gallium arsenide (GaAs) based transistor, and a Metal-Oxide-semiconductor Field effect transistor (MOSFET) Semiconductor Field-Effect Transistor, a Metal-Insulator-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, MISFET), a double heterojunction Field effect transistor (Double Heterojunction Field-Effect Transistor, DHFET), a Junction Field effect transistor (Junction Field-Effect Transistor, JFET), a Metal-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, MESFET), a Metal-Insulator-semiconductor heterojunction Field effect transistor (Metal-Semiconductor Heterojunction Field-Effect Transistor, HFMISET), or other Field effect transistor. The source electrode field plate arranged in the semiconductor device provided by the embodiment of the utility model can be widely applied to the field of manufacturing of semiconductor devices such as radio frequency microwaves, power electronics and the like. The gallium nitride electronic device has more obvious advantages on the gallium nitride electronic device with large forbidden bandwidth, high electron mobility, high breakdown field intensity and good heat conduction performance, and can better meet the high-performance requirements of the fields of fast development of electronic communication and the like.

Note that the above is only a preferred embodiment of the present utility model and the technical principle applied. It will be understood by those skilled in the art that the present utility model is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, while the utility model has been described in connection with the above embodiments, the utility model is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the utility model, which is set forth in the following claims.

Claims

1. A semiconductor device, comprising:

An active region and an inactive region surrounding the active region;

The source electrode field plate is arranged on one side of the grid electrode far away from the substrate and is insulated from the grid electrode, extends from the active region to the passive region, and extends to bypass the grid electrode and is electrically connected with the source electrode.

2. The semiconductor device of claim 1, wherein the gate includes a gate first portion located in the active region and a gate second portion located in the inactive region, wherein the source field plate includes a first portion located in the active region, a second portion located in the inactive region, and a third portion located in the active region and overlapping the source, wherein the second portion extends to a side of the gate second portion remote from the active region along an extension direction of the gate with a space therebetween.

3. The semiconductor device of claim 2, wherein a maximum width W1 of the third segment is greater than a maximum width W2 of the second segment.

4. The semiconductor device of claim 2, wherein the widths of the second sections are set equal or the widths of the second sections are increased along a direction in which the source field plate points toward the source.

5. The semiconductor device of claim 2, wherein a spacing D1 between the second division and the gate second division satisfies 0< D1 +.200 μm.

6. The semiconductor device of claim 2, wherein the second subsection is spaced from the active region by a distance D2 that satisfies D1< D2 +.300 μm.

7. The semiconductor device according to claim 2, wherein a source via is provided on the source electrode;

8. The semiconductor device of claim 1, wherein the semiconductor device comprises at least two source field plates, the at least two source field plates comprising a first source field plate and a second source field plate disposed adjacent to each other on either side of the source, the source field plates comprising a first portion disposed in the active region, a second portion disposed in the inactive region, and a third portion disposed in the active region and overlapping the source;

9. The semiconductor device of claim 8, wherein the first portion of the first source field plate and the first portion of the second source field plate are symmetrical about a first axis of symmetry;

10. The semiconductor device according to claim 1, wherein,

The epitaxial structure comprises:

a nucleation layer located on one side of the substrate;