CN222484674U

CN222484674U - Signal distribution circuit and distributor capable of adaptively adjusting gain

Info

Publication number: CN222484674U
Application number: CN202421075110.XU
Authority: CN
Inventors: 邸兴龙
Original assignee: Shenzhen Lvlian Technology Co Ltd
Current assignee: Shenzhen Lvlian Technology Co Ltd
Priority date: 2024-05-16
Filing date: 2024-05-16
Publication date: 2025-02-14
Anticipated expiration: 2034-05-16

Abstract

The utility model discloses a signal distribution circuit and distributor for adaptively adjusting gain, the circuit includes a first switching processing module, a second switching processing module and a signal output module, wherein the first switching processing module is used to receive a target input signal transmitted by a signal input module, and perform a first target processing operation on the target input signal to obtain a first target signal and transmit the first target signal to the second switching processing module, the second switching processing module is used to perform a second target processing operation on the first target signal to obtain a second target signal and transmit the second target signal to the signal output module, and the signal output module is used to transmit the received second target signal to a preset target device. It can be seen that the utility model can improve the quality and adaptive adjustment capability of the output signal, improve the distribution output capability and output clarity of the HDMI signal, and thus help improve the user experience.

Description

Signal distribution circuit and distributor capable of adaptively adjusting gain

Technical Field

The present utility model relates to the field of a splitter, and in particular, to a signal distribution circuit and a splitter capable of adaptively adjusting gain.

Background

With the continuous development of science and technology, digital electronic devices have become an indispensable part of life, and more digital electronic devices all adopt HDMI interfaces as main audio and video signal transmission interfaces, and various signal source output devices and display devices are connected through HDMI lines to transmit high-quality and stable audio and video signals.

The multi-channel HDMI distributor is an electronic device capable of distributing a high-definition signal generated by one high-definition signal source to a plurality of output display devices supporting the high-definition signal. At present, the multichannel HDMI distributor on the market does not process the output signals, if the HDMI versions and resolutions of different display devices used by the user side are inconsistent, only the lowest resolution output can be obtained, high-definition and high-quality visual experience cannot be provided for the user, and the multichannel HDMI distributor on the market has fewer output ports, lower output definition supported by the ports and poor user experience. Therefore, it is important to provide a new signal distribution circuit to improve the distribution output capability and output definition of HDMI signals and increase the number of output ports, so as to improve the user experience.

Disclosure of utility model

The signal distribution circuit and the distributor for adaptively adjusting the gain can improve the distribution output capacity and the output definition of HDMI signals and increase the number of output ports.

In order to solve the above technical problems, a first aspect of the present utility model discloses a signal distribution circuit for adaptively adjusting gain, which is characterized in that the circuit includes a first switching processing module, a second switching processing module, and a signal output module, wherein:

The first end of the first switching processing module is used for being electrically connected with the signal input module, the second end of the first switching processing module is electrically connected with the first end of the second switching processing module, and the second end of the second switching processing module is electrically connected with the first end of the signal output module;

The first switching processing module is configured to receive the target input signal transmitted by the signal input module, perform a first target processing operation on the target input signal, obtain a first target signal, and transmit the first target signal to the second switching processing module;

The second switching processing module is configured to perform a second target processing operation on the first target signal, obtain a second target signal, and transmit the second target signal to the signal output module;

the signal output module is used for transmitting the received second target signal to preset target equipment.

As an alternative embodiment, in the first aspect of the present utility model, the circuit further comprises a signal processing module, wherein:

the first end of the signal processing module is used for being electrically connected with the signal input module, and the second end of the signal processing module is electrically connected with the first end of the first switching processing module;

The signal processing module is configured to receive the target input signal transmitted by the signal input module, perform a signal processing operation on the target input signal, obtain the target input signal after the signal processing is completed, and transmit the target input signal after the signal processing to the first switching processing module.

As an alternative embodiment, in the first aspect of the present utility model, the circuit further comprises a control module, wherein:

the first end of the control module is electrically connected with the third end of the first switching processing module, and the second end of the control module is electrically connected with the third end of the second switching processing module;

The control module is used for managing the working modes of the first switching processing module, the second switching processing module and the signal processing module.

As an optional implementation manner, in the first aspect of the present utility model, the first switching processing module includes a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first p_mode circuit, where:

The first end of the first processing chip is electrically connected with the second end of the signal processing module, the second end of the first processing chip is electrically connected with the first end of the second switching processing module, the third end of the first processing chip is electrically connected with the first end of the control module, the fourth end of the first processing chip is electrically connected with the first end of the first JTAG circuit, the fifth end of the first processing chip is electrically connected with the first end of the first I2C circuit, the sixth end of the first processing chip is electrically connected with the first end of the first QSPI circuit, and the seventh end of the first processing chip is electrically connected with the first end of the first P_MODE circuit.

As an optional implementation manner, in the first aspect of the present utility model, the second switching processing module includes a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second p_mode circuit, and an AUDIO circuit, where:

The first end of the second processing chip is electrically connected with the second end of the first switching processing module, the second end of the second processing chip is electrically connected with the first end of the signal output module, the third end of the second processing chip is electrically connected with the second end of the control module, the fourth end of the second processing chip is electrically connected with the first end of the second JTAG circuit, the fifth end of the second processing chip is electrically connected with the first end of the second I2C circuit, the sixth end of the second processing chip is electrically connected with the first end of the second QSPI circuit, the seventh end of the second processing chip is electrically connected with the first end of the second P_MODE circuit, and the eighth end of the second processing chip is electrically connected with the first end of the AUDIO circuit.

As an optional implementation manner, in the first aspect of the present utility model, the control module includes a control chip and an EDID dial circuit, where:

The first end of the control chip is electrically connected with the third end of the first switching processing module, the second end of the control chip is electrically connected with the third end of the second switching processing module, and the third end of the control chip is electrically connected with the first end of the EDID dialing circuit;

The EDID dialing circuit is used for controlling the signal format of the second target signal output by the signal output module.

As an alternative embodiment, in the first aspect of the present utility model, the circuit further includes the signal input module, the signal input module includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

The first end of the target input chip is electrically connected with the first end of the signal processing module, the second end of the target input chip is electrically connected with the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected with the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected with the first end of the input HPD processing circuit.

As an optional implementation manner, in the first aspect of the present utility model, the signal output module includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, where:

The first end of the target output chip is electrically connected with the second end of the second switching processing module, the second end of the target output chip is electrically connected with the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected with the first end of the output DDC processing circuit, the fourth end of the target output chip is electrically connected with the first end of the output HPD processing circuit, and the fifth end of the target output chip is electrically connected with the first end of the current limiting protection circuit.

As an alternative implementation manner, in the first aspect of the present utility model, the signal processing module includes a signal processing chip, where:

The first end of the signal processing chip is electrically connected with the first end of the signal input module, and the second end of the signal processing chip is electrically connected with the first end of the first switching processing module.

The first aspect of the utility model discloses a splitter comprising an input port for receiving an HDMI signal and comprising a signal splitting circuit for adaptively adjusting the gain as disclosed in the first aspect of the utility model and comprising an output port for outputting a second target signal.

Compared with the prior art, the implementation of the utility model has the following beneficial effects:

by implementing the utility model, the two switching processing modules can execute corresponding adaptive gain adjustment operation on the input HDMI signals, so that the quality and adaptive adjustment capability of the output signals are improved, one-path HDMI video signal input can be converted into multi-path HDMI video signal output, multi-path 8K video signal output can be realized, the distribution output capability and output definition of the HDMI signals are improved, and further the user experience is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a signal distribution circuit for adaptively adjusting gain according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another signal distribution circuit for adaptively adjusting gain according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a signal distribution circuit for adaptively adjusting gain according to another embodiment of the present utility model;

FIG. 4 is a schematic diagram of a signal distribution circuit for adaptively adjusting gain according to another embodiment of the present utility model;

FIG. 5 is a schematic diagram of an LED indicator circuit according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of a first processing chip according to an embodiment of the present utility model;

FIG. 7 is a schematic diagram of a first JTAG circuit according to an embodiment of the present utility model;

FIG. 8 is a schematic diagram of a first I2C circuit according to an embodiment of the present utility model;

fig. 9 is a schematic diagram of a first QSPI circuit according to an embodiment of the present utility model;

FIG. 10 is a schematic diagram of a first P_MODE circuit according to an embodiment of the present utility model;

FIG. 11 is a schematic diagram of a second processing chip according to an embodiment of the present utility model;

FIG. 12 is a schematic diagram of a second JTAG circuit according to an embodiment of the present utility model;

FIG. 13 is a schematic diagram of a second I2C circuit according to an embodiment of the present utility model;

Fig. 14 is a schematic diagram of a second QSPI circuit according to an embodiment of the present utility model;

FIG. 15 is a schematic diagram of a second P_MODE circuit according to an embodiment of the present utility model;

Fig. 16 is a schematic diagram of an AUDIO circuit according to an embodiment of the present utility model;

FIG. 17 is a schematic diagram of a control chip according to an embodiment of the present utility model;

fig. 18 is a schematic diagram of an EDID dialing circuit according to an embodiment of the utility model;

FIG. 19 is a schematic diagram of a target input chip according to an embodiment of the present utility model;

FIG. 20 is a schematic diagram of an input ESD processing circuit according to an embodiment of the present utility model;

FIG. 21 is a schematic diagram of an input DDC processing circuit according to an embodiment of the present utility model;

FIG. 22 is a schematic diagram of an input HPD processing circuit in accordance with an embodiment of the utility model;

FIG. 23 is a schematic diagram of a target output chip according to an embodiment of the present utility model;

FIG. 24 is a schematic diagram of an output ESD processing circuit according to an embodiment of the present utility model;

fig. 25 is a schematic diagram of a structure of an output DDC processing circuit according to an embodiment of the present utility model;

FIG. 26 is a schematic diagram of an output HPD processing circuit in accordance with an embodiment of the utility model;

FIG. 27 is a schematic diagram of a current limiting protection circuit according to an embodiment of the present utility model;

fig. 28 is a schematic structural diagram of a signal processing chip according to an embodiment of the present utility model;

Fig. 29 is a schematic view showing a structure of a dispenser according to an embodiment of the present utility model.

Detailed Description

For a better understanding and implementation, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that, unless explicitly specified and limited otherwise, the term "electrically connected" in the description of the present utility model and in the claims and the above-mentioned drawings should be understood in a broad sense, for example, as a fixed electrical connection, as a detachable electrical connection, or as an integral electrical connection, as a mechanical electrical connection, as an electrical connection, or as a communication between each other, as a direct connection, as an indirect connection via an intermediary, as a communication between two elements, or as an interaction between two elements. Furthermore, the terms first, second and the like in the description and in the claims of the utility model and in the foregoing figures, are used for distinguishing between different objects and not for describing a particular sequential order, and are not intended to cover any exclusive inclusion. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The utility model discloses a signal distribution circuit and a distributor capable of adaptively adjusting gain, which can improve the quality and the adaptive adjustment capability of an output signal, improve the distribution output capability and the output definition of an HDMI signal, and further facilitate improving the use experience of a user. The following will explain in detail.

Example 1

Referring to fig. 1, fig. 1 is a schematic diagram of a signal distribution circuit with adaptive gain adjustment according to an embodiment of the present utility model. The signal distribution circuit with adaptively adjusted gain shown in fig. 1 not only can adaptively adjust gain to improve quality of an output signal, but also can output multiple paths of high-resolution HDMI signals, and simultaneously support EDID management functions of the HDMI signals. As shown in fig. 1, the signal distribution circuit for adaptively adjusting gain may include a first switching processing module 101, a second switching processing module 102, and a signal output module 103, where:

The first end of the first switching processing module 101 is electrically connected to the signal input module 104, the second end of the first switching processing module 101 is electrically connected to the first end of the second switching processing module 102, and the second end of the second switching processing module 102 is electrically connected to the first end of the signal output module 103;

The first switching processing module 101 is configured to receive the target input signal transmitted by the signal input module 104, perform a first target processing operation on the target input signal, obtain a first target signal, and transmit the first target signal to the second switching processing module 102;

A second switching processing module 102, configured to perform a second target processing operation on the first target signal, obtain a second target signal, and transmit the second target signal to the signal output module 103;

And the signal output module 103 is used for transmitting the received second target signal to a preset target device.

In an embodiment of the present utility model, optionally, the first switching processing module 101 may include an in-out video switching processing module, where the in-out video switching processing module may include a GSV6502 chip with equalizer gain control and adaptively adjusting gain, and the first switching processing module 101 may be configured to connect one path of HDMI input signal, that is, the target input signal received by the first switching processing module 101 may include one path of HDMI input signal, and perform a first target processing operation on the received one path of HDMI input signal to obtain a first target signal, where the first target signal may include two paths of HDMI signals identical to the received one path of HDMI input signal. Further, the first target processing operation may include a gain adjustment operation, and may further include an input signal one-in-two-out projection operation.

In this embodiment of the present utility model, optionally, the second switching processing module 102 may include an in-out-of-four video switching processing module, where the in-out-of-four video switching processing module may include a GSV6505 chip with equalizer gain control and adaptively adjusting gain and a peripheral circuit, and further optionally, the adaptively adjusting gain signal distribution circuit may include a plurality of identical second switching processing modules 102, as shown in fig. 2, and fig. 2 is a schematic structural diagram of another adaptively adjusting gain signal distribution circuit according to an embodiment of the present utility model. Two paths of HDMI signals output by the first switching processing module 101 are processed by two second switching processing modules 102, that is, one path of HDMI signal output by the first switching processing module 101 is connected to one second switching processing module 102, a second target processing operation is performed on the path of HDMI signal to obtain four paths of output HDMI signal, the other path of HDMI signal output by the first switching processing module 101 is connected to the other second switching processing module 102, and a second target processing operation is performed on the path of HDMI signal to obtain four paths of output HDMI signal. Further, the second target processing operation may include a gain adjustment operation, and may further include an input signal one-in-four-out projection operation.

In the embodiment of the present utility model, optionally, the preset target device may include a smart phone, a smart tablet, a smart computer, a smart portable computer, a smart watch, a television, a display, a game console, and/or other devices capable of displaying video signals and/or capable of playing sound signals.

In an embodiment of the present utility model, optionally, the second target signal may include an 8K video signal.

As can be seen, the signal distribution circuit for adaptively adjusting gain described in fig. 1 receives the target input signal transmitted by the signal input module through the first switching processing module, and transmits the obtained first target signal to the second switching processing module after performing the first target processing operation on the target input signal, and performs the second target processing operation on the first target signal through the second switching processing module, and transmits the obtained second target signal to the signal output module, and transmits the second target signal to the target device through the signal output module, and performs the corresponding adaptive gain adjustment operation on the input HDMI signal through the two switching processing modules, thereby improving the quality and adaptive adjustment capability of the output signal, and being capable of converting one path of video signal input into multiple paths of HDMI video signals for output, realizing multiple paths of 8K video signal output, improving the distribution output capability and output definition of the HDMI signal, and being beneficial to improving the user experience.

In an alternative embodiment, as shown in fig. 3, fig. 3 is a schematic diagram of a signal distribution circuit for adaptively adjusting gain according to another embodiment of the present utility model. The signal distribution circuit for adaptively adjusting gain shown in fig. 3 further includes a signal processing module 105, where:

the first end of the signal processing module 105 is electrically connected to the signal input module 104, and the second end of the signal processing module 105 is electrically connected to the first end of the first switching processing module 101;

The signal processing module 105 is configured to receive the target input signal transmitted by the signal input module 104, perform a signal processing operation on the target input signal, obtain a target input signal after signal processing, and transmit the target input signal after signal processing to the first switching processing module 101.

In this alternative embodiment, optionally, the signal processing module 105 may be composed of an HDMI2.1 video processing chip PS8419 with a driver and a peripheral circuit, where the signal processing module 105 is configured to receive the target input signal transmitted by the signal input module 104, perform a signal processing operation on the target input signal, obtain a target input signal after the signal processing, and transmit the target input signal after the signal processing to the first switching processing module 101, where the signal processing operation may include gain control for compensating insertion loss of the target input signal transmitted by the received signal input module 104.

It can be seen that implementing this alternative embodiment can improve the quality and stability of HDMI signals by performing gain control on the compensated insertion loss of the received target input signal transmitted by the signal input module by the signal processing module.

In another alternative embodiment, as shown in fig. 4, fig. 4 is a schematic structural diagram of a signal distribution circuit for adaptively adjusting gain according to another embodiment of the present utility model. Wherein the signal distribution circuit for adaptively adjusting gain shown in fig. 4 further comprises a control module 106, wherein:

The first end of the control module 106 is electrically connected with the third end of the first switching processing module 101, and the second end of the control module 106 is electrically connected with the third end of the second switching processing module 102;

The control module 106 is configured to manage the operation modes of the first switching processing module 101, the second switching processing module 102, and the signal processing module 105.

In this alternative embodiment, optionally, the control module 106 may include an MCU control chip, and the electrical connection between the control module 106 and the first switching processing module 101 may include connection through an IIC bus connection, and the electrical connection between the control module 106 and the second switching processing module 102 may include connection through an IIC bus connection. The IIC, also known as Inter-INTEGRATED CIRCUIT, is a two-wire serial bus developed by Philips, inc. for connecting a microcontroller and its peripherals. The synchronous, half-duplex and bidirectional two-wire serial bus consists of two buses, namely a serial clock line SCL and a serial data line SDA. The SCL line is responsible for generating the synchronous clock pulses, while the SDA line is responsible for transmitting serial data between the devices.

In this alternative embodiment, further alternatively, the third terminal of the control module 106 is electrically connected to the first terminal of the LED indication circuit, wherein:

And the LED indication circuit is used for indicating the position of the access port of the target device accessed to the signal input module.

In this alternative embodiment, as shown in fig. 5, fig. 5 is a schematic structural diagram of an LED indicating circuit according to an embodiment of the present utility model, where components included in the LED indicating circuit and connection manners between the components may be as shown in fig. 5.

In this optional embodiment, optionally, when the signal distribution circuit for adaptively adjusting gain disclosed in the embodiment of the present utility model includes eight output ports, the signal input module includes eight output ports, each output port may be connected to a target device, and if the second output port is connected to the target device, the LED indicator corresponding to the second output port is turned on to indicate that the second output port is connected to the target device.

In this alternative embodiment, optionally, the control module 106 is configured to manage the operation modes of the first switching processing module 101, the second switching processing module 102, and the signal processing module 105 at the same time.

Therefore, the working modes of the first switching processing module, the second switching processing module and the signal processing module can be managed by the control module, the automation and the intelligence level of the circuit are improved, the first switching processing module, the second switching processing module and the signal processing module are controlled by the control module to process, map and transmit the input video signals, one-path input can be converted into multiple-path output, and the quality and the definition of the output video signals can be improved.

In yet another alternative embodiment, the first switching processing module 101 includes a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first P_MODE circuit, wherein:

The first end of the first processing chip is electrically connected with the second end of the signal processing module 105, the second end of the first processing chip is electrically connected with the first end of the second switching processing module 102, the third end of the first processing chip is electrically connected with the first end of the control module 106, the fourth end of the first processing chip is electrically connected with the first end of the first JTAG circuit, the fifth end of the first processing chip is electrically connected with the first end of the first I2C circuit, the sixth end of the first processing chip is electrically connected with the first end of the first QSPI circuit, and the seventh end of the first processing chip is electrically connected with the first end of the first P_MODE circuit.

In this alternative embodiment, as shown in fig. 6, fig. 6 is a schematic structural diagram of a first processing chip according to the embodiment of the present utility model, where components included in the first processing chip and a connection manner between the components may be shown in fig. 6.

Further, as shown in fig. 7, fig. 7 is a schematic structural diagram of a first JTAG circuit according to an embodiment of the present utility model, where components included in the first JTAG circuit and connection manners between the components may be as shown in fig. 7.

Further, as shown in fig. 8, fig. 8 is a schematic structural diagram of a first I2C circuit according to an embodiment of the present utility model, where components included in the first I2C circuit and a connection manner between the components may be as shown in fig. 8.

Further, as shown in fig. 9, fig. 9 is a schematic structural diagram of a first QSPI circuit according to an embodiment of the present utility model, where components included in the first QSPI circuit and a connection manner between the components may be shown in fig. 9.

Further, as shown in fig. 10, fig. 10 is a schematic structural diagram of a first p_mode circuit according to an embodiment of the present utility model, where components included in the first p_mode circuit and connection manners between components may be as shown in fig. 10.

In this optional embodiment, optionally, the first processing chip may map one path of input HDMI signal into two paths of output HDMI signal, that is, implement one input and two outputs, and the first processing chip may include a GSV6502 chip, where GSV6502 is an input and two outputs HDMI2.1 distributor, and this chip integrates an RISC-V based enhanced microcontroller, which is suitable for various application scenarios requiring high quality HDMI signal processing and transmission.

In this alternative embodiment, the first JTAG circuitry optionally includes JTAG circuitry, wherein the JTAG circuitry is standard test access and boundary scan circuitry designed by the joint test working group (Joint Test Action Group). JTAG circuitry is comprised of a series of hardware components, such as Test Data Input (TDI), test Data Output (TDO), etc., that are connected to and communicate through a JTAG interface, and the main functions of JTAG circuitry include chip-level testing, boundary scan, copyright protection, debugging and troubleshooting, and configuration and programming of integrated circuits. By inserting an interface on a chip pin, JTAG can detect and diagnose chip errors, support functional test, boundary scan test and code coverage test, ensure normal operation and quality control of the chip, further, all operations of JTAG circuits must be synchronized with JTAG clock signals (TCK), test controllers can send test data to a test target through the JTAG interface and receive response data from the test target to verify the functions and performances of the circuit, and in a debugging mode, the test controllers can also read and modify the internal states and registers of the test target.

In this alternative embodiment, the first I2C circuit optionally includes an I2C circuit, where the I2C circuit, collectively referred to as an Inter-INTEGRATED CIRCUIT (interconnect integrated circuit) circuit, is a hardware circuit for short-range data transfer between integrated circuits, consisting essentially of two lines, SDA (data bus) and SCL (clock bus), through which the master device can communicate bi-directionally with the slave device.

In this alternative embodiment, the first QSPI circuit may optionally include a QSPI circuit, where QSPI is Queued SPI abbreviated as a special communication interface circuit for connecting single, double or four (data lines) SPI Flash storage media, and the largest feature of the QSPI circuit is that 80 bytes of RAM is used instead of SPI transmit and receive data registers. The 80-byte RAM is divided into three parts, a 16-word transmit RAM, a 16-word receive RAM, and a 16-byte command RAM. The three parts together form a transmission queue with 16 QSPI transmission control groups, each comprising a command RAM, a transmit RAM and a receive RAM. The data length, chip selection, etc. of each QSPI transmission may be individually determined by the command RAM of the corresponding QSPI transmission control group.

In this alternative embodiment, the first p_mode circuit may optionally comprise a p_mode circuit, wherein this is a circuit having a particular MODE of operation. According to different P_MODE settings, the P_MODE circuit enters different operating states. For example, when the operation MODE corresponding to p_mode is 0, the p_mode circuit is in an internal start state, and when the operation MODE corresponding to p_mode is 1, the p_mode circuit enters a QSPI circuit start state.

Therefore, the implementation of the optional embodiment can process the signal input to the HDMI signal by the first processing chip and output the processed signal to the second switching processing module, and the first JTAG circuit, the first I2C circuit, the first QSPI circuit and the first P_MODE circuit cooperatively operate, so that one path of HDMI input signal can be processed into two paths of HDMI output signals, the design and wiring of the whole system are simplified, the hardware complexity and the cost are reduced, and meanwhile, multiple paths of HDMI high-definition signals can be output, the same content is synchronously displayed on different devices, and the user experience is improved.

In yet another alternative embodiment, the second switch processing module 102 includes a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second P_MODE circuit, and an AUDIO circuit, wherein:

The first end of the second processing chip is electrically connected with the second end of the first switching processing module 101, the second end of the second processing chip is electrically connected with the first end of the signal output module 103, the third end of the second processing chip is electrically connected with the second end of the control module 106, the fourth end of the second processing chip is electrically connected with the first end of the second JTAG circuit, the fifth end of the second processing chip is electrically connected with the first end of the second I2C circuit, the sixth end of the second processing chip is electrically connected with the first end of the second QSPI circuit, the seventh end of the second processing chip is electrically connected with the first end of the second P_MODE circuit, and the eighth end of the second processing chip is electrically connected with the first end of the AUDIO circuit.

In this alternative embodiment, as shown in fig. 11, fig. 11 is a schematic structural diagram of a second processing chip disclosed in the present utility model, where components included in the second processing chip and a connection manner between the components may be shown in fig. 11;

Further, as shown in fig. 12, fig. 12 is a schematic structural diagram of a second JTAG circuit disclosed in the present utility model, wherein components included in the second JTAG circuit and connection manners between the components may be as shown in fig. 12;

Further, as shown in fig. 13, fig. 13 is a schematic structural diagram of a second I2C circuit disclosed in the present utility model, where components included in the second I2C circuit and connection manners between the components may be as shown in fig. 13;

Further, as shown in fig. 14, fig. 14 is a schematic structural diagram of a second QSPI circuit according to the present utility model, where components included in the second QSPI circuit and connection manners between the components may be as shown in fig. 14;

Further, as shown in fig. 15, fig. 15 is a schematic structural diagram of a second p_mode circuit disclosed in the present utility model, where components included in the second p_mode circuit and connection manners between the components may be as shown in fig. 15;

Further, as shown in fig. 16, fig. 16 is a schematic structural diagram of an AUDIO circuit according to the present disclosure, where components included in the AUDIO circuit and connection manners between the components may be as shown in fig. 16.

In this optional embodiment, optionally, the second processing chip may map one input HDMI signal to four output HDMI signals, that is, implement one input and four output HDMI signals, where the second processing chip includes a GSV6505 chip, and the GSV6505 is an input and four output HDMI2.1 distributor, and this chip integrates an RISC-V based enhanced microcontroller, which is suitable for various application scenarios requiring high quality HDMI signal processing and transmission.

In this alternative embodiment, optionally, the AUDIO circuit is mainly used for processing the AUDIO signal, so as to ensure that the AUDIO signal can be clearly and accurately transmitted and played, and the main function of the AUDIO circuit is to amplify and process the sound signal, where the process of amplifying and processing the sound signal by the AUDIO circuit may include one or more of filtering, equalizing, and reverberation.

In this alternative embodiment, the second JTAG circuit may optionally include JTAG circuitry, the second I2C circuit may include I2C circuitry, the second QSPI circuit may include QSPI circuitry, and the second P_MODE circuit may include P_MODE circuitry.

Therefore, in this optional embodiment, the second processing chip is configured to process the HDMI signal received by the second switching processing module, and output the four paths of HDMI signals to the signal output module, and through the cooperative operation of the second JTAG circuit, the second I2C circuit, the second QSPI circuit, the second p_mode circuit, and the AUDIO circuit, the second processing chip is configured to convert one path of input HDMI signal into four paths of output HDMI signal, and meanwhile, the second processing chip is configured to support the output of 8K HDMI video signal, so that the processing capability of the HDMI signal can be improved, the capability of outputting multiple paths of high-quality HDMI signals can be improved, the same high-quality HDMI signal content can be synchronously displayed in different devices, and the user experience can be improved.

In yet another alternative embodiment, the control module 106 includes a control chip and an EDID dial circuit, wherein:

The first end of the control chip is electrically connected with the third end of the first switching processing module 101, the second end of the control chip is electrically connected with the third end of the second switching processing module 102, and the third end of the control chip is electrically connected with the first end of the EDID dialing circuit;

The EDID dial circuit is configured to control a signal format of the second target signal output by the signal output module 103.

In this alternative embodiment, as shown in fig. 17, fig. 17 is a schematic structural diagram of a control chip disclosed in the present utility model, where components included in the control chip and a connection manner between the components may be shown in fig. 17;

Further, as shown in fig. 18, fig. 18 is a schematic structural diagram of an EDID dialing circuit disclosed in the present utility model, where components included in the EDID dialing circuit and connection manners between the components may be as shown in fig. 18.

In this alternative embodiment, the control chip may alternatively include a GD32F330CBT6 chip with a CPU core of ARM-M4 and a storage capacity of 64 KB.

In this alternative embodiment, optionally, the control chip may be used to manage the operation modes of the first switching processing module 101, the second switching processing module 102, and the signal processing module 105 at the same time.

In this optional embodiment, optionally, the EDID dial circuit may be used to control a signal format of the second target signal output by the signal output module 103, specifically, when the pin GPIO0 of the EDID dial circuit is 1 and the pin GPIO1 is 1, the signal distribution circuit for adaptively adjusting gain is an EDID COPY mode, at this time, the EDID of the first external target device is copied, the remaining seven outputs all output signals according to the EDID of the first path, when the pin GPIO0 of the EDID dial circuit is 0 and the pin GPIO1 is 0, the signal distribution circuit for adaptively adjusting gain is EDID Compose modes, at this time, the EDID is compared, and according to the signal of the corresponding definition of the EDID adaptive output of the target device, when the pin GPIO0 of the EDID dial circuit is 0 and the pin GPIO1 are 1, the signal of 4K or 2K is fixedly output, and when the pin GPIO0 of the EDID dial circuit is 1 and the pin GPIO1 is 0, the signal of the signal distribution circuit for adaptively adjusting gain is fixedly outputting the signal of GPIO 8.

Therefore, implementing this optional embodiment can quickly respond to and accurately control the working states of each module or circuit through the control chip, response speed and control precision of the system are improved, flexibility and expansibility of the system are also enhanced, reliability of the system is improved, the whole system is more efficient, stable, reliable and flexible, various complex application requirements can be met, meanwhile, the format of the HDMI video signal output by the signal output module can be changed through the EDID dial circuit, when different display resolutions of different target devices are faced, the format of the output HDMI video signal can be adjusted according to the EDID of the target device, or the EDID of a target device connected with a certain port can be copied to serve as the format of the unified output HDMI video signal, or the format of the fixed HDMI video signal can be used for output, various resolution type devices can be adapted, flexibility and stability of the HDMI video signal output can be improved, the format of the output HDMI video signal can be changed according to the user requirements, and user experience can be improved.

In yet another alternative embodiment, the circuit further comprises a signal input module 104, the signal input module 104 comprising a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

The first end of the target input chip is electrically connected to the first end of the signal processing module 105, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

In this alternative embodiment, as shown in fig. 19, fig. 19 is a schematic structural diagram of a target input chip disclosed in the present utility model, where components included in the target input chip and connection manners between the components may be as shown in fig. 19;

Further, as shown in fig. 20, fig. 20 is a schematic structural diagram of an input ESD processing circuit according to the present disclosure, where components included in the input ESD processing circuit and connection manners between the components may be as shown in fig. 20;

further, as shown in fig. 21, fig. 21 is a schematic structural diagram of an input DDC processing circuit disclosed in the present utility model, where components included in the input DDC processing circuit and connection manners between the components may be as shown in fig. 21;

further, as shown in fig. 22, fig. 22 is a schematic structural diagram of an input HPD processing circuit disclosed in the present utility model, where components included in the input HPD processing circuit and connection manners between the components may be as shown in fig. 22.

In this alternative embodiment, the target input chip may be an hdmi_a_smd chip, and further, the target input chip may be an hdmi_rx_23p_smt_0228 chip.

In this alternative embodiment, the input ESD processing circuit optionally includes an ESD protection circuit, wherein the ESD protection circuit is a circuit design for protecting the electronic components from external electrostatic discharge. Electrostatic discharge refers to a transient high voltage discharge phenomenon due to charge imbalance that can cause irreversible damage to sensitive electronic devices. The ESD protection circuit is designed to direct the energy of the external electrostatic discharge to a safe place, avoiding damage to the electronic equipment.

In this alternative embodiment, the input DDC processing circuitry may optionally include DDC processing circuitry, where DDC processing circuitry is an abbreviation for digital down conversion (Digital Downconverter) processing circuitry, which is used in the communication system to mix with a sinusoidal signal (local oscillator) generated by a local oscillator, thereby changing the frequency band in which the signal is located. Specifically, the increasing frequency is up-converting and the decreasing frequency is down-converting. The DDC processing circuit comprises at least one pull-up resistor, wherein the pull-up resistor is a resistor device and mainly used for pulling a certain signal pin to be high, so that the signal is kept in a high-level state. The pull-up resistor is usually used together with the pull-down resistor, so that signal transmission and logic functions of a circuit can be controlled, further, the input signal of the video input chip is maintained at a high level of the signal through the pull-up resistor, bad level of the signal can be avoided, the accuracy and reliability of the input signal can be guaranteed, and the driving capability of the video input chip can be improved.

In this alternative embodiment, the input HPD processing circuit may alternatively include an HPD input level conversion circuit, wherein the HPD input level conversion circuit is a circuit dedicated to processing an HPD (high voltage discharge) signal, and the main function thereof is to convert the level of the input HPD signal into a range suitable for subsequent circuit processing. For example, if the voltage corresponding to the device accessed by the video input chip is 5V and the operating voltage corresponding to the video input chip is 3.3V, the voltage corresponding to the device accessed by the video input chip is not matched with the voltage corresponding to the video input chip, the level conversion operation is performed by the HPD conversion submodule, so that the voltage corresponding to the device accessed by the video input chip is converted into the voltage corresponding to the video input chip of 3.3V, thereby ensuring the normal operation of the chip and preventing the chip from being damaged by high voltage.

In this alternative embodiment, alternatively, for example, the HDMI input signal is collected by the target input chip, and the electrostatic protection operation is performed on the target input chip by the input ESD processing circuit to prevent external static electricity from entering the target input chip and damaging the target input chip, and the driving capability of the target input chip is improved by the input DDC processing circuit, and the level conversion operation is performed by the input HPD processing circuit, so that the target input chip can be effectively protected from chip damage due to external high voltage.

Therefore, implementing this alternative embodiment can collect HDMI input signals through the target input chip in the signal input module, and improve the driving capability of the target input chip through the input DDC processing circuit, and eliminate the influence of the outside on the target input chip through the input ESD processing circuit, and perform level conversion operation through the input HPD processing circuit, can effectively improve the driving capability of the target input chip through the input DDC processing sub-module, and is favorable to improving the stability and high quality of HDMI input signals in the data transmission process, and can reduce signal attenuation and distortion when transmitting in long distance or complex environment, thereby improving the performance of the whole system, and can effectively absorb and disperse the energy of electrostatic discharge through the input ESD processing circuit, protect the target input chip from damage, improve the stability and reliability of the device, and can help to ensure that signals between different modules can be correctly matched and transmitted, avoid signal distortion or error caused by level mismatch, wherein the level conversion is a key step in the circuit design, it can make the whole system more flexible and favorable to improving the stability and the compatibility of the target chip, and the realization of the input accuracy and the reliability of the whole system, and the realization of the input accuracy and the reliability, and the realization of the high-accuracy and the reliability of the input system, and the realization of the high-performance, and the high-accuracy and the reliability of the input-quality.

In yet another alternative embodiment, signal output module 103 includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limit protection circuit, wherein:

The first end of the target output chip is electrically connected with the second end of the second switching processing module 102, the second end of the target output chip is electrically connected with the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected with the first end of the output DDC processing circuit, the fourth end of the target output chip is electrically connected with the first end of the output HPD processing circuit, and the fifth end of the target output chip is electrically connected with the first end of the current limiting protection circuit.

In this alternative embodiment, as shown in fig. 23, fig. 23 is a schematic structural diagram of a target output chip disclosed in the present utility model, where components included in the target output chip and connection manners between the components may be shown in fig. 23;

Further, as shown in fig. 24, fig. 24 is a schematic structural diagram of an output ESD processing circuit according to the present disclosure, where components included in the output ESD processing circuit and connection manners between the components may be as shown in fig. 24;

Further, as shown in fig. 25, fig. 25 is a schematic structural diagram of an output DDC processing circuit disclosed in the present utility model, where components included in the output DDC processing circuit and connection manners between the components may be as shown in fig. 25;

further, as shown in fig. 26, fig. 26 is a schematic structural diagram of an output HPD processing circuit disclosed in the present utility model, where components included in the output HPD processing circuit and connection manners between the components may be as shown in fig. 26;

Further, as shown in fig. 27, fig. 27 is a schematic structural diagram of a current limiting protection circuit disclosed in the present utility model, where components included in the current limiting protection circuit and connection manners between the components may be as shown in fig. 27.

In this alternative embodiment, the current limiting protection circuit may optionally comprise a current limiting short circuit protection circuit, wherein the current limiting short circuit protection circuit is an electronic protection circuit, wherein it is intended to limit the current and provide protection in case of a short circuit, further wherein the basic principle of the current limiting short circuit protection circuit is to monitor the magnitude of the current and trigger a protection measure when the current exceeds a certain threshold, further wherein the specific protection measure may comprise one or more of switching off the power supply, reducing the output voltage, limiting the current to be operable to prevent damage to the circuit caused by excessive current caused by the short circuit.

In this alternative embodiment, the target output chip may be an hdmi_a_smd chip, and further, the target output chip may be an hdmi_rx_23p_smt_0228 chip.

In this alternative embodiment, optionally, the second target signal is transmitted to the preset target device through the target output chip, the driving capability of the target output chip is improved through the output DDC processing circuit, and the level conversion operation is performed on the level signal corresponding to the output DDC processing circuit and the level signal corresponding to the output ESD processing circuit according to the output HPD processing circuit, so that the levels of the electronic components are balanced with each other, the target output chip can be effectively protected from being damaged due to external high voltage, and the phenomenon that the target output chip is burnt out due to short circuit can be prevented through the current limiting protection circuit.

It can be seen that implementing this alternative embodiment enables the second target signal to be transmitted to the preset target device through the target output chip, and improves the driving capability of the target output chip through the output DDC processing circuit, performs level conversion operation on the level signal corresponding to the output DDC processing circuit and the level signal line corresponding to the output HPD processing circuit through the output HPD processing current, eliminates the influence of static electricity on the target output chip through the output ESD processing circuit, prevents the target output chip from being shorted and thus burning out the chip through the current limiting protection circuit, can significantly improve the driving capability of the target output chip through the output DDC processing circuit, is beneficial to enabling the video signal to be transmitted to the target device more stably and more efficiently, and not only realizes conversion of the output level signal of the output DDC processing circuit through the output HPD processing circuit, meanwhile, the level signal of the output ESD processing circuit is processed, thus ensuring the accuracy and the integrity of the signal through double level conversion, leading the whole system to be suitable for various different devices or interfaces, greatly improving the compatibility, providing effective electrostatic protection for a target output chip through the output ESD processing circuit, preventing the external static from negatively affecting the video output chip, and once the short circuit condition is detected through the current limiting protection circuit, the circuit can rapidly cut off or limit the current, avoiding irreversible damage to the chip and other related components, thereby optimizing the transmission and the processing of HDMI signals, strengthening the protection mechanism of the system, leading the system to be stably and safely operated when facing various challenges, further realizing the improvement and the protection of the performance of the target output chip, and improving the stability and the reliability of the whole system, and further, the performance of the target output chip is improved and protected, and meanwhile, the stability and the reliability of the whole system are improved, so that the accuracy, the reliability and the intelligence for realizing the self-adaptive gain adjustment are improved.

In yet another alternative embodiment, the signal processing module 105 comprises a signal processing chip, wherein:

The first end of the signal processing chip is electrically connected to the first end of the signal input module 104, and the second end of the signal processing chip is electrically connected to the first end of the first switching processing module 101.

In this alternative embodiment, as shown in fig. 28, fig. 28 is a schematic structural diagram of a signal processing chip disclosed in the present utility model, where components included in the signal processing chip and a connection manner between the components may be shown in fig. 28.

In this alternative embodiment, the signal processing chip may alternatively be HDMI2.1 video processing chip PS8419 with a driver.

It can be seen that implementing this alternative embodiment can improve the quality and stability of HDMI signals by performing gain control on the compensated insertion loss of the received target input signal transmitted by the signal input module through the signal processing chip.

Example two

Referring to fig. 29, fig. 29 is a schematic view of a dispenser according to an embodiment of the utility model. The divider shown in fig. 29 includes a signal dividing circuit for adaptively adjusting gain as in any one of the first embodiments. The signal distribution function of the self-adaptive gain adjustment which can be realized by the distributor comprises, but is not limited to, self-adaptive gain adjustment so as to improve the quality of output signals, one path of HDMI video signal input is converted into multiple paths of HDMI video signal output, multiple paths of 8K video signal output is realized, the distribution output capacity and the output definition of HDMI signals are improved, and further the user experience is improved. It should be noted that, for the message description of the distributor, please refer to the specific description of the related content in the first embodiment, and the description is omitted herein.

Therefore, implementing the distributor described in fig. 29 can adapt to the adjustment gain to improve the quality of the output signal, convert one path of HDMI video signal input into multiple paths of HDMI video signal output, realize multiple paths of 8K video signal output, and improve the distribution output capability and output definition of HDMI signals, thereby being beneficial to improving the user experience.

While the foregoing has been described in detail with respect to the exemplary embodiments of the present utility model, the principles and implementations of the present utility model have been described in detail with reference to specific embodiments thereof, which are not intended to limit the utility model, but are merely illustrative of the methods and concepts of the present utility model, and variations in terms of the specific implementations and applications may be made by those of ordinary skill in the art in light of the teachings of the present utility model without departing from the spirit or scope thereof, and the scope of the utility model is defined in the appended claims.

Claims

1. A signal distribution circuit for adaptively adjusting gain, the circuit comprising a first switching processing module, a second switching processing module, and a signal output module, wherein:

2. The adaptively gain-adjusted signal distribution circuit of claim 1, further comprising a signal processing module, wherein:

3. The adaptively gain-adjusted signal distribution circuit of claim 2, further comprising a control module, wherein:

4. The adaptive gain-adjusted signal distribution circuit of claim 3 wherein the first switching processing module comprises a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first p_mode circuit, wherein:

5. The adaptive gain-adjusted signal distribution circuit of claim 3 or 4, wherein the second switching processing module comprises a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second p_mode circuit, and an AUDIO circuit, wherein:

6. The adaptive gain-adjusted signal distribution circuit of claim 3 or 4, wherein the control module comprises a control chip and an EDID dial circuit, wherein:

7. The adaptive gain-adjusted signal distribution circuit of any of claims 2-4, further comprising the signal input module comprising a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

8. The adaptive gain-adjusted signal distribution circuit of any of claims 1-4, wherein the signal output module comprises a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, wherein:

9. The adaptive gain-adjusted signal distribution circuit of claim 7, wherein the signal processing module comprises a signal processing chip, wherein:

10. A splitter comprising an input port for receiving an HDMI signal and comprising a signal splitting circuit for adaptively adjusting gain as in any one of claims 1-9, and comprising an output port for outputting a second target signal.